From nobody Mon Sep 28 19:24:41 2026 Received: from out203-205-221-221.mail.qq.com (out203-205-221-221.mail.qq.com [203.205.221.221]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E85B2F12AC for ; Tue, 18 Aug 2026 13:22:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.205.221.221 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787059369; cv=none; b=ChuCoxm2vAbymg8IjmQmlA/btqN9ngjeONr06asgLgcMnzaxbJnJoYh5GvEVy/fqA2spxwOyGjZhTryZoPZ8OBttx+IEHmMAcj9pGOSV4PYsD6YFRRY6a2SsEkGpAjijiXFsg7uAvQyWPr+dbpDisFcG+/WA7Z7QxUnMw+utMNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787059369; c=relaxed/simple; bh=/5sKh03+LQmXwvMnQ5agEB5mfk7rDWqcBeH1PEEwh+g=; h=Message-ID:From:Subject:To:Date; b=GDnJynSw+uLyW6lJntxFogFvc2wSoQM3vKFdsFaAO7HvDlFIyvHvX6RXqkvzRP5SqGS/y7/tFKRGFyYVMm/2pc2DqTWcDHFnrOFpwO4ktDshOziSF/2/tTagm8I7+PWGLW+GgRlRgBJQnpPH35GQ84+mtmyjBMN3c7WbepOikkk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=qq.com; spf=pass smtp.mailfrom=qq.com; dkim=pass (1024-bit key) header.d=qq.com header.i=@qq.com header.b=SS5tZDu8; arc=none smtp.client-ip=203.205.221.221 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=qq.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qq.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=qq.com header.i=@qq.com header.b="SS5tZDu8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qq.com; s=s201512; t=1787059363; bh=kcg/VpsEsEhvDBR2wFVPEe6e4HtfXO+m5leMiIe6dx4=; h=From:Subject:To:Date; b=SS5tZDu8hDvQBQvCsrOKCP5JFNknhk82ZHzQLwO0cCSPX9XA+5JqDk2V6v30Y/2ry qKL+Wz+u5p3SKfMeGtZZbRb2L/jMGonGhXLL4g0q5WRPzZ2ZWESUkZ/GEm9Q26dg3L SLNdnfVTk5/1AnrkDILDWIJgnk/E1iG6CTdYCZ0g= Received: from [127.0.1.1] ([5.195.0.150]) by newxmesmtplogicsvrsza63-0.qq.com (NewEsmtp) with SMTP id 1721C6D8; Tue, 18 Aug 2026 21:05:50 +0800 X-QQ-mid: xmsmtpt1787059270todi280c8 Message-ID: X-QQ-XMAILINFO: MFkgsonL4eTus6TEoug5APrlpO0T8uodIWRsEjz9yhvlX/LKLLBbfGPzZXiw1d 7zcM0NuOO3Zztut+A4eTyD4FkMIu9wEdH//seWNq+Eu3Nv9OHbNkbprpa8zwsFAuWIg1qL3VWeFH tmlcFIl9771njUF6Y5siBWBda9nBu4f274b9jMwP/QEi1B4obp0RIB5TUYdH4fYWBQ0gCVsdSErA T5TatQiuHrlRfQA9nTpjvuL9wnT/o/W0zpYd1OIJnZIFhTpox7maWxzzD7N2SA6ChfyuZPPGJSgt GNbjW7GzeLNBNOcEAiG7U0GsITOzprHozTdQ+72uf6o+iRAuJby8e/QKju9CDDvQkiC3ZeG053q2 h8XWF33BLOsw4L9oCwiCJP7oCOb5dTN9lLUu4y2ol0bueFuhlvrWGqabFyVUgyW9Can1jWR4oeDo 1PUV9bQYf0q2MDdH7puvkwVwU782G+ZFkyhDU0p5BkPh5tlsRkVYi/Qb7NhkHkrkFeNNg279fXLL Cbo00r9u5eJMyRHaqZoMwKyDOg7GasEVg1HKpQCPRIq4FFZSoFv8+v/n9UPWPjkt0rDiWREGoWNK J1ib26m7Jb3uUd2EA0RFJartQQt2z33vS6uNMFJX7RD8foJcn5KAXfcLlrlqGjPiQBCGFwn4k/IS kR3cR8aKnpolzpQI7p/nLLL74Ew+qerixfYvb1y5lYL90NnkYljfDxQMywmbJ+3OtIrJVLrZIGUX Vi9bv9+Ues7lwrJGo7hcP3u/ZiiJkeiCIhX8FjHE/uaiDwkH0gX+srHZzAZkU2DEIl7R/HeYrpxL 9kYQYzp42aZuA7LWsbzsltB8uuB29MG+TaiYTxOfIlQ7bCgCXId8AfB/8DwTRrPN1qJ5FtHyAW/g X0K9d09ki+p2r+tWIepHYUYKLcyEV9H9GSK5R0R3irosxZn/W1IaaEIXR0eMP7g9SDpyHBlFK7j8 dUy2uSTWlbtQy9rL8AXZSUorJe/vpA2GsqWeDqMq3wMTbX635oVzxl9uPU/7iYfKGlYlJKEpOvaz kf+ELsQiLE6bP2836HuKB/Ijh+BL/RY7Cf3yw5fgpi9TYV47R9qvltyo44UBFTz+qJE0YqXw== X-QQ-XMRINFO: MSVp+SPm3vtSI1QTLgDHQqIV1w2oNKDqfg== From: Jiawen Liu <1298662399@qq.com> Subject: [PATCH] misc: atmel-ssc: handle clock enable failure To: Claudiu Beznea , Andrei Simion , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Tue, 18 Aug 2026 17:22:40 +0400 X-OQ-MSGID: <178705936098.291840.14459285014555134889@qq.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Return error from failed clock enable. ssc_probe ignores clk_prepare_enable return before register writes and unconditional disable_unprepare. Unchecked prepare/enable may be unprepared on failure. Check temporary pclk enable before SSC register access in ssc_probe. Signed-off-by: jiawen <1298662399@qq.com> --- diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c --- a/drivers/misc/atmel-ssc.c +++ b/drivers/misc/atmel-ssc.c @@ -192,6 +192,7 @@ struct resource *regs; struct ssc_device *ssc; const struct atmel_ssc_platform_data *plat_dat; + int ret; =20 ssc =3D devm_kzalloc(&pdev->dev, sizeof(struct ssc_device), GFP_KERNEL); if (!ssc) { @@ -225,7 +226,9 @@ } =20 /* disable all interrupts */ - clk_prepare_enable(ssc->clk); + ret =3D clk_prepare_enable(ssc->clk); + if (ret) + return ret; ssc_writel(ssc->regs, IDR, -1); ssc_readl(ssc->regs, SR); clk_disable_unprepare(ssc->clk);