From nobody Thu Dec 18 04:44:39 2025 Received: from out203-205-221-205.mail.qq.com (out203-205-221-205.mail.qq.com [203.205.221.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C291A3E487; Sun, 16 Jun 2024 17:21:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.205.221.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558485; cv=none; b=mepGkBJS+LMlkhcVATS+uWyMvRg2rGjDJXiRvI8bdVu0jyVAPpxVsDtnQkw9p0hBnq3tC7Ay7Fq2U0uYDQqQxFPDp+osQrJEMH5afNpq+fUuYQMLjxqDz0lska2SodXOuuUerH7kV2oJV6z5VqolU9yd9rnsi0QA1WzY+3/B3Ak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558485; c=relaxed/simple; bh=g7ZIISHaCV5KlxvWKNY9HmAzINGpgn0ujIvqCO6gef0=; h=Message-ID:From:To:Cc:Subject:Date:In-Reply-To:References: MIME-Version; b=HHypkbFYRf8ERaptqSQahG8jvQgcV05dtW0WFTjxz9aa1Km2OAZW2ZotKLwJfbk0laHLXazNwS2Ploa4rElRL7mVJqrtAoTBUHMnDb6fpefXymHH1KFAwZYydYST5cnZ977ER96n6cnPPdM6mvZvAKm9XnPLEL23N6TAxbbK0E8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cyyself.name; spf=none smtp.mailfrom=cyyself.name; dkim=pass (1024-bit key) header.d=qq.com header.i=@qq.com header.b=xHvXW48/; arc=none smtp.client-ip=203.205.221.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cyyself.name Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cyyself.name Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=qq.com header.i=@qq.com header.b="xHvXW48/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qq.com; s=s201512; t=1718558478; bh=kffuiBy/CIyYVVV2x3157+XUp0m7JniF2uMW07+odRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=xHvXW48/FBDGhkl1LcYggxvVUj3u1ePlchhICTv5kuWnTURUcLZvuYUJQ3vQPRedH J7+F3g9qwU7cSmDpzRKK99Giz/voZp558AHPNAA3Z6U7FSgbS7G1KuEkZaTxR0D/5Z Xz2tBTBlCu9ioSRKvSLYDIWlTgUUOjdBZmX2yYb0= Received: from cyy-pc.lan ([240e:379:2260:ed00:cd33:e8cf:d8f9:bed3]) by newxmesmtplogicsvrszb9-0.qq.com (NewEsmtp) with SMTP id 5452D659; Mon, 17 Jun 2024 01:21:05 +0800 X-QQ-mid: xmsmtpt1718558476t9biaj28z Message-ID: X-QQ-XMAILINFO: OGZxhFXqN7PJ92jmdY2jgaFTkXMgqsMLVgpuozoE3xsnroHOp0n8VSKkDWRowp PkAC4YFiCS0vhKK6I0vinYJ1GbnqCkUH0vYUPHch4eq2ubOI+NJUykVYAwFfRQ4Vb9UQ0Ld5axj6 9iZyipQpsuLsDFZqbbUKueaJ7a/oHZIGAhRNibu9b4POBpGAjeNECgU6xh58Rt88kkhXzeWHAH+x aYiC/WAO/s0QF+NtGsETjuPpcSXmmLC0Y5l7AsHB5sfd2qKeJqatPJvXSssU5MUJcM2QKl25YRGk POlWuG35sj3BJ1WwrCda5x+GZiRVRP+Fz0/PgyufqQs7tznm+8FgfNEMqMurwtYe694tLpNDaLWK 9AxqXZH7dDRkQRqjmDE5pI0xq3k37afn0GzEE3omDdcjdj7Bla5U0KTA9Slh38awqAGcDBNdkxhL HhRFbwSyRoXWIJ8jeAXG5ffJe0k7IparxoCNx+4m6pRTOUbu5bcOvX8Cm1rTJ6q9NC8uCPCM7/uH GwB+/5bgL5zl6arfrnRq+OjS9Qu5IAWoJeHKHl4GOtkgkRGZ1rCiG/KRAEFG/+8pikYkHDeCzaij 32ckD3OX6pW3W5DMv0jQgXdUfgMkrdot5qYyTXu1wtEIGPiHUi2viV0gK/r5M44pQTPpmthhOmZc hbeP3+eFPyyzmeFNBiiivCOZuT2/Fgo1g/Ynp0C+Ak31HamSyn+qTx2UXEA4ezra+zmR4ihrOFxs rkhnPVUTJuEeIN1m052gWPCWqUPQgZdIh/Ay9fB4guBZ2AhoIxrFnW2CyBc3P0JzCvNLhlgLc9AS 2PhHiz3z26pguNF6GurWnYy98IEJA1rpjRbVnOmCFz9vUwdQJIIszKqZLB2KHi69oMK0xcniL5NL gA7OJDVCs0uE6Pv3rg+VNrxnkp8YP3DmJo4BAsjUzFD595gFy0ueXwTchvvIWCLoNQIbR+93QMdA hQvGYFDqIhGHrxxJFKO/XAytbw9s2hOorfhf5VqnAeTEEbICHBHUQfKzOAUonQbZu08s4PHeP+OE Com6Gu2HqQlepV6WnNjzKBTymiKGc= X-QQ-XMRINFO: M/715EihBoGSf6IYSX1iLFg= From: Yangyu Chen To: linux-riscv@lists.infradead.org Cc: Conor Dooley , Palmer Dabbelt , Paul Walmsley , Samuel Holland , Anup Patel , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yangyu Chen Subject: [PATCH v1 7/9] riscv: dts: add initial SpacemiT K1 SoC device tree Date: Mon, 17 Jun 2024 01:20:52 +0800 X-OQ-MSGID: <20240616172054.3074948-7-cyy@cyyself.name> X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1]. Key features: - 4 cores per cluster, 2 clusters on chip - UART IP is Intel XScale UART Some key considerations: - ISA string is inferred from vendor documentation[2] - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3] - No coherent DMA on this board Inferred by taking vendor ethernet and MMC drivers to the mainline kernel. Without dma-noncoherent in soc node, the driver fails. - No cache nodes now The parameters from vendor dts are likely to be wrong. It has 512 sets for a 32KiB L1 Cache. In this case, each set is 64B in size. When the size of the cache line is 64B, it is a directly mapped cache rather than a set-associative cache, the latter is commonly used. Thus, I didn't use the parameters from vendor dts. Currently only support booting into console with only uart, other features will be added soon later. [1] https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [2] https://developer.spacemit.com/#/documentation?token=3DBWbGwbx7liGW21kq= 9lucSA6Vnpb [3] https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot= /dts/spacemit/k1-x.dtsi Signed-off-by: Yangyu Chen --- arch/riscv/boot/dts/spacemit/k1.dtsi | 281 +++++++++++++++++++++++++++ 1 file changed, 281 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k1.dtsi diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi new file mode 100644 index 000000000000..58f9e143c659 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +/dts-v1/; +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SpacemiT K1"; + compatible =3D "spacemit,k1"; + + aliases { + serial0 =3D &uart0; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <10000000>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_0>; + }; + core1 { + cpu =3D <&cpu_1>; + }; + core2 { + cpu =3D <&cpu_2>; + }; + core3 { + cpu =3D <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_4>; + }; + core1 { + cpu =3D <&cpu_5>; + }; + core2 { + cpu =3D <&cpu_6>; + }; + core3 { + cpu =3D <&cpu_7>; + }; + }; + }; + + cpu_0: cpu@0 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_1: cpu@1 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_2: cpu@2 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_3: cpu@3 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_4: cpu@4 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <4>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_5: cpu@5 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <5>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_6: cpu@6 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <6>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu_7: cpu@7 { + compatible =3D "spacemit,x60", "riscv"; + device_type =3D "cpu"; + reg =3D <7>; + riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + ranges; + + plic: interrupt-controller@e0000000 { + compatible =3D "spacemit,k1-plic", "riscv,plic0"; + reg =3D <0x0 0xe0000000 0x0 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + riscv,ndev =3D <159>; + }; + + clint: timer@e4000000 { + compatible =3D "spacemit,k1-clint", "riscv,clint0"; + reg =3D <0x0 0xe4000000 0x0 010000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + uart0: serial@d4017000 { + compatible =3D "intel,xscale-uart"; + reg =3D <0x0 0xd4017000 0x0 0x100>; + interrupts =3D <42>; + clock-frequency =3D <14000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + }; +}; --=20 2.45.1