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([171.213.183.153]) by newxmesmtplogicsvrszc43-0.qq.com (NewEsmtp) with SMTP id CC618E70; Wed, 04 Mar 2026 10:51:06 +0800 X-QQ-mid: xmsmtpt1772592666tyf59obfk Message-ID: X-QQ-XMAILINFO: MDbayGdXPuoe5nxAnpEvlvbqcXsAZ419e0Z7oJTzqrjjArfZ0QJjmLnqaFoOQk NkS7blso9VHP18LBznt5yvjU+F5kYJFgIv54fBgiDOA5EQd4nxb5OwWwKWc8wc3T58SvBCxnHblC 8vyLzX66At9JMAUHe5cqF5gEUYe+F4h+d1LRUers5Z/jhencsJlVMDI5XfSFvuZnhZI6H8b7YfA/ I/Lzg6DSYgH2iddqIVGarnb9XTI6NmCUtD9zvz5YLhN8Mmt8PsUqRTH7B5xAw0cSKbWPHUTLW5/+ gAIRtO13+xHylLytmkIkl9qvKfMUEn304Ws9eKqJBl6oPUQs7YNdhUFNtA8eFARlRdgAt3F+2NM+ ILnz3tPylD1glT6kQ711K811kmdmJBZj06ygbyu5CB71miQfTcP5GpC6asOed205OLx08G/gZknG 6NQlzOrKkGd5xqSJ2DOaWi8LaSX7WeEYNWVB94MuXybAzjfxJnlJSNvUX3LM8vwL+qCRpw2NWFFK 5OvuGc/6tW9EdQ7ORCpS5XMUqNMfleu9EpBdI+EKnUJKVV9QFFNmTTva67Lrub4/gxNjgXpoG6Rw ZfXyf8nZ2WD53RLjTb/rclUja/XjJUAbtF7IeiledjBRwHMVIB+vty4YT5svtnc1H0mog7ZlsHXK iO58GubQ2FGHJ/po6iiWjk/HsljtEAJkDgXJ7wMyrnmBkTsHulwhtnB8XwW5FRAvB7E/mFaV1Z6C 9ako6DOK1Hr5uND0XUVYGJ8ktBEmM6jOQUoOoTKmNO5Q7bGCib/9u4TfOy8KSthUilpXSZyWVAFQ qKotk/FWEvbeF/2DRbZVtdADZuL/ZaUZb4Z8DbXXaLzr6IqpblBeg68WMfYEtZzAaOLTLgqNOHr0 4p8y/RKqAtsVQk2bh1+DHXZ5vjfJGbFmampY4ChfDDQp4nLNkJpA3Ve3n1f86iNO+XQJKyTsnHWi d0eDgh5rN93WtPM/ipncK2M1rq0mvBRXBFQHcMGlico1ACz5j8ObEk+Mlzc43I3M/OsShhIDl8Al 9YERlfwC4sUzRWTv6MMqzsHVyse1k9glWuUJqN/vDL41QW0j8XQVpIXpxc2+acKTVzdbiCBA== X-QQ-XMRINFO: MSVp+SPm3vtSI1QTLgDHQqIV1w2oNKDqfg== From: LUO Haowen To: Manivannan Sadhasivam Cc: Vinod Koul , Frank Li , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, LUO Haowen Subject: [PATCH] dmaengine: dw-edma: Fix multiple times setting of the CYCLE_STATE and CYCLE_BIT bits for HDMA. Date: Wed, 4 Mar 2026 10:50:49 +0800 X-OQ-MSGID: <20260304025049.324220-1-luo-hw@foxmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Others have submitted this issue (https://lore.kernel.org/dmaengine/ 20240722030405.3385-1-zhengdongxiong@gxmicro.cn/),=20 but it has not been fixed yet. Therefore, more supplementary information=20 is provided here. As mentioned in the "PCS-CCS-CB-TCB" Producer-Consumer Synchronization of "DesignWare Cores PCI Express Controller Databook, version 6.00a": 1. The Consumer CYCLE_STATE (CCS) bit in the register only needs to be=20 initialized once; the value will update automatically to be=20 ~CYCLE_BIT (CB) in the next chunk. 2. The Consumer CYCLE_BIT bit in the register is loaded from the LL=20 element and tested against CCS. When CB =3D CCS, the data transfer is=20 executed. Otherwise not. The current logic sets customer (HDMA) CS and CB bits to 1 in each chunk while setting the producer (software) CB of odd chunks to 0 and even=20 chunks to 1 in the linked list. This is leading to a mismatch between=20 the producer CB and consumer CS bits. This issue can be reproduced by setting the transmission data size to exceed one chunk. By the way, in the EDMA using the same "PCS-CCS-CB-TCB" mechanism, the CS bit is only initialized once and this issue was not=20 found. Refer to=20 drivers/dma/dw-edma/dw-edma-v0-core.c:dw_edma_v0_core_start. So fix this issue by initializing the CYCLE_STATE and CYCLE_BIT bits=20 only once. Signed-off-by: LUO Haowen --- drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4fe..ce8f7254b 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -252,10 +252,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chun= k *chunk, bool first) lower_32_bits(chunk->ll_region.paddr)); SET_CH_32(dw, chan->dir, chan->id, llp.msb, upper_32_bits(chunk->ll_region.paddr)); + /* Set consumer cycle */ + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); } - /* Set consumer cycle */ - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); =20 dw_hdma_v0_sync_ll_data(chunk); =20 --=20 2.34.1