From nobody Thu Dec 18 22:17:10 2025 Received: from mx0a-00823401.pphosted.com (mx0a-00823401.pphosted.com [148.163.148.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72C58156F37; Tue, 18 Jun 2024 14:41:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.148.104 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718721680; cv=none; b=XTbWEyNZe1UQN4jstFKKhXAzOjnhMkKjMvDQKIRSulltSZezDm/LXMXC4dhvAsjfHaU7gvJ1JTpI1KQ9kfLamnuQKA7VOXGakFkMMHYtZqX/kmto7+tuMEBo3FoqneGtnCkWbCtSelPrZ3k2VMriX9GzwwtDGkkPEbgsVWkRrfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718721680; c=relaxed/simple; bh=CPQMyVIALDnBNqUQ2z8TZ/GHAz+p3phcifIvMGM9M0o=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=lUR5SnAHo65fe2wv9TphvqFqb1SMvmGn6TY+8vWy+RHVNFP77dew3GMGSbPsGdN+fnwh9XVZh0fiWntPY/yfocEm+g7mq4G7d2mBZ9YKOCEktbB34KN+3aKw9uLaobn8yGqrgENigNDnS1evdK52Z/crmcmbZ7uBxxm4XfAX0Uc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motorola.com; spf=pass smtp.mailfrom=motorola.com; dkim=pass (2048-bit key) header.d=motorola.com header.i=@motorola.com header.b=Nj+tV39+; arc=none smtp.client-ip=148.163.148.104 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motorola.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=motorola.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=motorola.com header.i=@motorola.com header.b="Nj+tV39+" Received: from pps.filterd (m0355085.ppops.net [127.0.0.1]) by mx0a-00823401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45IEd3JS008967; Tue, 18 Jun 2024 14:40:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=motorola.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=DKIM202306; bh=ZiQ3f8xQzS9FA6BEFRuceTM lsKV6Mo9WAxwHVPxN0eM=; b=Nj+tV39+SFug10BoWEz7cWUgnPrs8dviGW7cYFp rc027YAqKCrb2WHJt+ThlffX5PYRm+OOfe0W3OPjbymBFOhAtI0WxunWcy4QQn+E AFPOTjwIjDPEsNZRV5XfBP9Ny4zIBGMcfELvz8Ay0TjZI9NJKnDtSuu2r+sbQTS9 HVvk3qcC6+GpXP6HAc6XcrGIR8yV/plDi3IIGpskek1twpsq633RplwxmH7tjbJA PJNTjIcJRbB0EC7k7bGMOKdunPR8k1ui+QPJnCH0jNuanamr94vooF6oBPIFapRn x/ofVlZu1aEh58PZTC5jvZBcR7HrAj2A9AbpyC+vIfqPuhg== Received: from va32lpfpp02.lenovo.com ([104.232.228.22]) by mx0a-00823401.pphosted.com (PPS) with ESMTPS id 3yssffxjhq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Jun 2024 14:40:51 +0000 (GMT) Received: from ilclmmrp02.lenovo.com (ilclmmrp02.mot.com [100.65.83.26]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by va32lpfpp02.lenovo.com (Postfix) with ESMTPS id 4W3TvQ06ymz50TkT; Tue, 18 Jun 2024 14:40:50 +0000 (UTC) Received: from ilclasset02 (ilclasset02.mot.com [100.64.49.13]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: mbland) by ilclmmrp02.lenovo.com (Postfix) with ESMTPSA id 4W3TvP5ry1z3p6jp; Tue, 18 Jun 2024 14:40:49 +0000 (UTC) Date: Tue, 18 Jun 2024 09:40:48 -0500 From: Maxwell Bland To: linux-mm@kvack.org Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Ard Biesheuvel , Mark Rutland , Christophe Leroy , Maxwell Bland , Alexandre Ghiti , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] arm64: non leaf ptdump support Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: kmBwrD3JLnyF3RFV3h1ScHXshTVxVoVj X-Proofpoint-GUID: kmBwrD3JLnyF3RFV3h1ScHXshTVxVoVj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 mlxscore=0 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=914 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406180110 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Separate the pte_bits used in ptdump from pxd_bits used by pmd, p4d, pud, and pgd descriptors, thereby adding support for printing key intermediate directory protection bits, such as PXNTable, and enable the associated support Kconfig option. Signed-off-by: Maxwell Bland --- arch/arm64/Kconfig | 1 + arch/arm64/mm/ptdump.c | 140 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 125 insertions(+), 16 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 5d91259ee7b5..f4c3290160db 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -98,6 +98,7 @@ config ARM64 select ARCH_SUPPORTS_NUMA_BALANCING select ARCH_SUPPORTS_PAGE_TABLE_CHECK select ARCH_SUPPORTS_PER_VMA_LOCK + select ARCH_SUPPORTS_NON_LEAF_PTDUMP select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT select ARCH_WANT_DEFAULT_BPF_JIT diff --git a/arch/arm64/mm/ptdump.c b/arch/arm64/mm/ptdump.c index 6986827e0d64..8f0b459c13ed 100644 --- a/arch/arm64/mm/ptdump.c +++ b/arch/arm64/mm/ptdump.c @@ -24,6 +24,7 @@ #include #include #include +#include =20 =20 #define pt_dump_seq_printf(m, fmt, args...) \ @@ -105,11 +106,6 @@ static const struct prot_bits pte_bits[] =3D { .val =3D PTE_CONT, .set =3D "CON", .clear =3D " ", - }, { - .mask =3D PTE_TABLE_BIT, - .val =3D PTE_TABLE_BIT, - .set =3D " ", - .clear =3D "BLK", }, { .mask =3D PTE_UXN, .val =3D PTE_UXN, @@ -143,34 +139,129 @@ static const struct prot_bits pte_bits[] =3D { } }; =20 +static const struct prot_bits pxd_bits[] =3D { + { + .mask =3D PMD_SECT_VALID, + .val =3D PMD_SECT_VALID, + .set =3D " ", + .clear =3D "F", + }, { + .mask =3D PMD_TABLE_BIT, + .val =3D PMD_TABLE_BIT, + .set =3D "TBL", + .clear =3D "BLK", + }, { + .mask =3D PMD_SECT_USER, + .val =3D PMD_SECT_USER, + .set =3D "USR", + .clear =3D " ", + }, { + .mask =3D PMD_SECT_RDONLY, + .val =3D PMD_SECT_RDONLY, + .set =3D "ro", + .clear =3D "RW", + }, { + .mask =3D PMD_SECT_S, + .val =3D PMD_SECT_S, + .set =3D "SHD", + .clear =3D " ", + }, { + .mask =3D PMD_SECT_AF, + .val =3D PMD_SECT_AF, + .set =3D "AF", + .clear =3D " ", + }, { + .mask =3D PMD_SECT_NG, + .val =3D PMD_SECT_NG, + .set =3D "NG", + .clear =3D " ", + }, { + .mask =3D PMD_SECT_CONT, + .val =3D PMD_SECT_CONT, + .set =3D "CON", + .clear =3D " ", + }, { + .mask =3D PMD_SECT_PXN, + .val =3D PMD_SECT_PXN, + .set =3D "NX", + .clear =3D "x ", + }, { + .mask =3D PMD_SECT_UXN, + .val =3D PMD_SECT_UXN, + .set =3D "UXN", + .clear =3D " ", + }, { + .mask =3D PMD_TABLE_PXN, + .val =3D PMD_TABLE_PXN, + .set =3D "NXTbl", + .clear =3D " ", + }, { + .mask =3D PMD_TABLE_UXN, + .val =3D PMD_TABLE_UXN, + .set =3D "UXNTbl", + .clear =3D " ", + }, { + .mask =3D PTE_GP, + .val =3D PTE_GP, + .set =3D "GP", + .clear =3D " ", + }, { + .mask =3D PMD_ATTRINDX_MASK, + .val =3D PMD_ATTRINDX(MT_DEVICE_nGnRnE), + .set =3D "DEVICE/nGnRnE", + }, { + .mask =3D PMD_ATTRINDX_MASK, + .val =3D PMD_ATTRINDX(MT_DEVICE_nGnRE), + .set =3D "DEVICE/nGnRE", + }, { + .mask =3D PMD_ATTRINDX_MASK, + .val =3D PMD_ATTRINDX(MT_NORMAL_NC), + .set =3D "MEM/NORMAL-NC", + }, { + .mask =3D PMD_ATTRINDX_MASK, + .val =3D PMD_ATTRINDX(MT_NORMAL), + .set =3D "MEM/NORMAL", + }, { + .mask =3D PMD_ATTRINDX_MASK, + .val =3D PMD_ATTRINDX(MT_NORMAL_TAGGED), + .set =3D "MEM/NORMAL-TAGGED", + } +}; + struct pg_level { const struct prot_bits *bits; char name[4]; int num; u64 mask; + unsigned long size; }; =20 static struct pg_level pg_level[] __ro_after_init =3D { { /* pgd */ .name =3D "PGD", - .bits =3D pte_bits, - .num =3D ARRAY_SIZE(pte_bits), + .bits =3D pxd_bits, + .num =3D ARRAY_SIZE(pxd_bits), + .size =3D PGDIR_SIZE, }, { /* p4d */ .name =3D "P4D", - .bits =3D pte_bits, - .num =3D ARRAY_SIZE(pte_bits), + .bits =3D pxd_bits, + .num =3D ARRAY_SIZE(pxd_bits), + .size =3D P4D_SIZE, }, { /* pud */ .name =3D "PUD", - .bits =3D pte_bits, - .num =3D ARRAY_SIZE(pte_bits), + .bits =3D pxd_bits, + .num =3D ARRAY_SIZE(pxd_bits), + .size =3D PUD_SIZE, }, { /* pmd */ .name =3D "PMD", - .bits =3D pte_bits, - .num =3D ARRAY_SIZE(pte_bits), + .bits =3D pxd_bits, + .num =3D ARRAY_SIZE(pxd_bits), + .size =3D PMD_SIZE, }, { /* pte */ .name =3D "PTE", .bits =3D pte_bits, .num =3D ARRAY_SIZE(pte_bits), + .size =3D PAGE_SIZE }, }; =20 @@ -251,10 +342,27 @@ static void note_page(struct ptdump_state *pt_st, uns= igned long addr, int level, note_prot_wx(st, addr); } =20 - pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", - st->start_address, addr); + /* + * Non-leaf entries use a fixed size for their range + * specification, whereas leaf entries are grouped by + * attributes and may not have a range larger than the type + * specifier. + */ + if (st->start_address =3D=3D addr) { + if (check_add_overflow(addr, pg_level[st->level].size, + &delta)) + delta =3D ULONG_MAX - addr + 1; + else + delta =3D pg_level[st->level].size; + pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", + addr, addr + delta); + } else { + delta =3D (addr - st->start_address); + pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", + st->start_address, addr); + } =20 - delta =3D (addr - st->start_address) >> 10; + delta >>=3D 10; while (!(delta & 1023) && unit[1]) { delta >>=3D 10; unit++; --=20 2.39.2