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[35.204.165.105]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65bad3f0d09sm585900a12.25.2026.02.13.03.51.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 03:51:15 -0800 (PST) Date: Fri, 13 Feb 2026 12:51:07 +0100 From: =?utf-8?Q?Pierre-Cl=C3=A9ment?= Tosi To: catalin.marinas@arm.com, will@kernel.org, suzuki.poulose@arm.com, maz@kernel.org, corbet@lwn.net Cc: yee.lee@mediatek.com, ascull@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH] arm64: Optionally disable EL0 MTE via command-line Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Although it is currently possible to fully disable MTE on MTE-capable CPUs (with arm64.nomte or id_aa64pfr1.mte=3D0) and to only use MTE in userspace (with kasan=3Doff), there is no way to limit the use of MTE to the kernel because CPU capabilities are traditionally exposed directly to userspace. To address this, introduce a new cmdline argument (inspired by the existing arm64.nomte) to only expose the MTE capability of the CPU to the kernel. Combined with KASAN, this results in only the kernel using the feature, while HWCAP2_MTE and the corresponding MSR ID_AA64PFR1_EL1 field are hidden from userspace. Implement it as a software-only feature override, similar to nokaslr. Signed-off-by: Pierre-Cl=C3=A9ment Tosi --- Documentation/admin-guide/kernel-parameters.txt | 3 +++ arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/kernel/cpufeature.c | 8 ++++++++ arch/arm64/kernel/pi/idreg-override.c | 2 ++ 4 files changed, 14 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 0869294363b3..4d138c1826f0 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -564,6 +564,9 @@ Kernel parameters arm64.nomte [ARM64] Unconditionally disable Memory Tagging Extension support =20 + arm64.nomte_el0 [ARM64] Unconditionally disable Memory Tagging Extension + support for userspace + arm64.nopauth [ARM64] Unconditionally disable Pointer Authentication support =20 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 4de51f8d92cb..0944ff5084a2 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -18,6 +18,7 @@ #define ARM64_SW_FEATURE_OVERRIDE_NOKASLR 0 #define ARM64_SW_FEATURE_OVERRIDE_HVHE 4 #define ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF 8 +#define ARM64_SW_FEATURE_OVERRIDE_NOMTE_EL0 12 =20 #ifndef __ASSEMBLER__ =20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6044d463d3fb..81ea00050e56 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2412,6 +2412,14 @@ static void user_feature_fixup(void) if (regp) regp->user_mask &=3D ~ID_AA64PFR1_EL1_SSBS_MASK; } + + if (arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_NOMTE_EL0)) { + struct arm64_ftr_reg *regp; + + regp =3D get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); + if (regp) + regp->user_mask &=3D ~ID_AA64PFR1_EL1_MTE_MASK; + } } =20 static void elf_hwcap_fixup(void) diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel/pi/i= dreg-override.c index bc57b290e5e7..758141bf9e37 100644 --- a/arch/arm64/kernel/pi/idreg-override.c +++ b/arch/arm64/kernel/pi/idreg-override.c @@ -211,6 +211,7 @@ static const struct ftr_set_desc sw_features __prel64_i= nitconst =3D { FIELD("nokaslr", ARM64_SW_FEATURE_OVERRIDE_NOKASLR, NULL), FIELD("hvhe", ARM64_SW_FEATURE_OVERRIDE_HVHE, hvhe_filter), FIELD("rodataoff", ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF, NULL), + FIELD("nomte_el0", ARM64_SW_FEATURE_OVERRIDE_NOMTE_EL0, NULL), {} }, }; @@ -244,6 +245,7 @@ static const struct { "id_aa64isar2.gpa3=3D0 id_aa64isar2.apa3=3D0" }, { "arm64.nomops", "id_aa64isar2.mops=3D0" }, { "arm64.nomte", "id_aa64pfr1.mte=3D0" }, + { "arm64.nomte_el0", "arm64_sw.nomte_el0=3D1" }, { "nokaslr", "arm64_sw.nokaslr=3D1" }, { "rodata=3Doff", "arm64_sw.rodataoff=3D1" }, { "arm64.nolva", "id_aa64mmfr2.varange=3D0" }, --=20 2.53.0.273.g2a3d683680-goog --=20 Pierre