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Sun, 12 Oct 2025 17:05:42 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 06/20] iommu/arm-smmu: Implement arm_smmu_test_dev Date: Sun, 12 Oct 2025 17:05:03 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F69:EE_|LV9PR12MB9760:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f53487a-5098-4eee-5aa2-08de09ec4a9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?vAFkRjJB5JStJFSzBCtyCX6nhRxwEgh4dQjIE2P22saOjD5LEnXMvkLo19Sm?= =?us-ascii?Q?zXC9N6/dUoKLvuaWuZJAK4NUg+vurrIqVhkBkQpTbI4woKCWuaB6xaaXoOYX?= =?us-ascii?Q?8NVAmKSZNqEVNr8RSkX6DjUaYaD7ZezsHG0y7icAWjtyZj0OdR/s0n5ePU0N?= =?us-ascii?Q?IOJC3ii+vEjdwF/jz7tfPO4pVEm8IRAfhViJSgqwflS2YXlEa6PbtVDtJSmc?= =?us-ascii?Q?k6k1CvU7FQ7VeronpexbMa74Vec1/DUOqmuiiZzflA++ltpvJQR+fE/uzkR6?= =?us-ascii?Q?km/L6u7OMe9BGi44efwQDKqKkfb3joz1jcSd6BnHGQ9M0EXttLWtBv8Ohszm?= =?us-ascii?Q?2gilYrbfByjYUn+86jvaQSg6nQqE67a2U1GANUrJhwESarx7PFuFdC7nuEzN?= =?us-ascii?Q?qO1aUK7aK1JqnpH7eE+XP7LOQBJIoSgPwttiE6ceF/zuojMV2DeqdPRiarwR?= =?us-ascii?Q?ijLjBXP5hueldap6siSj4WZ+QRzLUQK5bRVsp47RXpk3203i57MySuag3R/g?= =?us-ascii?Q?V3WuEBYQ+GsYfQN2VA/MR/AbPg2OXxvY9hKq0CYdZq8KROeKjoFDZJyNoOot?= =?us-ascii?Q?lDBr2dy/fiBAyUmZ+D6ScLgW8/00G47dxGCyhaypuZ3avQTJEPBHYJUzaZxl?= =?us-ascii?Q?jKu0FuRexoAHuH/U2tGZu6EWrjoSJOJ6FVBU0Hkz6iMXlRz5fQkbifeMLG31?= =?us-ascii?Q?PzEOVmA8EYvwztKRmxZHkXc+n59ABerc6UCNktHQxdGs7rNReKhDL5Q9NiNa?= =?us-ascii?Q?/ng2s452C+6KqLxG7YkFk/ZrCYPhN0HXdlL4fLSdQi1JLYVPa1IPt+P6+mvG?= =?us-ascii?Q?tTlbhj1TkF085M9IqnVknOlk15YGP6kDTCHnmg9L40T4a1oVtaV7Tx13pVFr?= =?us-ascii?Q?7T+SghpIR30GLTY2jG/q35LgfMz9yAMXOBhF+hVnrNGGxmhFcUx/d5dZgorS?= =?us-ascii?Q?QsfWH7G4hyj3iVhS9ZqCSn4RkrvHOcM8kirbNS/h9AtmT2Y/7NmhRLhj1Yzd?= =?us-ascii?Q?BllNu4+GtbJKhbUtIEaw7f4yPX3cxwwV9yRXouS1bA0dafpmmQAs68xpYBFT?= =?us-ascii?Q?1YC/9d8NAk0RsrbtEXs8vMY2GWeMStX3yW9hVbdVEJxt7ie/19nv2BeTGB0U?= =?us-ascii?Q?35dXvelRyr/Yc6CeFJNdIRwGJ0Q6RF8vqQ9Ax7q/RW/9M7UUcUkf/Jr6KcCh?= =?us-ascii?Q?g7Omop3i/1ER6DgE9XIJRwsWFq5cBFUrA34w52cXSPBUi3v4hLFzI93ahN2L?= =?us-ascii?Q?R0MHRyglpmq75a/lccTxWDxE0ysZoVMaPRQbFP5yB31Usb37d8u3WvL7VLKq?= =?us-ascii?Q?jKNlfiAemy6ZH8jo292k4/EdNExDnxEXIsB3OAYOIAA1Wb9PE90TTYukm2a1?= =?us-ascii?Q?TtvAhTiHOV87J0b+2x5wnwJSoel6S/FYAdyiLf+9DCBOh15qg9AFZ52QVnSb?= =?us-ascii?Q?hTVXYwF5Nr2oUqIBGUZVxMO+XGBi5F64JNWDn0mAYnsJgR4EUC5lm9XpoQ1F?= =?us-ascii?Q?vaBErmAjdIEVF/cpnG8K/1GzAZnElsGmOxycLkigPFTOmq0G7gcRrxX35dW4?= =?us-ascii?Q?/Nc0w0TAUQzWEktlnKM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:00.0566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f53487a-5098-4eee-5aa2-08de09ec4a9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9760 Content-Type: text/plain; charset="utf-8" Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 116 ++++++++++++++++---------- 1 file changed, 71 insertions(+), 45 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-= smmu/arm-smmu.c index 5e690cf85ec96..5752eecc1d434 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -672,6 +672,37 @@ static int arm_smmu_alloc_context_bank(struct arm_smmu= _domain *smmu_domain, return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_contex= t_banks); } =20 +static enum arm_smmu_context_fmt +arm_smmu_get_context_fmt(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; + enum arm_smmu_context_fmt fmt =3D cfg->fmt; + + /* + * Choosing a suitable context format is even more fiddly. Until we + * grow some way for the caller to express a preference, and/or move + * the decision into the io-pgtable code where it arguably belongs, + * just aim for the closest thing to the rest of the system, and hope + * that the hardware isn't esoteric enough that we can't assume AArch64 + * support to be a superset of AArch32 support... + */ + if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) + fmt =3D ARM_SMMU_CTX_FMT_AARCH32_L; + if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) && + !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) && + (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && + (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1)) + fmt =3D ARM_SMMU_CTX_FMT_AARCH32_S; + if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt =3D=3D ARM_SMMU_CTX_FMT_NONE) && + (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | + ARM_SMMU_FEAT_FMT_AARCH64_16K | + ARM_SMMU_FEAT_FMT_AARCH64_4K))) + fmt =3D ARM_SMMU_CTX_FMT_AARCH64; + + return fmt; +} + static int arm_smmu_init_domain_context(struct arm_smmu_domain *smmu_domai= n, struct arm_smmu_device *smmu, struct device *dev) @@ -712,31 +743,8 @@ static int arm_smmu_init_domain_context(struct arm_smm= u_domain *smmu_domain, if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) smmu_domain->stage =3D ARM_SMMU_DOMAIN_S1; =20 - /* - * Choosing a suitable context format is even more fiddly. Until we - * grow some way for the caller to express a preference, and/or move - * the decision into the io-pgtable code where it arguably belongs, - * just aim for the closest thing to the rest of the system, and hope - * that the hardware isn't esoteric enough that we can't assume AArch64 - * support to be a superset of AArch32 support... - */ - if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) - cfg->fmt =3D ARM_SMMU_CTX_FMT_AARCH32_L; - if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) && - !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) && - (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && - (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1)) - cfg->fmt =3D ARM_SMMU_CTX_FMT_AARCH32_S; - if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt =3D=3D ARM_SMMU_CTX_FMT_NONE) && - (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | - ARM_SMMU_FEAT_FMT_AARCH64_16K | - ARM_SMMU_FEAT_FMT_AARCH64_4K))) - cfg->fmt =3D ARM_SMMU_CTX_FMT_AARCH64; - - if (cfg->fmt =3D=3D ARM_SMMU_CTX_FMT_NONE) { - ret =3D -EINVAL; - goto out_unlock; - } + cfg->fmt =3D arm_smmu_get_context_fmt(smmu_domain); + WARN_ON(cfg->fmt =3D=3D ARM_SMMU_CTX_FMT_NONE); =20 switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: @@ -1165,14 +1173,11 @@ static void arm_smmu_master_install_s2crs(struct ar= m_smmu_master_cfg *cfg, } } =20 -static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device = *dev, - struct iommu_domain *old) +static int arm_smmu_test_dev(struct iommu_domain *domain, struct device *d= ev, + ioasid_t pasid, struct iommu_domain *old) { - struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); - struct arm_smmu_master_cfg *cfg; - struct arm_smmu_device *smmu; - int ret; + struct arm_smmu_master_cfg *cfg =3D dev_iommu_priv_get(dev); + struct arm_smmu_domain *smmu_domain; =20 /* * FIXME: The arch/arm DMA API code tries to attach devices to its own @@ -1181,11 +1186,40 @@ static int arm_smmu_attach_dev(struct iommu_domain = *domain, struct device *dev, * domains, just say no (but more politely than by dereferencing NULL). * This should be at least a WARN_ON once that's sorted. */ - cfg =3D dev_iommu_priv_get(dev); if (!cfg) return -ENODEV; =20 - smmu =3D cfg->smmu; + if (domain =3D=3D arm_smmu_ops.identity_domain || + domain =3D=3D arm_smmu_ops.blocked_domain) + return 0; + + smmu_domain =3D to_smmu_domain(domain); + scoped_guard(mutex, &smmu_domain->init_mutex) { + /* arm_smmu_init_domain_context() will initialize it */ + if (!smmu_domain->smmu) + return 0; + /* + * Sanity check the domain. We don't support domains across + * different SMMUs. + */ + if (smmu_domain->smmu !=3D cfg->smmu) + return -EINVAL; + if (arm_smmu_get_context_fmt(smmu_domain) =3D=3D + ARM_SMMU_CTX_FMT_NONE) + return -EINVAL; + } + + return 0; +} + +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device = *dev, + struct iommu_domain *old) +{ + struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); + struct arm_smmu_master_cfg *cfg =3D dev_iommu_priv_get(dev); + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct arm_smmu_device *smmu =3D cfg->smmu; + int ret; =20 ret =3D arm_smmu_rpm_get(smmu); if (ret < 0) @@ -1196,15 +1230,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev, if (ret < 0) goto rpm_put; =20 - /* - * Sanity check the domain. We don't support domains across - * different SMMUs. - */ - if (smmu_domain->smmu !=3D smmu) { - ret =3D -EINVAL; - goto rpm_put; - } - /* Looks ok, so add the device to the domain */ arm_smmu_master_install_s2crs(cfg, S2CR_TYPE_TRANS, smmu_domain->cfg.cbndx, fwspec); @@ -1221,8 +1246,6 @@ static int arm_smmu_attach_dev_type(struct device *de= v, struct arm_smmu_device *smmu; int ret; =20 - if (!cfg) - return -ENODEV; smmu =3D cfg->smmu; =20 ret =3D arm_smmu_rpm_get(smmu); @@ -1242,6 +1265,7 @@ static int arm_smmu_attach_dev_identity(struct iommu_= domain *domain, } =20 static const struct iommu_domain_ops arm_smmu_identity_ops =3D { + .test_dev =3D arm_smmu_test_dev, .attach_dev =3D arm_smmu_attach_dev_identity, }; =20 @@ -1258,6 +1282,7 @@ static int arm_smmu_attach_dev_blocked(struct iommu_d= omain *domain, } =20 static const struct iommu_domain_ops arm_smmu_blocked_ops =3D { + .test_dev =3D arm_smmu_test_dev, .attach_dev =3D arm_smmu_attach_dev_blocked, }; =20 @@ -1647,6 +1672,7 @@ static const struct iommu_ops arm_smmu_ops =3D { .def_domain_type =3D arm_smmu_def_domain_type, .owner =3D THIS_MODULE, .default_domain_ops =3D &(const struct iommu_domain_ops) { + .test_dev =3D arm_smmu_test_dev, .attach_dev =3D arm_smmu_attach_dev, .map_pages =3D arm_smmu_map_pages, .unmap_pages =3D arm_smmu_unmap_pages, --=20 2.43.0