From nobody Wed Apr 1 22:18:25 2026 Received: from www537.your-server.de (www537.your-server.de [188.40.3.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA4C43CEB89; Wed, 1 Apr 2026 12:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=188.40.3.216 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775046369; cv=none; b=m4fdmTWpGe2dVkjp3SIiG+tB80hsaaa1+4SjiiCVAP/bs1WfgSA7CdKl/5gcfVTiitI5YgwxaXxspbvFI4l/iF5ZQ1Od61/rErG6oFLWoNvAOTJPImeacczU3ciBhMmKNU19iWh0Rw4ubYEO1auQJoK0b5qTnXEoACwOI3lnNMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775046369; c=relaxed/simple; bh=Dyd9F+V79y9hNb/JUAVClmv+qWMBAkFMPXJfQHrsDSU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kpup5osMbU7i38x/a0wWFkp7XHJchc/HS7NhVk3yPNOOQDIhV6lvXha2CPJCk0g6FuG9xdI72AnCcQ4OBfw35zQ/sxQu56T3NTjADmGAkgkE9L2EYDthi0FbEDY7R2BTCQ0ND1nOYysP0nyqqpqvNEW+2xGP7ImygSxzKmYzHFQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=HZ2L4lL7; arc=none smtp.client-ip=188.40.3.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="HZ2L4lL7" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ew.tq-group.com; s=default2602; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID; bh=Ri29mMECTRLPmj/f28VKUr01MxVHN14NYrO0oRv5ApA=; b=HZ2L4lL7AGedirOqb9tjtBdAlV 1qJiVnnR+Yi01Pq4ofNg0n9DUg4j5WAldI9fdZdPGYA/gvzdaDF9VJF24lSWA1zFhRYwzyu9C11PP NwglrqTzTIxGd2/fwobjTI0i/BTxUfqi+nHYtczInCJok2TQd7k4UFcC1KwpAMcSxvRo/vXAa/iSe zW5vR7bYYoWOFx44AijBiBBkCf29z9wYD9+AjmiskBJ4qhG75etHcuW9OHcTGjqEk3Lir0hcMdNIV /ja3zYgNngwI0ORPqr/U7edKYst61l3GpFO+R+4Gsw02LQySL9vRQsgva+BDc0LVWrKtevRhLhQvv AB93wUrA==; Received: from sslproxy07.your-server.de ([78.47.199.104]) by www537.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1w7ue4-000IQz-0t; Wed, 01 Apr 2026 14:26:04 +0200 Received: from localhost ([127.0.0.1]) by sslproxy07.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w7ue3-00089b-2W; Wed, 01 Apr 2026 14:26:03 +0200 From: Nora Schiffer To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Vinod Koul , Neil Armstrong Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Roger Quadros , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, Nora Schiffer Subject: [PATCH v3 3/5] phy: ti: phy-j721e-wiz: add support for J722S SoC family Date: Wed, 1 Apr 2026 14:25:23 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: Clear (ClamAV 1.4.3/27958/Wed Apr 1 08:24:34 2026) The J722S WIZ is mostly identical to the AM64's, but additionally supports SGMII. Signed-off-by: Nora Schiffer --- drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 6e9ecb88dc8b7..99a80740cdc6b 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -331,6 +331,7 @@ enum wiz_type { J721E_WIZ_16G, J721E_WIZ_10G, /* Also for J7200 SR1.0 */ AM64_WIZ_10G, + J722S_WIZ_10G, J7200_WIZ_10G, /* J7200 SR2.0 */ J784S4_WIZ_10G, J721S2_WIZ_10G, @@ -1020,6 +1021,7 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct= device_node *node) =20 switch (wiz->type) { case AM64_WIZ_10G: + case J722S_WIZ_10G: case J7200_WIZ_10G: case J784S4_WIZ_10G: case J721S2_WIZ_10G: @@ -1089,6 +1091,7 @@ static void wiz_clock_init(struct wiz *wiz) =20 switch (wiz->type) { case AM64_WIZ_10G: + case J722S_WIZ_10G: case J7200_WIZ_10G: switch (rate) { case REF_CLK_100MHZ: @@ -1158,6 +1161,7 @@ static int wiz_clock_probe(struct wiz *wiz, struct de= vice_node *node) =20 switch (wiz->type) { case AM64_WIZ_10G: + case J722S_WIZ_10G: case J7200_WIZ_10G: case J784S4_WIZ_10G: case J721S2_WIZ_10G: @@ -1246,6 +1250,14 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int l= ane) if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); break; + + case J722S_WIZ_10G: + if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_PCIE) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); + break; + default: return 0; } @@ -1350,6 +1362,15 @@ static struct wiz_data am64_10g_data =3D { .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, }; =20 +static struct wiz_data j722s_10g_data =3D { + .type =3D J722S_WIZ_10G, + .pll0_refclk_mux_sel =3D &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel =3D &pll1_refclk_mux_sel, + .refclk_dig_sel =3D &refclk_dig_sel_10g, + .clk_mux_sel =3D clk_mux_sel_10g, + .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, +}; + static struct wiz_data j7200_pg2_10g_data =3D { .type =3D J7200_WIZ_10G, .pll0_refclk_mux_sel =3D &sup_pll0_refclk_mux_sel, @@ -1389,6 +1410,9 @@ static const struct of_device_id wiz_id_table[] =3D { { .compatible =3D "ti,am64-wiz-10g", .data =3D &am64_10g_data, }, + { + .compatible =3D "ti,j722s-wiz-10g", .data =3D &j722s_10g_data, + }, { .compatible =3D "ti,j7200-wiz-10g", .data =3D &j7200_pg2_10g_data, }, --=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider https://www.tq-group.com/