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Fri, 30 May 2025 02:36:36 -0700 (PDT) From: Bo Li To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, luto@kernel.org, kees@kernel.org, akpm@linux-foundation.org, david@redhat.com, juri.lelli@redhat.com, vincent.guittot@linaro.org, peterz@infradead.org Cc: dietmar.eggemann@arm.com, hpa@zytor.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, viro@zeniv.linux.org.uk, brauner@kernel.org, jack@suse.cz, lorenzo.stoakes@oracle.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, rostedt@goodmis.org, bsegall@google.com, mgorman@suse.de, vschneid@redhat.com, jannh@google.com, pfalcato@suse.de, riel@surriel.com, harry.yoo@oracle.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, duanxiongchun@bytedance.com, yinhongbo@bytedance.com, dengliang.1214@bytedance.com, xieyongji@bytedance.com, chaiwen.cc@bytedance.com, songmuchun@bytedance.com, yuanzhu@bytedance.com, chengguozhu@bytedance.com, sunjiadong.lff@bytedance.com, Bo Li Subject: [RFC v2 32/35] RPAL: fix unknown nmi on AMD CPU Date: Fri, 30 May 2025 17:28:00 +0800 Message-Id: X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In Lazy switch, the function event_sched_out() will be called. This function deletes the perf event of the task being scheduled out, causing the active_mask in cpu_hw_events to be cleared. In AMD's NMI handler, if the bit corresponding to active_mask is not set, the CPU will not handle the NMI event, ultimately triggering an unknown NMI error. Additionally, event_sched_out() may call amd_pmu_wait_on_overflow(), leading to a busy wait of up to 50us during lazy switch. This patch adds two per_cpu variables. rpal_nmi_handle is set when an NMI occurs. When encountering an unknown NMI, this NMI is skipped. rpal_nmi is set before lazy switch and cleared after lazy switch, preventing the busy wait caused by amd_pmu_wait_on_overflow(). Signed-off-by: Bo Li --- arch/x86/events/amd/core.c | 14 ++++++++++++++ arch/x86/kernel/nmi.c | 20 ++++++++++++++++++++ arch/x86/rpal/core.c | 17 ++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index b20661b8621d..633a9ac4e77c 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -719,6 +719,10 @@ static void amd_pmu_wait_on_overflow(int idx) } } =20 +#ifdef CONFIG_RPAL +DEFINE_PER_CPU(bool, rpal_nmi); +#endif + static void amd_pmu_check_overflow(void) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); @@ -732,6 +736,11 @@ static void amd_pmu_check_overflow(void) if (in_nmi()) return; =20 +#ifdef CONFIG_RPAL + if (this_cpu_read(rpal_nmi)) + return; +#endif + /* * Check each counter for overflow and wait for it to be reset by the * NMI if it has overflowed. This relies on the fact that all active @@ -807,6 +816,11 @@ static void amd_pmu_disable_event(struct perf_event *e= vent) if (in_nmi()) return; =20 +#ifdef CONFIG_RPAL + if (this_cpu_read(rpal_nmi)) + return; +#endif + amd_pmu_wait_on_overflow(event->hw.idx); } =20 diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index be93ec7255bf..dd72b6d1c7f9 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -351,12 +351,23 @@ NOKPROBE_SYMBOL(unknown_nmi_error); =20 static DEFINE_PER_CPU(bool, swallow_nmi); static DEFINE_PER_CPU(unsigned long, last_nmi_rip); +#ifdef CONFIG_RPAL +DEFINE_PER_CPU(bool, rpal_nmi_handle); +#endif =20 static noinstr void default_do_nmi(struct pt_regs *regs) { unsigned char reason =3D 0; int handled; bool b2b =3D false; +#ifdef CONFIG_RPAL + bool rpal_handle =3D false; + + if (__this_cpu_read(rpal_nmi_handle)) { + __this_cpu_write(rpal_nmi_handle, false); + rpal_handle =3D true; + } +#endif =20 /* * Back-to-back NMIs are detected by comparing the RIP of the @@ -471,6 +482,15 @@ static noinstr void default_do_nmi(struct pt_regs *reg= s) */ if (b2b && __this_cpu_read(swallow_nmi)) __this_cpu_add(nmi_stats.swallow, 1); +#ifdef CONFIG_RPAL + /* + * Lazy switch may clear the bit in active_mask, causing + * nmi event not handled. This will lead to unknown nmi, + * try to avoid this. + */ + else if (rpal_handle) + goto out; +#endif else unknown_nmi_error(reason, regs); =20 diff --git a/arch/x86/rpal/core.c b/arch/x86/rpal/core.c index 6a22b9faa100..92281b557a6c 100644 --- a/arch/x86/rpal/core.c +++ b/arch/x86/rpal/core.c @@ -376,11 +376,26 @@ rpal_exception_context_switch(struct pt_regs *regs) return next; } =20 +DECLARE_PER_CPU(bool, rpal_nmi_handle); +DECLARE_PER_CPU(bool, rpal_nmi); __visible struct task_struct *rpal_nmi_context_switch(struct pt_regs *regs) { struct task_struct *next; =20 - next =3D rpal_kernel_context_switch(regs); + if (rpal_test_current_thread_flag(RPAL_LAZY_SWITCHED_BIT)) + rpal_update_fsbase(regs); + + next =3D rpal_misidentify(); + if (unlikely(next !=3D NULL)) { + next =3D rpal_fix_critical_section(next, regs); + if (next) { + __this_cpu_write(rpal_nmi_handle, true); + /* avoid wait in amd_pmu_check_overflow */ + __this_cpu_write(rpal_nmi, true); + next =3D rpal_do_kernel_context_switch(next, regs); + __this_cpu_write(rpal_nmi, false); + } + } =20 return next; } --=20 2.20.1