From nobody Sun Feb 8 12:20:04 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 147E62139A8 for ; Mon, 2 Sep 2024 17:52:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725299540; cv=none; b=tGKNsAJJlRx4Pd8b928uMBJjUE3fe1z3BFvczoE9sPpERPGmqWH16YooiCSLgM6WXJ3Kf3ZCxblURiv8M1F7HdzV6D6YuHhNjIbam99EHJT2pSdRfwq/wK+e0DRstKN4g2fhf0/VFRzbgQsT8c+6kou/6oAR/kr9UL7s3nEHS3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725299540; c=relaxed/simple; bh=U6P/WM3enBmBShcQtqn6MpRIbH6tfJVCZb5J+YHAeHw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rmOT3f3HB0BZ3x+QadQEkcXEtdonsbwpJeN0YroMbddBQbZ4dPYsFnEJtbV8i2roC7R4LqxsMfH/N6dVk3htz+gn3XT5bzVA8oSBvmXYZhBJPylZFQnaVrT9mjKptqDhcVEY02VWU99Xd6ZvV7Cwn+8zSWpyNc/weq+zZf4MmLo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D7581424; Mon, 2 Sep 2024 10:52:45 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2FC0C3F73B; Mon, 2 Sep 2024 10:52:18 -0700 (PDT) From: Robin Murphy To: will@kernel.org Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ilkka@os.amperecomputing.com Subject: [PATCH v2 6/8] perf/arm-cmn: Refactor DTC PMU register access Date: Mon, 2 Sep 2024 18:52:02 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Annoyingly, we're soon going to have to cope with PMU registers moving about. This will mostly be straightforward, except for the hard-coding of CMN_PMU_OFFSET for the DTC PMU registers. As a first step, refactor those accessors to allow for encapsulating a variable offset without making a big mess all over. As a bonus, we can repack the arm_cmn_dtc structure to accommodate the new pointer without growing any larger, since irq_friend only encodes a range of +/-3. Acked-by: Mark Rutland Reviewed-by: Ilkka Koskinen Signed-off-by: Robin Murphy --- v2: Mention deliberate struct repack --- drivers/perf/arm-cmn.c | 64 ++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 2205c183ec1b..ac7dd4c352e8 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -123,24 +123,24 @@ =20 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) -#define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n)) -#define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40) +#define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n)) +#define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40) =20 -#define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n)) -#define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90) +#define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG= (n)) +#define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90) =20 -#define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100) +#define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0x100) #define CMN_DT_PMCR_PMU_EN BIT(0) #define CMN_DT_PMCR_CNTR_RST BIT(5) #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) =20 -#define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118) -#define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120) +#define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0x118) +#define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0x120) =20 -#define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128) +#define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0x128) #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) =20 -#define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130) +#define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0x130) #define CMN_DT_PMSRR_SS_REQ BIT(0) =20 #define CMN_DT_NUM_COUNTERS 8 @@ -307,8 +307,9 @@ struct arm_cmn_dtm { =20 struct arm_cmn_dtc { void __iomem *base; + void __iomem *pmu_base; int irq; - int irq_friend; + s8 irq_friend; bool cc_active; =20 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; @@ -412,10 +413,15 @@ static enum cmn_model arm_cmn_model(const struct arm_= cmn *cmn) }; } =20 +static int arm_cmn_pmu_offset(const struct arm_cmn *cmn, const struct arm_= cmn_node *dn) +{ + return CMN_PMU_OFFSET; +} + static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, const struct arm_cmn_node *xp, int port) { - int offset =3D CMN_MXP__CONNECT_INFO(port); + int offset =3D CMN_MXP__CONNECT_INFO(port) - arm_cmn_pmu_offset(cmn, xp); =20 if (port >=3D 2) { if (cmn->part =3D=3D PART_CMN600 || cmn->part =3D=3D PART_CMN650) @@ -428,7 +434,7 @@ static u32 arm_cmn_device_connect_info(const struct arm= _cmn *cmn, offset +=3D CI700_CONNECT_INFO_P2_5_OFFSET; } =20 - return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset); + return readl_relaxed(xp->pmu_base + offset); } =20 static struct dentry *arm_cmn_debugfs; @@ -1398,7 +1404,7 @@ static u32 arm_cmn_wp_config(struct perf_event *event= , int wp_idx) static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) { if (!cmn->state) - writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR); + writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0])); cmn->state |=3D state; } =20 @@ -1407,7 +1413,7 @@ static void arm_cmn_clear_state(struct arm_cmn *cmn, = u32 state) cmn->state &=3D ~state; if (!cmn->state) writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, - cmn->dtc[0].base + CMN_DT_PMCR); + CMN_DT_PMCR(&cmn->dtc[0])); } =20 static void arm_cmn_pmu_enable(struct pmu *pmu) @@ -1442,18 +1448,19 @@ static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, st= ruct arm_cmn_hw_event *hw, =20 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) { - u64 val =3D readq_relaxed(dtc->base + CMN_DT_PMCCNTR); + void __iomem *pmccntr =3D CMN_DT_PMCCNTR(dtc); + u64 val =3D readq_relaxed(pmccntr); =20 - writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); + writeq_relaxed(CMN_CC_INIT, pmccntr); return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); } =20 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) { - u32 val, pmevcnt =3D CMN_DT_PMEVCNT(idx); + void __iomem *pmevcnt =3D CMN_DT_PMEVCNT(dtc, idx); + u32 val =3D readl_relaxed(pmevcnt); =20 - val =3D readl_relaxed(dtc->base + pmevcnt); - writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt); + writel_relaxed(CMN_COUNTER_INIT, pmevcnt); return val - CMN_COUNTER_INIT; } =20 @@ -1464,7 +1471,7 @@ static void arm_cmn_init_counter(struct perf_event *e= vent) u64 count; =20 for_each_hw_dtc_idx(hw, i, idx) { - writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + CMN_DT_PMEVCNT(idx)); + writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx)); cmn->dtc[i].counters[idx] =3D event; } =20 @@ -1551,7 +1558,7 @@ static void arm_cmn_event_start(struct perf_event *ev= ent, int flags) =20 writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE, dtc->base + CMN_DT_DTC_CTL); - writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); + writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc)); dtc->cc_active =3D true; } else if (type =3D=3D CMN_TYPE_WP) { u64 val =3D CMN_EVENT_WP_VAL(event); @@ -2028,7 +2035,7 @@ static irqreturn_t arm_cmn_handle_irq(int irq, void *= dev_id) irqreturn_t ret =3D IRQ_NONE; =20 for (;;) { - u32 status =3D readl_relaxed(dtc->base + CMN_DT_PMOVSR); + u32 status =3D readl_relaxed(CMN_DT_PMOVSR(dtc)); u64 delta; int i; =20 @@ -2050,7 +2057,7 @@ static irqreturn_t arm_cmn_handle_irq(int irq, void *= dev_id) } } =20 - writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR); + writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc)); =20 if (!dtc->irq_friend) return ret; @@ -2104,15 +2111,16 @@ static int arm_cmn_init_dtc(struct arm_cmn *cmn, st= ruct arm_cmn_node *dn, int id { struct arm_cmn_dtc *dtc =3D cmn->dtc + idx; =20 - dtc->base =3D dn->pmu_base - CMN_PMU_OFFSET; + dtc->pmu_base =3D dn->pmu_base; + dtc->base =3D dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn); dtc->irq =3D platform_get_irq(to_platform_device(cmn->dev), idx); if (dtc->irq < 0) return dtc->irq; =20 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); - writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base += CMN_DT_PMCR); - writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR); - writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR); + writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR= (dtc)); + writeq_relaxed(0, CMN_DT_PMCCNTR(dtc)); + writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc)); =20 return 0; } @@ -2200,7 +2208,7 @@ static void arm_cmn_init_node_info(struct arm_cmn *cm= n, u32 offset, struct arm_c node->id =3D FIELD_GET(CMN_NI_NODE_ID, reg); node->logid =3D FIELD_GET(CMN_NI_LOGICAL_ID, reg); =20 - node->pmu_base =3D cmn->base + offset + CMN_PMU_OFFSET; + node->pmu_base =3D cmn->base + offset + arm_cmn_pmu_offset(cmn, node); =20 if (node->type =3D=3D CMN_TYPE_CFG) level =3D 0; --=20 2.39.2.101.g768bb238c484.dirty