From nobody Sun Apr 5 04:12:26 2026 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD8163D8133 for ; Tue, 10 Mar 2026 17:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773165283; cv=none; b=Nerp66F7+V3FYt7ooAWeLJvfphAK7MxInPIcLWK6GYkvmaZhg9RsBBKs0Gj97mO7dsY5242YM4O+GblB0ldSkNICAG/lX1bKse1wzq5l5vS7DNHkC3GeBAejZEehREO8KJVr9W5vypYuw61mBjc3y5d+3Ao27HtIqSpj2FuzbRs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773165283; c=relaxed/simple; bh=3dk+frueDuHQjriFgAHAMkt4rUMWp604vJfW3rYS4JA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jdTTEpw6MaYxwkd956D8QCwJmPVHghZ12yilsbrDbQ3eGuzOM3LwTV0sNAlwXa0nDX9crcufOb9WPjb8jK8UmNF6gcPr/2HePIdtXot/CvzMg6NM0NFqyja2PW4odC/RCggdmuwRP/sAUV1f3GlzzQDtjH/aHWAxk6dvFRz7MY0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=aUgMhbIx; arc=none smtp.client-ip=109.224.244.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="aUgMhbIx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773165279; x=1773424479; bh=unipzal6Mh5Coy7VvqackQjj3jPPOlgMpAcUBvdM8Gg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=aUgMhbIxKT3ySXWftqfDg/1yncRcL1gkUJ8z8o5q4rWzucKb6TdpI0SQDhDSc6x/3 Xx6RNciGKljqssT8L4hZ58Wy6Q/SoRvVKqZd8y0YRjKwzuhA0LWB+PgehDlbG+WHMc gtlXQPow0iwPkCKDKVWzgFYimd+2HpDf0u8IMFiOSYdE7E6fquWKq23d/wjLzmoBGT LryWVJj7xUDHeNaJfgCoxJ8MvK/xdzLVhlMfmKOgXmSrEZuk4YOEB6adTM5wmNAsNX 5w3D7ZWmxn+Q99EJUz+ulUG2uIFnf74Zv8EHnKBWDhn2PpkMCWXmie/wHoyFJ8GtfF 0ELFcaBzuRCbg== Date: Tue, 10 Mar 2026 17:54:37 +0000 To: akpm@linux-foundation.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , Alexander Potapenko , linux-kernel@vger.kernel.org Subject: [PATCH v11 11/15] x86/mm: Initialize LAM_SUP Message-ID: In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 4bb4271a3fcf87066663522d0d22fd74051cfcfd Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman To make use of KASAN's tag based mode on x86, Linear Address Masking (LAM) needs to be enabled. To do a bit in CR4 has to be set. When launching secondary CPUs the LAM CR4 bit needs to be added to a mask in head_64.S. Bits that are not part of that mask are cleared when secondary CPUs are getting enabled by the primary one. Signed-off-by: Maciej Wieczor-Retman Acked-by: Alexander Potapenko --- Changelog v11: - Redo the patch message according to Dave's suggestions. Changelog v9: - Rename patch title so it fits the tip standards. Changelog v7: - Add Alexander's acked-by tag. Changelog v6: - boot_cpu_has() -> cpu_feature_enabled() arch/x86/kernel/head_64.S | 3 +++ arch/x86/mm/init.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index cbf7647a25d8..253667acd8a5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -209,6 +209,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) * there will be no global TLB entries after the execution." */ movl $(X86_CR4_PAE | X86_CR4_LA57), %edx +#ifdef CONFIG_ADDRESS_MASKING + orl $X86_CR4_LAM_SUP, %edx +#endif #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index fb67217fddcd..11804ccf2fbb 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -763,6 +763,9 @@ void __init init_mem_mapping(void) probe_page_size_mask(); setup_pcid(); =20 + if (cpu_feature_enabled(X86_FEATURE_LAM) && IS_ENABLED(CONFIG_KASAN_SW_TA= GS)) + cr4_set_bits_and_update_boot(X86_CR4_LAM_SUP); + #ifdef CONFIG_X86_64 end =3D max_pfn << PAGE_SHIFT; #else --=20 2.53.0