From nobody Sun Apr 12 12:02:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B90B1DE4EF; Wed, 4 Mar 2026 17:11:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644279; cv=none; b=dTLQGCCnhU+aKCP7uOGc3egdlmDN33pbQcBSV/34L5OhkOVFaoMbTywtOSU7JnAHGBmIJXk5/5w6rqeHHZQ2zOGqpRvOFVaZb5jkFxwggFZHYm3sPvMJFWkGcnzHtB1aMPPU1hw6PmUDRKMwyz4S6WajeLG63/78pBO5L+jk53w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644279; c=relaxed/simple; bh=3XUFvG1f6yCbCvmXobd5paJM8vfILRAPPcyfQMtZrcg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s/p4DY9NsyxM0I+MGK2FBcO/bxYAdVzaevtBvf7a/Vtg/HLfzvoCLK8QetMRYX6Z1Qs25XyR0yD2V3nfbNzgpkAy6PBC2CwtqlrQjTtfPMErcDxku2x23V65qGd8b26LRud82qn67DSdeP3G1fILZliN1zIK5nfWSeu6s4heqUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90D7DC19425; Wed, 4 Mar 2026 17:11:14 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/7] arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:10:58 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. While at it, replace the magic number for IRQ_TYPE_LEVEL_HIGH by its symbolic definition. Signed-off-by: Geert Uytterhoeven Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s6.dtsi index 8ef6319390331fcf..ab3acef2b147e62c 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -53,10 +53,10 @@ pwrc: power-controller { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 psci { @@ -84,7 +84,7 @@ gic: interrupt-controller@ff200000 { interrupt-controller; reg =3D <0x0 0xff200000 0 0x10000>, <0x0 0xff240000 0 0x80000>; - interrupts =3D ; + interrupts =3D ; }; =20 apb: bus@fe000000 { --=20 2.43.0