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Thu, 18 Dec 2025 12:27:16 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v1 3/9] iommu/arm-smmu-v3: Store ASIDs and VMID in arm_smmu_master Date: Thu, 18 Dec 2025 12:26:49 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C380:EE_|BL3PR12MB6402:EE_ X-MS-Office365-Filtering-Correlation-Id: 02bd8fce-b077-4a3d-6aa1-08de3e73e00b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/0eQeG0FubfjoM/V6Z6rHpqJJUbkA+Zl9TWHZSPwJfouxltWvQPq4DLWiYaT?= =?us-ascii?Q?KHzj/DttpMW/jJ3R2hcObopS+Eu39i23RZP4HjD1ay9MjOokrYn9r8aOMa4H?= =?us-ascii?Q?Oi7jI5Nfsi7JUYnuY82kXG4KGOZhEWDRbUX14ZxM13/2fmdjIW9E+A4rYpvZ?= =?us-ascii?Q?gcdP/2SE9q4IvO7jHQMZtNAtQZGh+ZrROinLpPCbjhJh3D1ybRicoI3w03vL?= =?us-ascii?Q?A6ri4E+Pg0X8FigvWQmnjYMX9gPUADlgyaAUKlJvV6Ym0Tox4O2YSQkgeiSm?= =?us-ascii?Q?/7wGEf8qq+7r8HTn/eMu6ByT+63jwJusIwQf/p7/zvFIHvBpP6ofDdN54LBs?= =?us-ascii?Q?XpJkW7YwXJowqysOzcv3PSA1MCY3gOzfm5eGX8VWnSYeNi5OtLvzvWGnfGnn?= =?us-ascii?Q?Uwv6qrMUqYx97gi2TfdurpFXUIrsX5WX6rKaSW2gnQgGT5myZbtbl7jieqoq?= =?us-ascii?Q?K4+c8ZxrQ97oem/Ro645KTMGeR0YG0ERBav72ZEyZ1YZnuVYVsetXvMg5WXw?= =?us-ascii?Q?YuvIK7oibgpOZF3ZlGuRBRYO+FJUiePkMiVdGPFp6XtFdAXFzj5UVCdEDmu3?= =?us-ascii?Q?r+1NumkefdYrLncJDnxFOQ9V0KFVrLj/QZOopAvtipBV/kp8KXafCZ0OeEf2?= =?us-ascii?Q?UFxJK51DRlwk8yx2VQKE7UMbR/qUocIS5trNmbPwuI0E84jtMtu1VZoh2Qry?= =?us-ascii?Q?Y86fkQotJqzGwnvJZhbfoaqFbJXAu5HM7+1H+O4t4mSKKon8qXrsnEqlZQzC?= =?us-ascii?Q?xLvyNvqC9pxRbb3M60wcrcl5Dyds1j+fUcJFI+w/PlAxE/7HgE7X4FTAcYKl?= =?us-ascii?Q?lLdX/UEFAnuzaxwbUwjdp3NT00uCeC0kX4hnlGiF3gd1/tO71QECttCMFfz3?= =?us-ascii?Q?JWfK/Exg7sWVRULZXTLj2yZGXF2jhv5DrbJKiAH9FOcCSuv2TYZIxCHnwcYv?= =?us-ascii?Q?ztbbvNUuG27JfJNMbaeF6eqgLs7WsAnm5z17AejC6a/n+68U/ZY5nHx52GYj?= =?us-ascii?Q?KCV3ulJAWM4LQNQPXLs8UXCiXydqJk4nBkPSwFyytJ0wZ8Itcz4EVAM4YQQI?= =?us-ascii?Q?+8wypde8ADoM+xfP+vfgZRC6/fNP+0I2zytOn7WajAUicBIWxMP9GPZe2IFM?= =?us-ascii?Q?fC6GPvwWCsLrUUAlVVVourOSY46ORwCYQG77dFzOmKu9iSrjX9+2TEM0Qxz9?= =?us-ascii?Q?42I0eiGWQGz39GlK4uWX1swroAPfJz1NPVXXybXMZHwsVXV8LB5T5zGbUiBQ?= =?us-ascii?Q?QsuSBQHCuUKc9Yqy+uqieNl4bY6eXMfxfJfycRfUCIqGKpkS1jh/BGCQleD1?= =?us-ascii?Q?ZuVkw1zMFm+AgTmaZFC9kFk2HIfOOw/SLqMIn5cMBh4DxikUVz6bS3RC0aQp?= =?us-ascii?Q?bRWPF5DrMgJCw220twhLjMNdQD8TB0t71FqyaRT+FhuZTTko20/ja2Ng2gWr?= =?us-ascii?Q?2akszlJ2Yy1Myw8qULUEIsgpGzNmVYtOIdl0TcnqmwG8z3IcGVVc4ZJd6ed9?= =?us-ascii?Q?15z9B4y+2zoa1ysKjEvX+vU49+bwbnEr+t4f9vQmJfX13nqFssWacKqaR+eS?= =?us-ascii?Q?81JIk9bExy2Sti2Exmw=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:33.2927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02bd8fce-b077-4a3d-6aa1-08de3e73e00b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C380.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 Content-Type: text/plain; charset="utf-8" Currently, ASID is allocated per smmu_domain, stored in the domain, and freed with the domain. Practically, ASID is only used in a CD as an iotlb tag. Therefore, ASID doesn't really follow the life cycle of a domain but domain attachment. On the other hand, the CD carrying ASID is installed to a device's STE. This applies to the VMID as well, which is installed in an STE directly. Since a device can only have one ASID per SSID and one VMID per SID, add an ASID array and VMID in the arm_smmu_master structure, to decouple the ASID/VMID from the domain structure. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 +++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 13 ++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++++++++++ 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index b275673c03ce..e21e95936b05 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -953,6 +953,8 @@ struct arm_smmu_master { bool stall_enabled; unsigned int ssid_bits; unsigned int iopf_refcount; + /* Store allocated ASID[1 << ssid_bits] and VMID */ + u16 *asid, vmid; }; =20 /* SMMU private data for an IOMMU domain */ @@ -1117,11 +1119,13 @@ static inline bool arm_smmu_master_canwbs(struct ar= m_smmu_master *master) * @new_invs: for new domain, this is the new invs array to update domain-= >invs; * for old domain, this is the master->build_invs to pass in as= the * to_unref argument to an arm_smmu_invs_unref() call + * @iotlb_tag: copy of the first entry in the build_invs for the domain */ struct arm_smmu_inv_state { struct arm_smmu_invs __rcu **invs_ptr; struct arm_smmu_invs *old_invs; struct arm_smmu_invs *new_invs; + struct arm_smmu_inv iotlb_tag; }; =20 struct arm_smmu_attach_state { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index e4bdb4cfdacd..ead0d84cc9a0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -449,7 +449,8 @@ static void arm_smmu_v3_test_cd_expect_hitless_transiti= on( num_syncs_expected, true); } =20 -static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd *cd, unsigned int = asid) +static void arm_smmu_test_make_s1_cd(struct kunit *test, struct arm_smmu_c= d *cd, + unsigned int asid) { struct arm_smmu_master master =3D { .smmu =3D &smmu, @@ -471,6 +472,10 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_c= d *cd, unsigned int asid) io_pgtable.cfg.arm_lpae_s1_cfg.tcr.tsz =3D 4; io_pgtable.cfg.arm_lpae_s1_cfg.mair =3D 0xabcdef012345678ULL; =20 + master.asid =3D kunit_kzalloc(test, sizeof(*master.asid), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, master.asid); + + master.asid[IOMMU_NO_PASID] =3D asid; arm_smmu_make_s1_cd(cd, &master, &smmu_domain, IOMMU_NO_PASID); } =20 @@ -479,7 +484,7 @@ static void arm_smmu_v3_write_cd_test_s1_clear(struct k= unit *test) struct arm_smmu_cd cd =3D {}; struct arm_smmu_cd cd_2; =20 - arm_smmu_test_make_s1_cd(&cd_2, 1997); + arm_smmu_test_make_s1_cd(test, &cd_2, 1997); arm_smmu_v3_test_cd_expect_non_hitless_transition( test, &cd, &cd_2, NUM_EXPECTED_SYNCS(2)); arm_smmu_v3_test_cd_expect_non_hitless_transition( @@ -491,8 +496,8 @@ static void arm_smmu_v3_write_cd_test_s1_change_asid(st= ruct kunit *test) struct arm_smmu_cd cd =3D {}; struct arm_smmu_cd cd_2; =20 - arm_smmu_test_make_s1_cd(&cd, 778); - arm_smmu_test_make_s1_cd(&cd_2, 1997); + arm_smmu_test_make_s1_cd(test, &cd, 778); + arm_smmu_test_make_s1_cd(test, &cd_2, 1997); arm_smmu_v3_test_cd_expect_hitless_transition(test, &cd, &cd_2, NUM_EXPECTED_SYNCS(1)); arm_smmu_v3_test_cd_expect_hitless_transition(test, &cd_2, &cd, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8a2b7064d29b..1bf7b7233109 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3391,6 +3391,7 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, arm_smmu_invs_merge(invst->old_invs, build_invs); if (IS_ERR(invst->new_invs)) return PTR_ERR(invst->new_invs); + invst->iotlb_tag =3D build_invs->inv[0]; } =20 if (old_smmu_domain) { @@ -3440,6 +3441,11 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_att= ach_state *state) */ smp_mb(); kfree_rcu(invst->old_invs, rcu); + + if (invst->iotlb_tag.type =3D=3D INV_TYPE_S1_ASID) + state->master->asid[state->ssid] =3D invst->iotlb_tag.id; + else + state->master->vmid =3D invst->iotlb_tag.id; } =20 /* @@ -3471,8 +3477,11 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_= smmu_inv *inv) static void arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) { + struct arm_smmu_inv *new_iotlb_tag =3D &state->new_domain_invst.iotlb_tag; + struct arm_smmu_inv *old_iotlb_tag =3D &state->old_domain_invst.iotlb_tag; struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; struct arm_smmu_invs *old_invs =3D invst->old_invs; + struct arm_smmu_master *master =3D state->master; struct arm_smmu_invs *new_invs; =20 lockdep_assert_held(&arm_smmu_asid_lock); @@ -3482,6 +3491,7 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_atta= ch_state *state) =20 arm_smmu_invs_unref(old_invs, invst->new_invs, arm_smmu_inv_flush_iotlb_tag); + *old_iotlb_tag =3D invst->new_invs->inv[0]; =20 new_invs =3D arm_smmu_invs_purge(old_invs); if (!new_invs) @@ -3506,6 +3516,14 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_att= ach_state *state) */ smp_mb(); kfree_rcu(old_invs, rcu); + + /* Make sure we don't clear the stored new iotlb tag */ + if (!new_iotlb_tag->id) { + if (old_iotlb_tag->type =3D=3D INV_TYPE_S1_ASID) + cmpxchg(&master->asid[state->ssid], old_iotlb_tag->id, 0); + else + cmpxchg(&master->vmid, old_iotlb_tag->id, 0); + } } =20 /* @@ -4286,6 +4304,13 @@ static struct iommu_device *arm_smmu_probe_device(st= ruct device *dev) master->ssid_bits =3D min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); =20 + master->asid =3D kcalloc(1 << master->ssid_bits, sizeof(*master->asid), + GFP_KERNEL); + if (!master->asid) { + ret =3D -ENOMEM; + goto err_disable_pasid; + } + if ((smmu->features & ARM_SMMU_FEAT_STALLS && device_property_read_bool(dev, "dma-can-stall")) || smmu->features & ARM_SMMU_FEAT_STALL_FORCE) @@ -4299,6 +4324,9 @@ static struct iommu_device *arm_smmu_probe_device(str= uct device *dev) =20 return &smmu->iommu; =20 +err_disable_pasid: + arm_smmu_disable_pasid(master); + arm_smmu_remove_master(master); err_free_master: kfree(master); return ERR_PTR(ret); --=20 2.43.0