From nobody Thu Apr 2 17:21:42 2026 Received: from mail-106118.protonmail.ch (mail-106118.protonmail.ch [79.135.106.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6843130EF84 for ; Fri, 27 Mar 2026 15:10:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774624258; cv=none; b=Zqpdrgp1hxS4fuQuTDJJdKllkjvNJxx1xLBQMUhW8UZTk05sKPaHEgBATUtfvP8J+H2TBLws0SX36pBhx0yDYX7Ojzla98COaa5wt/WC3ecN0Z7WA8FH1KYJnUmGJPEg9mTtu8DYnbg6UT/3+j3xlhQhEroNl+MzpiASYBDHYJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774624258; c=relaxed/simple; bh=mEEXKUlmkVBIzNV5wtuGiKeQL7kp/lCT/CJFn9Wdi4I=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uSk870CTy5zHsruA7atFJXa1BwKq1t6m6+webqS2bBYoZ2jic+K6mqHhk+206+QLOTX50sTu9fcr7EOiKRVsMaL1XTAEr5EbshxLB9qIAYTba1yvyL6zsdHJXKlEZbP0QHDRdJOD/GwFBad7iGOuBV4pow4YJChQRkXR5klZYAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=Gaqlt6aU; arc=none smtp.client-ip=79.135.106.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="Gaqlt6aU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1774624249; x=1774883449; bh=mWI6Ci0OExEN/NmgLmPa48Tm+LQjRqPyhRE3t1Uth/U=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Gaqlt6aUxhMMhlPp/6ty2fLuu96xv1NLDl5fkam4cVnelieUusOZcoUqe71QU7boA iRlt0ezdrJzOBB+hcTZQpYQ1YX20eXCQQjk9/TIFIltaBbp1+YhMdiJu4qOElBQu4z l7e2Nagz97jOq/igvf+rQKMhcB6HDCxPXxtTlCv/0oiFSH8HSiG2RzMO3r/6id1na+ VGCoh0M3kAebxmr7Hmi1dP4APY44OXZOP4zj2aw06d5P0+JJGH3X/HgHS0Lbo4myD+ 3bQV3KyCTfQ1XuQK6dkjpE/ZxVjaSkEVLz3D6O5ONcPNwIk59JRyf2I8ewXch8eQOC yTjIQu08cS+gQ== Date: Fri, 27 Mar 2026 15:10:46 +0000 To: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, xin@zytor.com, chang.seok.bae@intel.com, mingo@redhat.com, elena.reshetova@intel.com, maciej.wieczor-retman@intel.com, babu.moger@amd.com, sohil.mehta@intel.com, pawan.kumar.gupta@linux.intel.com, pmladek@suse.com, nik.borisov@suse.com, ptesarik@suse.com, darwi@linutronix.de, tglx@kernel.org, peterz@infradead.org, jpoimboe@kernel.org, ak@linux.intel.com From: Maciej Wieczor-Retman Cc: linux-kernel@vger.kernel.org, x86@kernel.org, m.wieczorretman@pm.me, Farrah Chen Subject: [PATCH v12 1/4] x86/cpu: Clear feature bits disabled at compile-time Message-ID: In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 1536c57c83be7abb7d9b964ea5054429c2c1cd7d Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman If some config options are disabled during compile time, they still are enumerated in macros that use the x86_capability bitmask - cpu_has() or this_cpu_has(). The features are also visible in /proc/cpuinfo even though they are not enabled - which is contrary to what the documentation states about the file. Examples of such feature flags are lam, fred, sgx, user_shstk and enqcmd. Initialize cpu_caps_cleared[] with an autogenerated disabled bitmask. During CPU init, apply_forced_caps() will clear the corresponding bits in struct cpuinfo_x86 for each CPU. Thus features disabled at compile time won't show up in /proc/cpuinfo. No BUGS are defined to be cleared at compile time, therefore only the NCAPINTS part of cpu_caps_cleared[] is initialized using the macro. The NBUGINTS part is set to zero. Reported-by: Farrah Chen Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D220348 Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Sohil Mehta --- Changelog v10: - Remove examples of feature flags that came from stable kernels. - Redo the patch message a bit with Sohil's suggestions. - Add Sohil's Reviewed-by tag. Changelog v9: - *_MASK_INITIALIZER -> *_MASK_INIT - Remove Cc stable. - Note that the BUGS part of cpu_caps_cleared[] is zeroed. Changelog v6: - Remove patch message portions that are not just describing the diff. arch/x86/kernel/cpu/common.c | 3 ++- arch/x86/tools/cpufeaturemasks.awk | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a8ff4376c286..76339e988304 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -735,7 +735,8 @@ static const char *table_lookup_model(struct cpuinfo_x8= 6 *c) } =20 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long= )); +__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long= )) =3D + DISABLED_MASK_INIT; __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); =20 #ifdef CONFIG_X86_32 diff --git a/arch/x86/tools/cpufeaturemasks.awk b/arch/x86/tools/cpufeature= masks.awk index 173d5bf2d999..9382bd15279a 100755 --- a/arch/x86/tools/cpufeaturemasks.awk +++ b/arch/x86/tools/cpufeaturemasks.awk @@ -82,6 +82,12 @@ END { } printf " 0\t\\\n"; printf "\t) & (1U << ((x) & 31)))\n\n"; + + printf "\n#define %s_MASK_INIT\t\t\t\\", s; + printf "\n\t{\t\t\t\t\t\t\\"; + for (i =3D 0; i < ncapints; i++) + printf "\n\t\t%s_MASK%d,\t\t\t\\", s, i; + printf "\n\t}\n\n"; } =20 printf "#endif /* _ASM_X86_CPUFEATUREMASKS_H */\n"; --=20 2.53.0