From nobody Tue Dec 16 11:32:08 2025 Received: from pegase1.c-s.fr (pegase1.c-s.fr [93.17.236.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0F6C179BC for ; Sun, 26 May 2024 09:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.236.30 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716715402; cv=none; b=l4ydlrfVlixqe9fJKJ3fzI4Vutycux5yaRa67P9YLl9uqBp3qX86iW041JGX36rn5ueLbtPGp8b1x/qLUCddOCpyiWwT9WlS4MEbzeES1joau3IhkOo6sdXQ1r5cvJOCUoVNtYCS0UYDqj+ac0peT+wqh52ilkGdBTQAiCLbPtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716715402; c=relaxed/simple; bh=GvUuKmINqllZ54PyQ+lDpy16CYLzBdm/Cr1rg49spF8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LPwyDzTPv0uP+qE5tdZuhpcEm+fwcbtBHtBtMc8DXKez0xGMWJarn3GHW/93WLXyHD7BQjE5Bb7oNVHry1s6M1okxgZlIt7oceVTlosHEFbyAavNdMgCr0tYE86mjwks9ubqSmdPgoArB93v7YsIzkCWmY806GEYuxFRHOk//iw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.236.30 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub3.si.c-s.fr [192.168.12.233]) by localhost (Postfix) with ESMTP id 4VnCws1CNQz9tM6; Sun, 26 May 2024 11:22:37 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase1.c-s.fr ([192.168.12.234]) by localhost (pegase1.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JruguevNDikF; Sun, 26 May 2024 11:22:37 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase1.c-s.fr (Postfix) with ESMTP id 4VnCwn36pWz9t0b; Sun, 26 May 2024 11:22:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 66AD98B773; Sun, 26 May 2024 11:22:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id kh32NAzcDDi9; Sun, 26 May 2024 11:22:33 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.233.45]) by messagerie.si.c-s.fr (Postfix) with ESMTP id D75428B774; Sun, 26 May 2024 11:22:32 +0200 (CEST) From: Christophe Leroy To: Andrew Morton , Jason Gunthorpe , Peter Xu , Oscar Salvador , Michael Ellerman , Nicholas Piggin Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org Subject: [RFC PATCH v3 10/16] powerpc/e500: Remove enc and ind fields from struct mmu_psize_def Date: Sun, 26 May 2024 11:22:30 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716715344; l=3777; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=GvUuKmINqllZ54PyQ+lDpy16CYLzBdm/Cr1rg49spF8=; b=d9+A30hsr6+WdZlbUsIdtK+TSdEN3bWFPGbJYvW17ggKvjX2Yrn6aM1NgByklQUj8NRk4OZ2r Rwr94EFR2ibCqZY5flmp1fIpsZ0dcIaUsmk0q8YrB04xKD2l1+DnjpL X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" enc field is hidden behind BOOK3E_PAGESZ_XX macros, and when you look closer you realise that this field is nothing else than the value of shift minus ten. So remove enc field and calculate tsize from shift field. Also remove inc field which is unused. Signed-off-by: Christophe Leroy Reviewed-by: Oscar Salvador --- arch/powerpc/include/asm/nohash/mmu-e500.h | 3 --- arch/powerpc/mm/nohash/book3e_pgtable.c | 4 ++-- arch/powerpc/mm/nohash/tlb.c | 9 +-------- arch/powerpc/mm/nohash/tlb_64e.c | 2 +- 4 files changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/include/asm/nohash/mmu-e500.h b/arch/powerpc/incl= ude/asm/nohash/mmu-e500.h index 7dc24b8632d7..b281d9eeaf1e 100644 --- a/arch/powerpc/include/asm/nohash/mmu-e500.h +++ b/arch/powerpc/include/asm/nohash/mmu-e500.h @@ -244,14 +244,11 @@ typedef struct { /* Page size definitions, common between 32 and 64-bit * * shift : is the "PAGE_SHIFT" value for that page size - * penc : is the pte encoding mask * */ struct mmu_psize_def { unsigned int shift; /* number of bits */ - unsigned int enc; /* PTE encoding */ - unsigned int ind; /* Corresponding indirect page size shift */ unsigned int flags; #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ diff --git a/arch/powerpc/mm/nohash/book3e_pgtable.c b/arch/powerpc/mm/noha= sh/book3e_pgtable.c index 1c5e4ecbebeb..ad2a7c26f2a0 100644 --- a/arch/powerpc/mm/nohash/book3e_pgtable.c +++ b/arch/powerpc/mm/nohash/book3e_pgtable.c @@ -29,10 +29,10 @@ int __meminit vmemmap_create_mapping(unsigned long star= t, _PAGE_KERNEL_RW; =20 /* PTEs only contain page size encodings up to 32M */ - BUG_ON(mmu_psize_defs[mmu_vmemmap_psize].enc > 0xf); + BUG_ON(mmu_psize_defs[mmu_vmemmap_psize].shift - 10 > 0xf); =20 /* Encode the size in the PTE */ - flags |=3D mmu_psize_defs[mmu_vmemmap_psize].enc << 8; + flags |=3D (mmu_psize_defs[mmu_vmemmap_psize].shift - 10) << 8; =20 /* For each PTE for that area, map things. Note that we don't * increment phys because all PTEs are of the large size and diff --git a/arch/powerpc/mm/nohash/tlb.c b/arch/powerpc/mm/nohash/tlb.c index f57dc721d063..b653a7be4cb1 100644 --- a/arch/powerpc/mm/nohash/tlb.c +++ b/arch/powerpc/mm/nohash/tlb.c @@ -53,37 +53,30 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] =3D { [MMU_PAGE_4K] =3D { .shift =3D 12, - .enc =3D BOOK3E_PAGESZ_4K, }, [MMU_PAGE_2M] =3D { .shift =3D 21, - .enc =3D BOOK3E_PAGESZ_2M, }, [MMU_PAGE_4M] =3D { .shift =3D 22, - .enc =3D BOOK3E_PAGESZ_4M, }, [MMU_PAGE_16M] =3D { .shift =3D 24, - .enc =3D BOOK3E_PAGESZ_16M, }, [MMU_PAGE_64M] =3D { .shift =3D 26, - .enc =3D BOOK3E_PAGESZ_64M, }, [MMU_PAGE_256M] =3D { .shift =3D 28, - .enc =3D BOOK3E_PAGESZ_256M, }, [MMU_PAGE_1G] =3D { .shift =3D 30, - .enc =3D BOOK3E_PAGESZ_1GB, }, }; =20 static inline int mmu_get_tsize(int psize) { - return mmu_psize_defs[psize].enc; + return mmu_psize_defs[psize].shift - 10; } #else static inline int mmu_get_tsize(int psize) diff --git a/arch/powerpc/mm/nohash/tlb_64e.c b/arch/powerpc/mm/nohash/tlb_= 64e.c index 053128a5636c..7988238496d7 100644 --- a/arch/powerpc/mm/nohash/tlb_64e.c +++ b/arch/powerpc/mm/nohash/tlb_64e.c @@ -53,7 +53,7 @@ int extlb_level_exc; */ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address) { - int tsize =3D mmu_psize_defs[mmu_pte_psize].enc; + int tsize =3D mmu_psize_defs[mmu_pte_psize].shift - 10; =20 if (book3e_htw_mode !=3D PPC_HTW_NONE) { unsigned long start =3D address & PMD_MASK; --=20 2.44.0