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Sun, 12 Oct 2025 17:05:34 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 03/20] iommu/arm-smmu-v3: Implement arm_smmu_domain_test_dev Date: Sun, 12 Oct 2025 17:05:00 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|SJ2PR12MB8881:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ac1a793-973b-40e7-9948-08de09ec4549 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xhsdQx3rW29xTC6K6kz9QpFrrlAk20RfkCnfvlQo5okLGvQyPS3yiUU+6m1J?= =?us-ascii?Q?go8yaUwEWmOjn0Ddoh+9fKpPYCclHk44OC32n9oRMERTm54xqxi9mHOwGeYT?= =?us-ascii?Q?4x/5u81B15IbmdjNKMR9gxa8f7z9MdButm4Z6QJR2iAWiVH6V7QZlJwGpoRQ?= =?us-ascii?Q?WJheR/x5rIVG484dVCM65NCq4v2YHIMVqHwzeK3tcbNHQK6dYFY1RtGPhFfk?= =?us-ascii?Q?NzwbYiQjAo1Kqq1HmR2KXvw+EEEHhdpyfso3oJxONhkOlZCoT0qfMguTEDV5?= =?us-ascii?Q?V3RfzikCVDnjni4j1mNsfBCcBFwBYwCopgu7auFRk55OdfLJXfW7xOH8aW3O?= =?us-ascii?Q?0jzrXtNpkaVw6wMK4Due6DN3lUtxihFlIQvc4Glf8+D+Z3TAcIZ+MaJiWC/K?= =?us-ascii?Q?MwZ/ESgMkgZktBqgM3ElYEGYfxUWuUeX7TURA/X8cXxmJkGcTDhWlRPwHAAK?= =?us-ascii?Q?/2KsugD5BPJDvkJFOdaEX6vAVw9XtjJCzY4V7JI2uaor18ey6HJ30LVipK/M?= =?us-ascii?Q?oyc/KSL6StVaOd/97I6qZAkjSEfcytF6xgrK76aXN6M+vZUESjfe+U27r6+A?= =?us-ascii?Q?Mj3q62CDmddVpzvi/C6/YqnSyspm+i/a9fyCGC44c4ZSSRIP6iJcl8bCwMIi?= =?us-ascii?Q?wYT4vXk7O6Z5orKJLtkF9cGMZr6RSWw8yGwW70mhbJGyxzm8ktCMOjLdl7xQ?= =?us-ascii?Q?V5iN7cyRY4eZlUZ7lopy7F2WELj/WoIebVlLBwS/C47cv/QZCgGq+QU1QOC6?= =?us-ascii?Q?HQ7+cxFqiNi4QqZPbgUYtBC63VRrWNfx4wQ9UT2F4ydLLxSYqlnyPGIeRj4o?= =?us-ascii?Q?SH8mzFNIbt305QjTI4GlNOz8FGQYKlTqp2DcjLU1P1enHCLaZPoik7hGC6NX?= =?us-ascii?Q?K7hd+jF0c82hyvwmS1hyr4dftIPBo6U1DU9C2/W3fuZ1yPKQmzG2v1P93yy8?= =?us-ascii?Q?Xgczy+dQtVXzfFMScgHEr1WSXmoyeH+ySdEgF5hJr9VmAByS0CYln3R59vy2?= =?us-ascii?Q?SkIQ3wy5PVQXiSEhHcFUa00ilr9A1+MtSWR+ybdiiQe0PQJttrCSWIle4MFb?= =?us-ascii?Q?qN7FDhR4VJlbc8j27nK2mQHNTpcC6QYu3EWrEWe+UYIwm77Y3VBjPVVFUbiA?= =?us-ascii?Q?cn7NqH2NivREWKj848d5qFocGBaY1+Xmh8TGREVnWWl8TW5RqpEkjHdRvf3o?= =?us-ascii?Q?SjfaIlAFWp0YnFByoa/F0Q9NU6XEnPBe5UZdy+Axo30Fkjivw9rKT5uT1ah4?= =?us-ascii?Q?3CsKkR92GFxksgfuCTE4iR1mdVxe+1vRBvhDwLipasdkGx68aBmPH4PrJYn5?= =?us-ascii?Q?nBuFvr0yw8t5Qao1O+WKDea45elBMFNQoVNJ43kh9x+j5ybq0PUIGHpY3RkN?= =?us-ascii?Q?gshNtTPON3uykwJK6nq6dRmLanbKEC/kI2HddLgE96ogUm+62gjcznFpffCA?= =?us-ascii?Q?QC5h3Ol026o/0cGp9YBCQIPT+lLJkg7GfwGGDi764TEj5EEP1tNOgHdUc3ZF?= =?us-ascii?Q?A8ABCw3PRINht/eGoDLgIxOdVqhHEVAmAywjj5PFkt8BWd0RKKJULwIYuF6T?= =?us-ascii?Q?hEPiLVPudpAiwixk7Tc=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:05:51.1083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ac1a793-973b-40e7-9948-08de09ec4549 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8881 Content-Type: text/plain; charset="utf-8" Move sanity and compatibility tests from the attach_dev callbacks to this new test_dev callback function. The IOMMU core makes sure an attach_dev() must be invoked after a successful test_dev callback. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 6 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 4 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 113 +++++++++++------- 4 files changed, 74 insertions(+), 51 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ae23aacc38402..acb1dbc592cf0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -963,6 +963,8 @@ void arm_smmu_write_cd_entry(struct arm_smmu_master *ma= ster, int ssid, struct arm_smmu_cd *cdptr, const struct arm_smmu_cd *target); =20 +int arm_smmu_domain_test_dev(struct iommu_domain *domain, struct device *d= ev, + ioasid_t pasid, struct iommu_domain *old_domain); int arm_smmu_set_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 313201a616991..a253f9c8bb290 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -152,11 +152,6 @@ static int arm_smmu_attach_dev_nested(struct iommu_dom= ain *domain, struct arm_smmu_ste ste; int ret; =20 - if (nested_domain->vsmmu->smmu !=3D master->smmu) - return -EINVAL; - if (arm_smmu_ssids_in_use(&master->cd_table)) - return -EBUSY; - mutex_lock(&arm_smmu_asid_lock); /* * The VM has to control the actual ATS state at the PCI device because @@ -187,6 +182,7 @@ static void arm_smmu_domain_nested_free(struct iommu_do= main *domain) } =20 static const struct iommu_domain_ops arm_smmu_nested_ops =3D { + .test_dev =3D arm_smmu_domain_test_dev, .attach_dev =3D arm_smmu_attach_dev_nested, .free =3D arm_smmu_domain_nested_free, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80f..610d9e826c07e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -276,9 +276,6 @@ static int arm_smmu_sva_set_dev_pasid(struct iommu_doma= in *domain, struct arm_smmu_cd target; int ret; =20 - if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) - return -EOPNOTSUPP; - /* Prevent arm_smmu_mm_release from being called while we are attaching */ if (!mmget_not_zero(domain->mm)) return -EINVAL; @@ -319,6 +316,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domai= n *domain) } =20 static const struct iommu_domain_ops arm_smmu_sva_domain_ops =3D { + .test_dev =3D arm_smmu_domain_test_dev, .set_dev_pasid =3D arm_smmu_sva_set_dev_pasid, .free =3D arm_smmu_sva_domain_free }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a33fbd12a0dd9..3448e55bbcdbb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2765,9 +2765,6 @@ static int arm_smmu_enable_iopf(struct arm_smmu_maste= r *master, =20 iommu_group_mutex_assert(master->dev); =20 - if (!IS_ENABLED(CONFIG_ARM_SMMU_V3_SVA)) - return -EOPNOTSUPP; - /* * Drivers for devices supporting PRI or stall require iopf others have * device-specific fault handlers and don't need IOPF, so this is not a @@ -2776,10 +2773,6 @@ static int arm_smmu_enable_iopf(struct arm_smmu_mast= er *master, if (!master->stall_enabled) return 0; =20 - /* We're not keeping track of SIDs in fault events */ - if (master->num_streams !=3D 1) - return -EOPNOTSUPP; - if (master->iopf_refcount) { master->iopf_refcount++; master_domain->using_iopf =3D true; @@ -2937,14 +2930,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_s= tate *state, * one of them. */ spin_lock_irqsave(&smmu_domain->devices_lock, flags); - if (smmu_domain->enforce_cache_coherency && - !arm_smmu_master_canwbs(master)) { - spin_unlock_irqrestore(&smmu_domain->devices_lock, - flags); - ret =3D -EINVAL; - goto err_iopf; - } - if (state->ats_enabled) atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); @@ -2962,8 +2947,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, } return 0; =20 -err_iopf: - arm_smmu_disable_iopf(master, master_domain); err_free_master_domain: kfree(master_domain); err_free_vmaster: @@ -3002,13 +2985,79 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_= state *state) master->ats_enabled =3D state->ats_enabled; } =20 +int arm_smmu_domain_test_dev(struct iommu_domain *domain, struct device *d= ev, + ioasid_t pasid, struct iommu_domain *old_domain) +{ + struct arm_smmu_domain *device_domain =3D to_smmu_domain_devices(domain); + struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + + if (!dev_iommu_fwspec_get(dev)) + return -ENOENT; + + switch (domain->type) { + case IOMMU_DOMAIN_NESTED: { + struct arm_smmu_nested_domain *nested_domain =3D + to_smmu_nested_domain(domain); + + if (WARN_ON(pasid !=3D IOMMU_NO_PASID)) + return -EOPNOTSUPP; + if (nested_domain->vsmmu->smmu !=3D master->smmu) + return -EINVAL; + if (arm_smmu_ssids_in_use(&master->cd_table)) + return -EBUSY; + break; + } + case IOMMU_DOMAIN_SVA: + if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) + return -EOPNOTSUPP; + break; + default: { + struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); + + if (smmu_domain->smmu !=3D master->smmu) + return -EINVAL; + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S2 && + arm_smmu_ssids_in_use(&master->cd_table)) + return -EBUSY; + if (pasid !=3D IOMMU_NO_PASID) { + struct iommu_domain *sid_domain =3D + iommu_get_domain_for_dev(master->dev); + + if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_S1) + return -EINVAL; + if (!master->cd_table.in_ste && + sid_domain->type !=3D IOMMU_DOMAIN_IDENTITY && + sid_domain->type !=3D IOMMU_DOMAIN_BLOCKED) + return -EINVAL; + } + break; + } + } + + if (domain->iopf_handler) { + if (!IS_ENABLED(CONFIG_ARM_SMMU_V3_SVA)) + return -EOPNOTSUPP; + /* We're not keeping track of SIDs in fault events */ + if (master->stall_enabled && master->num_streams !=3D 1) + return -EOPNOTSUPP; + } + + if (device_domain) { + scoped_guard(spinlock_irqsave, &device_domain->devices_lock) { + if (device_domain->enforce_cache_coherency && + !arm_smmu_master_canwbs(master)) + return -EINVAL; + } + } + + return 0; +} + static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device = *dev, struct iommu_domain *old_domain) { int ret =3D 0; struct arm_smmu_ste target; - struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); - struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_attach_state state =3D { .old_domain =3D old_domain, @@ -3017,21 +3066,13 @@ static int arm_smmu_attach_dev(struct iommu_domain = *domain, struct device *dev, struct arm_smmu_master *master; struct arm_smmu_cd *cdptr; =20 - if (!fwspec) - return -ENOENT; - state.master =3D master =3D dev_iommu_priv_get(dev); - smmu =3D master->smmu; - - if (smmu_domain->smmu !=3D smmu) - return -EINVAL; =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cdptr =3D arm_smmu_alloc_cd_ptr(master, IOMMU_NO_PASID); if (!cdptr) return -ENOMEM; - } else if (arm_smmu_ssids_in_use(&master->cd_table)) - return -EBUSY; + } =20 /* * Prevent arm_smmu_share_asid() from trying to change the ASID @@ -3078,15 +3119,8 @@ static int arm_smmu_s1_set_dev_pasid(struct iommu_do= main *domain, { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); - struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_cd target_cd; =20 - if (smmu_domain->smmu !=3D smmu) - return -EINVAL; - - if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_S1) - return -EINVAL; - /* * We can read cd.asid outside the lock because arm_smmu_set_pasid() * will fix it @@ -3136,14 +3170,6 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, =20 /* The core code validates pasid */ =20 - if (smmu_domain->smmu !=3D master->smmu) - return -EINVAL; - - if (!master->cd_table.in_ste && - sid_domain->type !=3D IOMMU_DOMAIN_IDENTITY && - sid_domain->type !=3D IOMMU_DOMAIN_BLOCKED) - return -EINVAL; - cdptr =3D arm_smmu_alloc_cd_ptr(master, pasid); if (!cdptr) return -ENOMEM; @@ -3695,6 +3721,7 @@ static const struct iommu_ops arm_smmu_ops =3D { .user_pasid_table =3D 1, .owner =3D THIS_MODULE, .default_domain_ops =3D &(const struct iommu_domain_ops) { + .test_dev =3D arm_smmu_domain_test_dev, .attach_dev =3D arm_smmu_attach_dev, .enforce_cache_coherency =3D arm_smmu_enforce_cache_coherency, .set_dev_pasid =3D arm_smmu_s1_set_dev_pasid, --=20 2.43.0