From nobody Sat Jun 13 03:33:48 2026 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C4542DCF61 for ; Mon, 11 May 2026 05:30:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778477414; cv=none; b=VQQJ7XFDJNumrjQAJKwG/ia864KtXSpowpkU0U1v66BRAC+4vER6y14bEvt+3LEOQzO1g42/DHyOAcCQukK2SUWsQ9Ei6TvOE7wvNAc2ByAmBXAjMjZGeXxdf0RJttmQMgW2uC3lj/ACN3B2AVpoMiTt0HaFi2Svitni2UfEyBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778477414; c=relaxed/simple; bh=QeZk6I6vDb94k17HTc7BL5zwbPsYJmsXJ1vRZR+UJOo=; h=From:To:CC:Subject:Date:Message-ID:Content-Type:MIME-Version; b=A+7ZK5pv7ZZ79QOv/tOF1ELTKnp30qsvY9YNbHcZ5vRkTdmvn7lm1IB+SAI2DWYdnoHaxyPxy6ePwczBFzJ7eN/ZSu8c8k8Cbxh9mu3eCL9k1eIYfVUzGJzH+22Xo9/HQnKz4BugtlgFpGHZZ2UmZXxVPddBvfBDySmnqfArkQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=W2LCJyyZ; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="W2LCJyyZ" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 06C9E2C03DB for ; Mon, 11 May 2026 17:30:04 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1778477404; bh=QeZk6I6vDb94k17HTc7BL5zwbPsYJmsXJ1vRZR+UJOo=; h=From:To:CC:Subject:Date:From; b=W2LCJyyZpAwARVJJdbjgZZgsIONgKQ4+Kyhp28FB/YWa94kcuVoaNEdJ7jmNpMZ3Q b5e/g+WNgEIwhCNMl/JbzxkeaqPiead36DNIn351jbeY5IaGtWqeofxeNQT/QxTGU7 aOaFAKWljb04XEgwLt9msE4PY+UudALqKvuqBkC6+VnoImewNBfa61+vFMJ9lWUYe/ aXZ/KsgMJfmKKN6TwHqwmIKkX5KPNIY+87UjFpJvnsR4k2YS4odKi6TWAAdT2TxKTa aZox5F0Na2vprcQuFr4EDcAMNQm2Mk8Lq5Ck743aR3mAV4T24pLX+cCG02id51P3xl rfZ+fs6DGmOBw== Received: from svr-chch-ex2.atlnz.lc (Not Verified[2001:df5:b000:bc8::76]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 11 May 2026 17:30:03 +1200 Received: from svr-chch-ex2.atlnz.lc (2001:df5:b000:bc8::76) by svr-chch-ex2.atlnz.lc (2001:df5:b000:bc8::76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.39; Mon, 11 May 2026 17:30:03 +1200 Received: from svr-chch-ex2.atlnz.lc ([fe80::a9eb:c9b7:8b52:9567]) by svr-chch-ex2.atlnz.lc ([fe80::a9eb:c9b7:8b52:9567%15]) with mapi id 15.02.1748.039; Mon, 11 May 2026 17:30:03 +1200 From: Mark Tomlinson To: "linux@armlinux.org.uk" CC: "linux-kernel@vger.kernel.org" , "thomas.petazzoni@bootlin.com" Subject: ARM deadlock with PL310 on Armada-38x Thread-Topic: ARM deadlock with PL310 on Armada-38x Thread-Index: AQHc4Qc4jY+P670/90OnC0i7mf4/Rw== Date: Mon, 11 May 2026 05:30:03 +0000 Message-ID: Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="utf-8" Content-ID: <1C4C4A291B817D498215D01FEB962EDD@alliedtelesis.co.nz> Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=FPe4xPos c=1 sm=1 tr=0 ts=6a01695b a=Xf/6aR1Nyvzi7BryhOrcLQ==:117 a=xqWC_Br6kY4A:10 a=3pNRdvVr4ggA:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=hpJrrrpKso11i55GIIQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-SEG-SpamProfiler-Score: 0 I have encountered an issue where, during allocation of DMA memory, the CPU can deadlock, requiring a reset to clear. Although I have a work-around I need some more information in order to make a patch I can be confident in. I have found the patch 98ea2dba6593 "ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache" documents that writing to any PL310 register could cause a deadlock, and it disables the ->sync call to prevent this. If I also disable the ->flush_range call I do not get my deadlock, and everything seems fine. However, Thomas' patch also states that these calls are necessary during secondary CPU boot, so I am worried my patch is not complete. The CPU I am using is dual-core, and although I'm not currently experiencing any issue, there may be a latent bug. I am not sure the best way to fix this, if it indeed is an issue. Finally, Thomas' patch is only active when "arm,io-coherent" is added to the DTS file. Although the comments imply that this code is necessary for the Armada 375/38x, this DTS change is not in the dtsi files for these CPUs. I find that a bit puzzling. Here is my current patch to avoid the deadlock: diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi index 1181b13deabc..21c813a8222e 100644 --- a/arch/arm/boot/dts/marvell/armada-38x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -110,6 +110,7 @@ sdramc: sdramc@1400 { =20 L2: cache-controller@8000 { compatible =3D "arm,pl310-cache"; + arm,io-coherent; reg =3D <0x8000 0x1000>; cache-unified; cache-level =3D <2>; diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 43d91bfd2360..6742e9934344 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1341,7 +1341,6 @@ static const struct l2c_init_data of_l2c310_coherent_data __initconst =3D { .outer_cache =3D { .inv_range =3D l2c210_inv_range, .clean_range =3D l2c210_clean_range, - .flush_range =3D l2c210_flush_range, .flush_all =3D l2c210_flush_all, .disable =3D l2c310_disable, .resume =3D l2c310_resume,