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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 07:58:02.5043 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e728bb1-fa0c-441f-0bf0-08dd773c40dd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5751 Content-Type: text/plain; charset="utf-8" Uncore counters do not provide mechanisms like interrupts to report overflows and the accumulated user-visible count is incorrect if there is more than one overflow between two successive read requests for the same event because the value of prev_count goes out-of-date for calculating the correct delta. To avoid this, start a hrtimer to periodically initiate a pmu->read() of the active counters for keeping prev_count up-to-date. It should be noted that the hrtimer duration should be lesser than the shortest time it takes for a counter to overflow for this approach to be effective. Signed-off-by: Sandipan Das --- arch/x86/events/amd/uncore.c | 72 ++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 010024f09f2c..ee6528f2189f 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -21,6 +21,7 @@ #define NUM_COUNTERS_NB 4 #define NUM_COUNTERS_L2 4 #define NUM_COUNTERS_L3 6 +#define NUM_COUNTERS_MAX 64 =20 #define RDPMC_BASE_NB 6 #define RDPMC_BASE_LLC 10 @@ -38,6 +39,10 @@ struct amd_uncore_ctx { int refcnt; int cpu; struct perf_event **events; + unsigned long active_mask[BITS_TO_LONGS(NUM_COUNTERS_MAX)]; + int nr_active; + struct hrtimer hrtimer; + u64 hrtimer_duration; }; =20 struct amd_uncore_pmu { @@ -87,6 +92,51 @@ static struct amd_uncore_pmu *event_to_amd_uncore_pmu(st= ruct perf_event *event) return container_of(event->pmu, struct amd_uncore_pmu, pmu); } =20 +static enum hrtimer_restart amd_uncore_hrtimer(struct hrtimer *hrtimer) +{ + struct amd_uncore_ctx *ctx; + struct perf_event *event; + unsigned long flags; + int bit; + + ctx =3D container_of(hrtimer, struct amd_uncore_ctx, hrtimer); + + if (!ctx->nr_active || ctx->cpu !=3D smp_processor_id()) + return HRTIMER_NORESTART; + + /* + * Disable local interrupts to prevent pmu->start() or pmu->stop() + * from interrupting the update process + */ + local_irq_save(flags); + + for_each_set_bit(bit, ctx->active_mask, NUM_COUNTERS_MAX) { + event =3D ctx->events[bit]; + event->pmu->read(event); + } + + local_irq_restore(flags); + + hrtimer_forward_now(hrtimer, ns_to_ktime(ctx->hrtimer_duration)); + return HRTIMER_RESTART; +} + +static void amd_uncore_start_hrtimer(struct amd_uncore_ctx *ctx) +{ + hrtimer_start(&ctx->hrtimer, ns_to_ktime(ctx->hrtimer_duration), + HRTIMER_MODE_REL_PINNED); +} + +static void amd_uncore_cancel_hrtimer(struct amd_uncore_ctx *ctx) +{ + hrtimer_cancel(&ctx->hrtimer); +} + +static void amd_uncore_init_hrtimer(struct amd_uncore_ctx *ctx) +{ + hrtimer_setup(&ctx->hrtimer, amd_uncore_hrtimer, CLOCK_MONOTONIC, HRTIMER= _MODE_REL); +} + static void amd_uncore_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; @@ -117,18 +167,26 @@ static void amd_uncore_read(struct perf_event *event) =20 static void amd_uncore_start(struct perf_event *event, int flags) { + struct amd_uncore_pmu *pmu =3D event_to_amd_uncore_pmu(event); + struct amd_uncore_ctx *ctx =3D *per_cpu_ptr(pmu->ctx, event->cpu); struct hw_perf_event *hwc =3D &event->hw; =20 + if (!ctx->nr_active++) + amd_uncore_start_hrtimer(ctx); + if (flags & PERF_EF_RELOAD) wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); =20 hwc->state =3D 0; + __set_bit(hwc->idx, ctx->active_mask); wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); perf_event_update_userpage(event); } =20 static void amd_uncore_stop(struct perf_event *event, int flags) { + struct amd_uncore_pmu *pmu =3D event_to_amd_uncore_pmu(event); + struct amd_uncore_ctx *ctx =3D *per_cpu_ptr(pmu->ctx, event->cpu); struct hw_perf_event *hwc =3D &event->hw; =20 wrmsrl(hwc->config_base, hwc->config); @@ -138,6 +196,11 @@ static void amd_uncore_stop(struct perf_event *event, = int flags) event->pmu->read(event); hwc->state |=3D PERF_HES_UPTODATE; } + + if (!--ctx->nr_active) + amd_uncore_cancel_hrtimer(ctx); + + __clear_bit(hwc->idx, ctx->active_mask); } =20 static int amd_uncore_add(struct perf_event *event, int flags) @@ -490,6 +553,9 @@ static int amd_uncore_ctx_init(struct amd_uncore *uncor= e, unsigned int cpu) goto fail; } =20 + amd_uncore_init_hrtimer(curr); + curr->hrtimer_duration =3D 60LL * NSEC_PER_SEC; + cpumask_set_cpu(cpu, &pmu->active_mask); } =20 @@ -879,12 +945,18 @@ static int amd_uncore_umc_event_init(struct perf_even= t *event) =20 static void amd_uncore_umc_start(struct perf_event *event, int flags) { + struct amd_uncore_pmu *pmu =3D event_to_amd_uncore_pmu(event); + struct amd_uncore_ctx *ctx =3D *per_cpu_ptr(pmu->ctx, event->cpu); struct hw_perf_event *hwc =3D &event->hw; =20 + if (!ctx->nr_active++) + amd_uncore_start_hrtimer(ctx); + if (flags & PERF_EF_RELOAD) wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); =20 hwc->state =3D 0; + __set_bit(hwc->idx, ctx->active_mask); wrmsrl(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC)); perf_event_update_userpage(event); } --=20 2.43.0