From nobody Sat Sep 21 06:45:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 345BDC636CC for ; Fri, 3 Feb 2023 07:04:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232127AbjBCHEX (ORCPT ); Fri, 3 Feb 2023 02:04:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231579AbjBCHEV (ORCPT ); Fri, 3 Feb 2023 02:04:21 -0500 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B0204B8A8; Thu, 2 Feb 2023 23:03:46 -0800 (PST) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1pNq6o-0000qD-0K; Fri, 03 Feb 2023 08:03:42 +0100 Date: Fri, 3 Feb 2023 07:02:01 +0000 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Russell King , Heiner Kallweit , Lorenzo Bianconi , Mark Lee , John Crispin , Felix Fietkau , AngeloGioacchino Del Regno , Matthias Brugger , DENG Qingfang , Landen Chao , Sean Wang , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Vladimir Oltean , Florian Fainelli , Andrew Lunn Cc: Jianhui Zhao , =?iso-8859-1?Q?Bj=F8rn?= Mork Subject: [PATCH 4/9] net: ethernet: mtk_eth_soc: only write values if needed Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only restart auto-negotiation and write link timer if actually necessary. Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index f3cf66a23e72..58b5f2f70a66 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -41,17 +41,13 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsi= gned int mode, struct mtk_pcs *mpcs =3D pcs_to_mtk_pcs(pcs); unsigned int rgc3, sgm_mode, bmcr; int advertise, link_timer; - bool changed, use_an; + bool mode_changed =3D false, changed, use_an; =20 advertise =3D phylink_mii_c22_pcs_encode_advertisement(interface, advertising); if (advertise < 0) return advertise; =20 - link_timer =3D phylink_get_link_timer_ns(interface); - if (link_timer < 0) - return link_timer; - /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and * we assume that fixes it's speed at bitrate =3D line rate (in * other words, 1000Mbps or 2500Mbps). @@ -77,8 +73,7 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsign= ed int mode, } =20 if (use_an) { - /* FIXME: Do we need to set AN_RESTART here? */ - bmcr =3D SGMII_AN_RESTART | SGMII_AN_ENABLE; + bmcr =3D SGMII_AN_ENABLE; } else { bmcr =3D 0; } @@ -106,16 +101,21 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, un= signed int mode, regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3, RG_PHY_SPEED_3_125G, rgc3); =20 + /* Setup the link timer and QPHY power up inside SGMIISYS */ + link_timer =3D phylink_get_link_timer_ns(interface); + if (link_timer < 0) + return link_timer; + + regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8); + mpcs->interface =3D interface; + mode_changed =3D true; } =20 /* Update the advertisement, noting whether it has changed */ regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE, SGMII_ADVERTISE, advertise, &changed); =20 - /* Setup the link timer and QPHY power up inside SGMIISYS */ - regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8); - /* Update the sgmsys mode register */ regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN | @@ -123,7 +123,7 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsi= gned int mode, =20 /* Update the BMCR */ regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, - SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr); + SGMII_AN_ENABLE, bmcr); =20 /* Release PHYA power down state * Only removing bit SGMII_PHYA_PWD isn't enough. @@ -137,7 +137,7 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsi= gned int mode, usleep_range(50, 100); regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); =20 - return changed; + return changed || mode_changed; } =20 static void mtk_pcs_restart_an(struct phylink_pcs *pcs) --=20 2.39.1