From nobody Sun Nov 24 06:03:37 2024 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 254101CCEFC; Tue, 19 Nov 2024 12:54:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732020892; cv=none; b=PLEgl9sAJykhA545tvLK3S7XYah09ufIjcEnpGsw9+ISNhKiHSYt0hfeR4h0ozIuzH/TcPbLIT3CCUeHH7pU6IQScRT1FHfaM0jCLMHoiklGP7msmplp9yIxBWhiFqhUFR0h6Hk2ZiqwJLiIyRoYaipLXa65tmkM6yFCK2geK90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732020892; c=relaxed/simple; bh=0NtJLeywE+5TIOBJlVnnpu8TszEYpxScCqZ+saKDLZE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uUgQ87amUvYR4F8jgXvB+teN2U/+f4MB7w0s//wCsusVJHmNsx23L1gwXDxJahurhUVM9+BI3a5gRN2x7GaY6q0yIjaEdjO27TqhrWJjKPtLnXkXjkhdopqoqhdDjxadCn1tAofXME4LUt1rizwSr2Cc2Zmv3b8V8deJtR5DTsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=wMSZ+HFh; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="wMSZ+HFh" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AJB18gM009127; Tue, 19 Nov 2024 07:54:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=ATPUJ Fb2+7Q0aIr6pLA77tNE670dlGb9JHs4u0ZKanc=; b=wMSZ+HFhSKXq/HXwU70or oV15qa1xgp8Xc3lmR1aTGXAS/5k04h+rGszct8kEuprsbLGDwMXhti793XhxJldw IlTpJhEBZ+t+sszo10LnS8Z5kl8nOZRTlNZSQzCY86ngfOWoAz/2MXIXcFbxpxfH dfwIEag2Bn++A8nafjv6riTwD5M51+nrZq1r0I/fRfdqyErWxr2c0Ma6CE5dCnRh nqfJw98xT+1fScbYRZX+iDWOCJkfxSCvzvcVy3jLfrg5fzrJhu23VhC/9ry8Wk0w WS95VtKa+HtGelkVq5lZuSM/legG4YvIhdEOljzu4rCnL7QU4P92A0U6fSlTq0LV g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 430seageje-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Nov 2024 07:54:37 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 4AJCsaTb005026 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Nov 2024 07:54:36 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 19 Nov 2024 07:54:36 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 19 Nov 2024 07:54:35 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 4AJCsOOD007325; Tue, 19 Nov 2024 07:54:27 -0500 From: Marcelo Schmitt To: , , , , , , , CC: , , Subject: [PATCH v3 3/4] iio: adc: ad4000: Use device specific timing for SPI transfers Date: Tue, 19 Nov 2024 09:54:22 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: w1bXRaGFWh2B7bHw8PBN3V4vWyK9IA3a X-Proofpoint-ORIG-GUID: w1bXRaGFWh2B7bHw8PBN3V4vWyK9IA3a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411190095 Content-Type: text/plain; charset="utf-8" The SPI transfers for AD4020, AD4021, and AD4022 have slightly different timing specifications. Use device specific timing constraints to set SPI transfer parameters. While tweaking time constraints, remove time related defines including unused AD4000_TQUIET1_NS. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4000.c | 51 +++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad4000.c b/drivers/iio/adc/ad4000.c index 21731c4d31ee..c700d51b5637 100644 --- a/drivers/iio/adc/ad4000.c +++ b/drivers/iio/adc/ad4000.c @@ -35,10 +35,6 @@ =20 #define AD4000_SCALE_OPTIONS 2 =20 -#define AD4000_TQUIET1_NS 190 -#define AD4000_TQUIET2_NS 60 -#define AD4000_TCONV_NS 320 - #define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_acces= s) \ { \ .type =3D IIO_VOLTAGE, \ @@ -122,10 +118,31 @@ static const int ad4000_gains[] =3D { 454, 909, 1000, 1900, }; =20 +struct ad4000_time_spec { + int t_conv_ns; + int t_quiet2_ns; +}; + +/* + * Same timing specifications for all of AD4000, AD4001, ..., AD4008, AD40= 10, + * ADAQ4001, and ADAQ4003. + */ +static const struct ad4000_time_spec ad4000_t_spec =3D { + .t_conv_ns =3D 320, + .t_quiet2_ns =3D 60, +}; + +/* AD4020, AD4021, AD4022 */ +static const struct ad4000_time_spec ad4020_t_spec =3D { + .t_conv_ns =3D 350, + .t_quiet2_ns =3D 60, +}; + struct ad4000_chip_info { const char *dev_name; struct iio_chan_spec chan_spec[2]; struct iio_chan_spec reg_access_chan_spec[2]; + const struct ad4000_time_spec *time_spec; bool has_hardware_gain; }; =20 @@ -133,90 +150,105 @@ static const struct ad4000_chip_info ad4000_chip_inf= o =3D { .dev_name =3D "ad4000", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4001_chip_info =3D { .dev_name =3D "ad4001", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4002_chip_info =3D { .dev_name =3D "ad4002", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4003_chip_info =3D { .dev_name =3D "ad4003", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4004_chip_info =3D { .dev_name =3D "ad4004", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4005_chip_info =3D { .dev_name =3D "ad4005", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4006_chip_info =3D { .dev_name =3D "ad4006", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4007_chip_info =3D { .dev_name =3D "ad4007", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4008_chip_info =3D { .dev_name =3D "ad4008", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4010_chip_info =3D { .dev_name =3D "ad4010", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4011_chip_info =3D { .dev_name =3D "ad4011", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4020_chip_info =3D { .dev_name =3D "ad4020", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .time_spec =3D &ad4020_t_spec, }; =20 static const struct ad4000_chip_info ad4021_chip_info =3D { .dev_name =3D "ad4021", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .time_spec =3D &ad4020_t_spec, }; =20 static const struct ad4000_chip_info ad4022_chip_info =3D { .dev_name =3D "ad4022", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .time_spec =3D &ad4020_t_spec, }; =20 static const struct ad4000_chip_info adaq4001_chip_info =3D { .dev_name =3D "adaq4001", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .time_spec =3D &ad4000_t_spec, .has_hardware_gain =3D true, }; =20 @@ -224,6 +256,7 @@ static const struct ad4000_chip_info adaq4003_chip_info= =3D { .dev_name =3D "adaq4003", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, .has_hardware_gain =3D true, }; =20 @@ -238,6 +271,7 @@ struct ad4000_state { bool span_comp; u16 gain_milli; int scale_tbl[AD4000_SCALE_OPTIONS][2]; + const struct ad4000_time_spec *time_spec; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -502,16 +536,15 @@ static const struct iio_info ad4000_info =3D { static int ad4000_prepare_3wire_mode_message(struct ad4000_state *st, const struct iio_chan_spec *chan) { - unsigned int cnv_pulse_time =3D AD4000_TCONV_NS; struct spi_transfer *xfers =3D st->xfers; =20 xfers[0].cs_change =3D 1; - xfers[0].cs_change_delay.value =3D cnv_pulse_time; + xfers[0].cs_change_delay.value =3D st->time_spec->t_conv_ns; xfers[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 xfers[1].rx_buf =3D &st->scan.data; xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); - xfers[1].delay.value =3D AD4000_TQUIET2_NS; + xfers[1].delay.value =3D st->time_spec->t_quiet2_ns; xfers[1].delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 spi_message_init_with_transfers(&st->msg, st->xfers, 2); @@ -529,7 +562,6 @@ static int ad4000_prepare_3wire_mode_message(struct ad4= 000_state *st, static int ad4000_prepare_4wire_mode_message(struct ad4000_state *st, const struct iio_chan_spec *chan) { - unsigned int cnv_to_sdi_time =3D AD4000_TCONV_NS; struct spi_transfer *xfers =3D st->xfers; =20 /* @@ -537,7 +569,7 @@ static int ad4000_prepare_4wire_mode_message(struct ad4= 000_state *st, * going low. */ xfers[0].cs_off =3D 1; - xfers[0].delay.value =3D cnv_to_sdi_time; + xfers[0].delay.value =3D st->time_spec->t_conv_ns; xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 xfers[1].rx_buf =3D &st->scan.data; @@ -576,6 +608,7 @@ static int ad4000_probe(struct spi_device *spi) =20 st =3D iio_priv(indio_dev); st->spi =3D spi; + st->time_spec =3D chip->time_spec; =20 ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4000_power_suppl= ies), ad4000_power_supplies); --=20 2.45.2