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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2025 15:03:39.0731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c063834-9419-4146-dd5d-08ddea31e626 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7274 Content-Type: text/plain; charset="utf-8" Add missing cache layout description. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/versal-net.dtsi | 248 +++++++++++++++++++++ 1 file changed, 248 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/d= ts/xilinx/versal-net.dtsi index c037a7819967..62861138c8f4 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -104,6 +104,18 @@ cpu0: cpu@0 { reg =3D <0>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_00>; + l2_00: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; }; cpu100: cpu@100 { compatible =3D "arm,cortex-a78"; @@ -112,6 +124,18 @@ cpu100: cpu@100 { reg =3D <0x100>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_01>; + l2_01: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; }; cpu200: cpu@200 { compatible =3D "arm,cortex-a78"; @@ -120,6 +144,18 @@ cpu200: cpu@200 { reg =3D <0x200>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_02>; + l2_02: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; }; cpu300: cpu@300 { compatible =3D "arm,cortex-a78"; @@ -128,6 +164,18 @@ cpu300: cpu@300 { reg =3D <0x300>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_03>; + l2_03: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; }; cpu10000: cpu@10000 { compatible =3D "arm,cortex-a78"; @@ -136,6 +184,18 @@ cpu10000: cpu@10000 { reg =3D <0x10000>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_10>; + l2_10: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; }; cpu10100: cpu@10100 { compatible =3D "arm,cortex-a78"; @@ -144,6 +204,18 @@ cpu10100: cpu@10100 { reg =3D <0x10100>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_11>; + l2_11: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; }; cpu10200: cpu@10200 { compatible =3D "arm,cortex-a78"; @@ -152,6 +224,18 @@ cpu10200: cpu@10200 { reg =3D <0x10200>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_12>; + l2_12: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; }; cpu10300: cpu@10300 { compatible =3D "arm,cortex-a78"; @@ -160,6 +244,18 @@ cpu10300: cpu@10300 { reg =3D <0x10300>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_13>; + l2_13: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; }; cpu20000: cpu@20000 { compatible =3D "arm,cortex-a78"; @@ -168,6 +264,18 @@ cpu20000: cpu@20000 { reg =3D <0x20000>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_20>; + l2_20: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_2>; + }; }; cpu20100: cpu@20100 { compatible =3D "arm,cortex-a78"; @@ -176,6 +284,18 @@ cpu20100: cpu@20100 { reg =3D <0x20100>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_21>; + l2_21: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_2>; + }; }; cpu20200: cpu@20200 { compatible =3D "arm,cortex-a78"; @@ -184,6 +304,18 @@ cpu20200: cpu@20200 { reg =3D <0x20200>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_22>; + l2_22: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_2>; + }; }; cpu20300: cpu@20300 { compatible =3D "arm,cortex-a78"; @@ -192,6 +324,18 @@ cpu20300: cpu@20300 { reg =3D <0x20300>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_23>; + l2_23: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_2>; + }; }; cpu30000: cpu@30000 { compatible =3D "arm,cortex-a78"; @@ -200,6 +344,18 @@ cpu30000: cpu@30000 { reg =3D <0x30000>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_30>; + l2_30: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_3>; + }; }; cpu30100: cpu@30100 { compatible =3D "arm,cortex-a78"; @@ -208,6 +364,18 @@ cpu30100: cpu@30100 { reg =3D <0x30100>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_31>; + l2_31: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_3>; + }; }; cpu30200: cpu@30200 { compatible =3D "arm,cortex-a78"; @@ -216,6 +384,18 @@ cpu30200: cpu@30200 { reg =3D <0x30200>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_32>; + l2_32: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_3>; + }; }; cpu30300: cpu@30300 { compatible =3D "arm,cortex-a78"; @@ -224,7 +404,75 @@ cpu30300: cpu@30300 { reg =3D <0x30300>; operating-points-v2 =3D <&cpu_opp_table>; cpu-idle-states =3D <&CPU_SLEEP_0>; + next-level-cache =3D <&l2_33>; + l2_33: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; /* 512kB */ + cache-line-size =3D <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&l3_3>; + }; + }; + + l3_0: l3-0-cache { /* cluster private */ + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x200000>; /* 2MB */ + cache-line-size =3D <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&llc>; + }; + + l3_1: l3-1-cache { /* cluster private */ + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x200000>; /* 2MB */ + cache-line-size =3D <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&llc>; + }; + + l3_2: l3-2-cache { /* cluster private */ + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x200000>; /* 2MB */ + cache-line-size =3D <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&llc>; + }; + + l3_3: l3-3-cache { /* cluster private */ + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x200000>; /* 2MB */ + cache-line-size =3D <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&llc>; + }; + + llc: l4-cache { /* LLC inside CMN */ + compatible =3D "cache"; + cache-level =3D <4>; + cache-size =3D <0x1000000>; /* 16MB */ + cache-unified; }; + idle-states { entry-method =3D "psci"; =20 --=20 2.43.0 base-commit: 3160658ea2c4dd09a1d68918271177cf55437a8f