From nobody Fri Apr 3 01:24:33 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCC002C3757 for ; Sun, 15 Feb 2026 08:55:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771145747; cv=none; b=PCtKLekkgxBA7rs7p97rOru5c6uUL8ThT1kiY85M/y3XELwOqfT3+7Pzfx52BFA+TKVmCe+L5A16ORGKi4O74tXhQJwwBdSEbvS4HfGtM2aSMdOvWiW1tRzchiHz0IQ9SWDAyRLTr3GSz4kvA/ibkIt1N7Pa73Kc9x1QpmtNkww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771145747; c=relaxed/simple; bh=qfwcnFi77p2rcOG/oSUsUf4wTJFkZNPOsw/D/70PXKc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ezr9OxC6+Addm16W26G6h2Xbpn8lKEteAw941v9qY6AYGEQWdOjRXuGbdnj2Ozn7ANYnGlVXpW6eFaH6N8mppwPl8rU5nn2pCDYFKl0YDXEmaXx0wC7NtlrrFSWD+PvFT7dTka9kcckMkESVkL+J8ddHgSjsV/x/fBvMQCwkZJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ceWlvB/b; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ceWlvB/b" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-48378136adcso9821515e9.1 for ; Sun, 15 Feb 2026 00:55:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771145744; x=1771750544; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tMkpYF7y2Q4cqPGN71X2yW3ov4J2sqIdlYQITivE9qI=; b=ceWlvB/b29Ywtz8uKixnGMlViOjSyHGxc2tGop5gepcFzKdawQKK278HD/XoMZAVey cYfHavbqBdKbAETI+yQFya9foX09Crgg7snxYB4myTX4zTi/5IpZJDqfYq6LRwL92NNb +NsDyf0abn+GB312SSePI5+TuQ3p2o0MnFPgf/vCQp8759jR7A1djfxfRH/eqGZrAvsr 6AzL+GKEtdtkzJGdAepXGHIkK5MmUT4CyCl/pVRex4jrhxRRwcQDsLuKiU7dgsjQOzrZ RlSFFKHjZVNUPh8D9JnXotVFFTQWu+vf9zNIqRiu7KHwVFdDGgC7+OntnenzJMoOJdvy S5pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771145744; x=1771750544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=tMkpYF7y2Q4cqPGN71X2yW3ov4J2sqIdlYQITivE9qI=; b=R9vE+Mt5B+UqcnsljGDw+GkI7tukL4ebn4tkg+w/lCgwJ++fMzMGEDNczjllwCJMhy EVtX7G+JdP5/tRACk1b7UOQe9z7MWePKdXBTPo64FMdKWZ79gp2PFzVqWm2k3Its5Zq2 iA1DqFfD82yXTkb8aIwtS0n1o+SZXh60ozewMHLCwcskOodBHMmuItZmUEUsFWqaePyg LbR5DjHfLaUaAc6ZCCY43jX1GkALhMUiekCjJbvxH5cwcA01jaJzZXGKEhiTRXmeM2Wv eqtfnYWBXLf82WNNmAAikhZ9jRlg+i9YiCGdxQ1gSiuX9yp225ghuUY0Y0Se1vUvQpxe bJ9Q== X-Forwarded-Encrypted: i=1; AJvYcCVgXXHs9WQhOu6aKwl5BSam9iQiaFK9Dro7oBSCFPIHw3Qb0VaSkKIQklCtsBsbv2IYraIGcXvst7X8JSI=@vger.kernel.org X-Gm-Message-State: AOJu0Yxuc+1txGegdNH4RVzVzBM+eP7Ly/CnRQf9wTTTp6QaSxStMut1 e/gOQVPOfYBThWdAx3+v/KonG9w0EEkqLu2kK4nzj9Mp/a67DWW32DL0 X-Gm-Gg: AZuq6aJHoFSM2LwwVxiZ0+V2GRU47gMKh0FWTka65zVG0EyXy8gwV6BezeBd9u9FLb1 4d4UL+nVUMuo+wjbE8CpEJG/YmdPPFzwj84RZICsfvi5V+IYZlzfRyuApNH3KSFKx2v+7UUCQ6A 8wJhCznnoD4Pj4qPBtwv8FofwZM8Tyob9Vqzz+BHiJofhyA6xNkG2DlRtQVoJn8a9i20ijGEJaG qCXHonoLtZguWshplIY7dMGA1AJ1prjzOnuKonPUrK88dDfKpcFPt7Tn7jx298vkZjdCjL9XX35 PV/fVWl9FEumhUatYX9QOe20wW7gnvsnVbLWKfNlPqzmpL02rtoDeBnutZrPu1EUBqJvLqMm6mb lH5BLStpvh7kqsHSuJw/ngSAGof1BIH9S4CI6H+ZDLhCfTYLPctZ8Sp+HOkXXbwTwqroLxP+ZX4 nbA+3jWZegGz0QdsYU5DV/XaoDB+J9fw== X-Received: by 2002:a05:600c:609a:b0:483:7020:864 with SMTP id 5b1f17b1804b1-48379c178eamr79445925e9.25.1771145744106; Sun, 15 Feb 2026 00:55:44 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d78cfsm547211675e9.1.2026.02.15.00.55.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Feb 2026 00:55:43 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH 3/4] arm64: dts: mediatek: mt8167: Add DRM nodes Date: Sun, 15 Feb 2026 08:53:55 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add all the DRM nodes required to get DSI to work on MT8167 SoC. Signed-off-by: Luca Leonardo Scorcia --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 386 +++++++++++++++++++++++ 1 file changed, 386 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts= /mediatek/mt8167.dtsi index 27cf32d7ae35..c6306234e592 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -16,6 +16,20 @@ / { compatible =3D "mediatek,mt8167"; =20 + aliases { + aal0 =3D &aal; + ccorr0 =3D &ccorr; + color0 =3D &color; + dither0 =3D &dither; + dsi0 =3D &dsi; + gamma0 =3D γ + ovl0 =3D &ovl0; + pwm0 =3D &disp_pwm; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + wdma0 =3D &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible =3D "mediatek,mt8167-topckgen", "syscon"; @@ -120,10 +134,371 @@ iommu: m4u@10203000 { #iommu-cells =3D <1>; }; =20 + disp_pwm: pwm@1100f000 { + compatible =3D "mediatek,mt8167-disp-pwm", + "mediatek,mt8173-disp-pwm"; + reg =3D <0 0x1100f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_PWM_26M>, + <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names =3D "main", + "mm"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + mmsys: syscon@14000000 { compatible =3D "mediatek,mt8167-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; #clock-cells =3D <1>; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mmsys_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + + mmsys_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_in>; + }; + }; + }; + + ovl0: ovl0@14007000 { + compatible =3D "mediatek,mt8167-disp-ovl"; + reg =3D <0 0x14007000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ovl0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mmsys_main>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ovl0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color_in>; + }; + }; + }; + }; + + rdma0: rdma0@14009000 { + compatible =3D "mediatek,mt8167-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg =3D <0 0x14009000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dsi_in>; + }; + }; + }; + }; + + rdma1: rdma1@1400a000 { + compatible =3D "mediatek,mt8167-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg =3D <0 0x1400a000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma1_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma1_out: endpoint@0 { + reg =3D <0>; + }; + }; + }; + }; + + wdma: wdma0@1400b000 { + compatible =3D "mediatek,mt8167-disp-wdma", + "mediatek,mt8173-disp-wdma"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_WDMA>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_WDMA0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + }; + + color: color@1400c000 { + compatible =3D "mediatek,mt8167-disp-color"; + reg =3D <0 0x1400c000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + color_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + color_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr_in>; + }; + }; + }; + }; + + ccorr: ccorr@1400d000 { + compatible =3D "mediatek,mt8167-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ccorr_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ccorr_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal_in>; + }; + }; + }; + }; + + aal: aal@1400e000 { + compatible =3D "mediatek,mt8167-disp-aal", + "mediatek,mt8173-disp-aal"; + reg =3D <0 0x1400e000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_AAL>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + aal_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + aal_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma_in>; + }; + }; + }; + }; + + gamma: gamma@1400f000 { + compatible =3D "mediatek,mt8167-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + gamma_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + gamma_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither_in>; + }; + }; + }; + }; + + dither: dither@14010000 { + compatible =3D "mediatek,mt8167-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x14010000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dither_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dither_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_in>; + }; + }; + }; + }; + + dsi: dsi@14012000 { + compatible =3D "mediatek,mt8167-dsi", + "mediatek,mt2701-dsi"; + reg =3D <0 0x14012000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names =3D "engine", "digital", "hs"; + interrupts =3D ; + phys =3D <&mipi_tx>; + phy-names =3D "dphy"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dsi_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dsi_out: endpoint@0 { + reg =3D <0>; + }; + }; + }; + }; + + mutex: mutex@14015000 { + compatible =3D "mediatek,mt8167-disp-mutex"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 larb0: larb@14016000 { @@ -145,6 +520,17 @@ smi_common: smi@14017000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 + mipi_tx: dsi-phy@14018000 { + compatible =3D "mediatek,mt8167-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg =3D <0 0x14018000 0 0x90>; + clocks =3D <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names =3D "mipi_tx0_pll"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + imgsys: syscon@15000000 { compatible =3D "mediatek,mt8167-imgsys", "syscon"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.43.0