From nobody Wed Nov 13 06:55:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DEFCC64EC4 for ; Thu, 9 Mar 2023 11:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230113AbjCILFL (ORCPT ); Thu, 9 Mar 2023 06:05:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjCILEd (ORCPT ); Thu, 9 Mar 2023 06:04:33 -0500 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98F8CE91AE; Thu, 9 Mar 2023 02:59:40 -0800 (PST) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1paDzm-0003eR-0f; Thu, 09 Mar 2023 11:59:38 +0100 Date: Thu, 9 Mar 2023 10:58:00 +0000 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Russell King , Heiner Kallweit , Lorenzo Bianconi , Mark Lee , John Crispin , Felix Fietkau , AngeloGioacchino Del Regno , Matthias Brugger , DENG Qingfang , Landen Chao , Sean Wang , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Vladimir Oltean , Florian Fainelli , Andrew Lunn , Vladimir Oltean Cc: =?iso-8859-1?Q?Bj=F8rn?= Mork , Frank Wunderlich , Alexander Couzens Subject: [PATCH net-next v13 12/16] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability bit Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi Introduce MTK_NETSYS_V1 bit in the device capabilities for MT7621/MT7622/MT7623/MT7628/MT7629 SoCs. Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase. This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++--------- 2 files changed, 41 insertions(+), 34 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 4d18e88aa02d..15985e8ed49e 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -658,7 +658,7 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, un= signed int idx, FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | MTK_QTX_SCH_LEAKY_BUCKET_SIZE; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) val |=3D MTK_QTX_SCH_LEAKY_BUCKET_EN; =20 if (IS_ENABLED(CONFIG_SOC_MT7621)) { @@ -1037,7 +1037,7 @@ static bool mtk_rx_get_desc(struct mtk_eth *eth, stru= ct mtk_rx_dma_v2 *rxd, rxd->rxd1 =3D READ_ONCE(dma_rxd->rxd1); rxd->rxd3 =3D READ_ONCE(dma_rxd->rxd3); rxd->rxd4 =3D READ_ONCE(dma_rxd->rxd4); - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { rxd->rxd5 =3D READ_ONCE(dma_rxd->rxd5); rxd->rxd6 =3D READ_ONCE(dma_rxd->rxd6); } @@ -1095,7 +1095,7 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) =20 txd->txd3 =3D TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); txd->txd4 =3D 0; - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { txd->txd5 =3D 0; txd->txd6 =3D 0; txd->txd7 =3D 0; @@ -1286,7 +1286,7 @@ static void mtk_tx_set_dma_desc(struct net_device *de= v, void *txd, struct mtk_mac *mac =3D netdev_priv(dev); struct mtk_eth *eth =3D mac->hw; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) mtk_tx_set_dma_desc_v2(dev, txd, info); else mtk_tx_set_dma_desc_v1(dev, txd, info); @@ -1937,7 +1937,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, break; =20 /* find out which mac the packet come from. values start at 1 */ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) mac =3D RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) @@ -2033,7 +2033,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, skb->dev =3D netdev; bytes +=3D skb->len; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { reason =3D FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); hash =3D trxd.rxd5 & MTK_RXD5_FOE_ENTRY; if (hash !=3D MTK_RXD5_FOE_ENTRY) @@ -2059,7 +2059,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, mtk_ppe_check_skb(eth->ppe[0], skb, hash); =20 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { if (trxd.rxd3 & RX_DMA_VTAG_V2) { vlan_proto =3D RX_DMA_VPID(trxd.rxd4); vlan_tci =3D RX_DMA_VID(trxd.rxd4); @@ -2384,7 +2384,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) txd->txd2 =3D next_ptr; txd->txd3 =3D TX_DMA_LS0 | TX_DMA_OWNER_CPU; txd->txd4 =3D 0; - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { txd->txd5 =3D 0; txd->txd6 =3D 0; txd->txd7 =3D 0; @@ -2437,7 +2437,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | MTK_QTX_SCH_LEAKY_BUCKET_SIZE; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) val |=3D MTK_QTX_SCH_LEAKY_BUCKET_EN; mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); ofs +=3D MTK_QTX_OFFSET; @@ -2573,7 +2573,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring= _no, int rx_flag) =20 rxd->rxd3 =3D 0; rxd->rxd4 =3D 0; - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { rxd->rxd5 =3D 0; rxd->rxd6 =3D 0; rxd->rxd7 =3D 0; @@ -3139,7 +3139,7 @@ static int mtk_start_dma(struct mtk_eth *eth) MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) val |=3D MTK_MUTLI_CNT | MTK_RESV_BUF | MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; @@ -3542,7 +3542,7 @@ static void mtk_hw_reset(struct mtk_eth *eth) { u32 val; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); val =3D RSTCTRL_PPE0_V2; } else { @@ -3554,7 +3554,7 @@ static void mtk_hw_reset(struct mtk_eth *eth) =20 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0x3ffffff); } @@ -3750,7 +3750,7 @@ static int mtk_hw_init(struct mtk_eth *eth, bool rese= t) else mtk_hw_reset(eth); =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { /* Set FE to PDMAv2 if necessary */ val =3D mtk_r32(eth, MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); @@ -3787,7 +3787,7 @@ static int mtk_hw_init(struct mtk_eth *eth, bool rese= t) */ val =3D mtk_r32(eth, MTK_CDMQ_IG_CTRL); mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { val =3D mtk_r32(eth, MTK_CDMP_IG_CTRL); mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); } diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index 3dfa880da41a..cb3cdf0b38d5 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -820,6 +820,7 @@ enum mkt_eth_capabilities { MTK_SHARED_INT_BIT, MTK_TRGMII_MT7621_CLK_BIT, MTK_QDMA_BIT, + MTK_NETSYS_V1_BIT, MTK_NETSYS_V2_BIT, MTK_SOC_MT7628_BIT, MTK_RSTCTRL_PPE1_BIT, @@ -855,6 +856,7 @@ enum mkt_eth_capabilities { #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) #define MTK_QDMA BIT(MTK_QDMA_BIT) +#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) @@ -911,25 +913,30 @@ enum mkt_eth_capabilities { =20 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) =3D=3D (_x)) =20 -#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ - MTK_GMAC2_RGMII | MTK_SHARED_INT | \ - MTK_TRGMII_MT7621_CLK | MTK_QDMA) - -#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII = | \ - MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ - MTK_MUX_GDM1_TO_GMAC1_ESW | \ - MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) - -#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII= | \ - MTK_QDMA) - -#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) - -#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY = | \ - MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ - MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ - MTK_MUX_U3_GMAC2_TO_QPHY | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) +#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ + MTK_GMAC2_RGMII | MTK_SHARED_INT | \ + MTK_TRGMII_MT7621_CLK | MTK_QDMA | \ + MTK_NETSYS_V1) + +#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \ + MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \ + MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\ + MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \ + MTK_QDMA | MTK_NETSYS_V1) + +#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ + MTK_GMAC2_RGMII | MTK_QDMA | \ + MTK_NETSYS_V1) + +#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \ + MTK_NETSYS_V1) + +#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \ + MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\ + MTK_MUX_GDM1_TO_GMAC1_ESW | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII) =20 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY = | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ --=20 2.39.2