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Mon, 14 Apr 2025 21:58:10 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 02/11] iommu/arm-smmu-v3: Pass in smmu/iommu_domain to __arm_smmu_tlb_inv_range() Date: Mon, 14 Apr 2025 21:57:37 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|BN5PR12MB9510:EE_ X-MS-Office365-Filtering-Correlation-Id: 898d9638-4163-4a31-5a74-08dd7bda25dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014|3613699012; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+HU7UvY9jjvq6eWFoslFg6sAomDh4mVPvmg+/vTqFGo8DIqDBr+eomASEgLG?= =?us-ascii?Q?RC/9ipY9A8JESj3IL/iAvvz96Ls1C3ZLXLUu08KpEZEwtJTIE8ITXNgk4pkR?= =?us-ascii?Q?SxbKtqUiteFf1bfuoKOP/bTihfGG5OZpdKhFXXdlpDYUo3mA/lbfEs/5yvqx?= =?us-ascii?Q?ZybXuVZO3FzahLIgy9HpM12yuMPQfVeUZEcphn3VFdBpK8+9j54Q/iYJaXwg?= =?us-ascii?Q?y7YWcUdYbztCxPy4MVt1nwIGR8GgTHK8dy7ppwcN8sF3B6OTrhInaGPwj+r3?= =?us-ascii?Q?GtqfeuE9qG3sadO1tx8Hab020SyBFe0KLIWcHi1OixgEmUeAhJN/brQ3CO0f?= =?us-ascii?Q?y8OhcQ4Yviu701K+REfWMnPgGiV9fT2W0nxYELKZyS0QitMuq1pOta867lfv?= =?us-ascii?Q?MRGTm1XifS1NrNBGqs1h3d6rZlfK5bleGmCtw72s0ZKQ5g95+ua7wxCUSIZn?= =?us-ascii?Q?tkf9K1CmY1Wj22lrnUjuWm5//zpPUWzE0mhmjOoLApF8TAiVuUBkaIlkYA7W?= =?us-ascii?Q?g8R+0awhHYtN/VcBZLsQgds8ddizvKwneiL39S0hVTmhDE3Lkd7nzBiEgejg?= =?us-ascii?Q?cow3SZEoFJFoyk4GzxyCJjq9mvCpUXGw3S2Eafa4xgt+tsqLiipNPPtaP8pI?= =?us-ascii?Q?pvXkIc+BACaDp3FkC+lllredOE9Z+VWpBa9HAN5qMftSmRJCrNj+VjcNGZtP?= =?us-ascii?Q?vKI6o0zuC8J7et/TBvnR7BEEvh8wvDdIcelpj/NddEElO3QURs40v06kPzzs?= =?us-ascii?Q?D88iDHmRkxN3kZ9nGcnCH/LGnkOV/Pqk5TT137EM7wKYMUbv1O5XiqKMqqi/?= =?us-ascii?Q?K1PbWP+Zm1kUqwXJkmJ2DnpIU1nJDWyFaEy2vzdAY3o73bjuEEGGwKTyPlgW?= =?us-ascii?Q?+ciNNmAHzDNY5h6ExPacjMEoaV+/YW8eBja5yEzJCTXyinJPHZKF3mLsyuaH?= =?us-ascii?Q?TtejLS4DbHq2Gr+dnjpFXjIatrCNUiXuiyQvaAlLM+LLEH2caOpH8xl3J9ET?= =?us-ascii?Q?bMmIAHxhImsH48766alsJqSswV6K0WBi6DhFNv3yXveJ/EaMhgEfeJ0O3PIQ?= =?us-ascii?Q?289oh6yK6+IIhsOFpmHXN2gnMPqhhkf0/ZowW7m1Wnac4nm49+xfm7E80ENZ?= =?us-ascii?Q?TeG0/3Z6YUvyjrsP8VBZmdbw250eDVmh8yphma39Xsl0kcbzxfza/MUGxc1b?= =?us-ascii?Q?0kvpofq7Ad6S4Oi61ri6re7oam9D4vmeN/iGwfN8ezZp3s5nflFJg+vE/vxn?= =?us-ascii?Q?ClP7DB3VfSZCXcW5lww9wMvOJl3zwigB5eXElHueVQrHFccmRZ1wi7YadWhb?= =?us-ascii?Q?HW6SMFDHe+MmbqL94jYHnaIZrFbLFynonuDu3us0b4lwaZoM04Qr68LRzxDM?= =?us-ascii?Q?onyQCkutyez5t4zAecc+ULPhH9X6fYYn8t3AUxq/Buc48Hmng40dZuO1dOAf?= =?us-ascii?Q?olMXWV+nhiI4BJ1Mru5MuWoPaZv8WDJbsKu/UM188iLFrRKdrsELbDjJFipq?= =?us-ascii?Q?Mk28FOzYth3oZ8jh0FnRMJ7uXraieVxgEt7E8/duryGy4nRQDTXHctWiKXf1?= =?us-ascii?Q?BhphzpCBWCnPBuRt9fw=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014)(7416014)(3613699012);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:22.3579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 898d9638-4163-4a31-5a74-08dd7bda25dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9510 Content-Type: text/plain; charset="utf-8" What __arm_smmu_tlb_inv_range() really needs is the smmu and iommu_domain pointers from the smmu_domain. For a nest_parent smmu_domain, it will no longer store an smmu pointer as it can be shared across vSMMU instances. A vSMMU structure sharing the S2 smmu_domain instead would hold the smmu pointer. Pass them in explicitly to fit both !nest_parent and nest_parent cases. While changing it, share it in the header with arm-smmu-v3-iommmufd that will call it too. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 +++++++++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index d4837a33fb81..5dbdc61558a9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -955,6 +955,10 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova, s= ize_t size, int asid, struct arm_smmu_domain *smmu_domain); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size); +void __arm_smmu_tlb_inv_range(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *cmd, unsigned long iova, + size_t size, size_t granule, + struct iommu_domain *domain); =20 void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1ec5efca1d42..e9d4bbdacc99 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2267,12 +2267,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_atc_inv_domain(smmu_domain, 0, 0); } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) +void __arm_smmu_tlb_inv_range(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *cmd, unsigned long iova, + size_t size, size_t granule, + struct iommu_domain *domain) { - struct arm_smmu_device *smmu =3D smmu_domain->smmu; unsigned long end =3D iova + size, num_pages =3D 0, tg =3D 0; size_t inv_range =3D granule; struct arm_smmu_cmdq_batch cmds; @@ -2282,7 +2281,7 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_= cmdq_ent *cmd, =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { /* Get the leaf page size */ - tg =3D __ffs(smmu_domain->domain.pgsize_bitmap); + tg =3D __ffs(domain->pgsize_bitmap); =20 num_pages =3D size >> tg; =20 @@ -2356,7 +2355,8 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); + __arm_smmu_tlb_inv_range(smmu_domain->smmu, &cmd, iova, size, granule, + &smmu_domain->domain); =20 if (smmu_domain->nest_parent) { /* @@ -2387,7 +2387,8 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova, = size_t size, int asid, }, }; =20 - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); + __arm_smmu_tlb_inv_range(smmu_domain->smmu, &cmd, iova, size, granule, + &smmu_domain->domain); } =20 static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, --=20 2.43.0