From nobody Thu Apr 2 09:29:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D631742F54F; Thu, 5 Mar 2026 17:44:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732695; cv=none; b=O3b1adFkBX6qrQwOkXtFu1o6Q9e6tivFkUCjfwFSSXGQvvnjfttUfJPjRIbaw/yZDstvV6HS25Zc5gCUi5VofhJ18pvIfcPx7eR6JW8FkbUVBcAmA9Vt8tgVfugJKfufY7MYNe+mUTle8w77i2HKkfpVVR1Ugb9jDVtGg5A+eoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732695; c=relaxed/simple; bh=Xp9vVVC9VmSIjmyuA7qa6qei/ZbOzg/Sj/hvegc3Ao8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CokNIpctnGpIifoPslcUefiJk5kH6N7ejk+v38wS/IpuNOfxFIsDb5aJTfO0SwjOzYWKxfVo7JdOmqVUaZvdY8DXF4waJV8lcKQGITcWX0+MSwRQFoUUqCC4hS7hlvdG7+R9s0GqQnjlN/XlnowNG8E2OuFJGIj+9Xj3au8F7cQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=X6ynK1/E; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="X6ynK1/E" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772732692; x=1804268692; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xp9vVVC9VmSIjmyuA7qa6qei/ZbOzg/Sj/hvegc3Ao8=; b=X6ynK1/ENyq7Ol2PDeohMzJEcOzna/gNtxZ3mmZuyLRwt1sAHHJHIuAV tiIlD5iWQBCffv4uhL/JrQlTEqPUmyePdaLkFq1/xfzmztCTXUUKleuA6 sIBg9w7TRsWrXMKJHBQKzHZGfy16w08h9yhntsaqsDdXmA5Ldljvy4+XJ rpzpsuk2BfzhwUBwcc+y9CQu2FgxYRQE2vPpDbSDVf8POWdxfF5Ul9oMb u87e4NBqsi742RSMS5RWzHXlDn5J9UwzS61aRN+c+hrttXB1PAxp0ctWd HyiNdrldDrsS/2VTk2XPiDzSrkYwfZgPNDC20QTKaOL7m+tSSm8HCDdnt g==; X-CSE-ConnectionGUID: tj1mA6V6Qkymp91SQimaUw== X-CSE-MsgGUID: vZToPptaRgCJEkJRUFaQbw== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="85301956" X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="85301956" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:50 -0800 X-CSE-ConnectionGUID: 5cvMxudgT1aSgr3LDBmKnw== X-CSE-MsgGUID: REg7F8XTT2yTbKlTU/pxpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="222896527" Received: from mdroper-mobl2.amr.corp.intel.com (HELO localhost) ([10.124.220.244]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:48 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , Sean Christopherson , linux-kernel@vger.kernel.org Subject: [PATCH v2 27/36] KVM: selftests: Add test for nVMX MSR_IA32_VMX_PROCBASED_CTLS3 Date: Thu, 5 Mar 2026 09:44:07 -0800 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata Add test case for nVMX MSR_IA32_VMX_PROCBASED_CTLS3 emulation. Test if the access to MSR_IA32_VMX_PROCBASED_CTLS3 to succeed or fail, depending on whether the vCPU supports it or not. Signed-off-by: Isaku Yamahata --- .../testing/selftests/kvm/x86/vmx_msrs_test.c | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/tools/testing/selftests/kvm/x86/vmx_msrs_test.c b/tools/testin= g/selftests/kvm/x86/vmx_msrs_test.c index 90720b6205f4..3ec5b73b4f2f 100644 --- a/tools/testing/selftests/kvm/x86/vmx_msrs_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_msrs_test.c @@ -48,6 +48,11 @@ static void vmx_fixed0and1_msr_test(struct kvm_vcpu *vcp= u, uint32_t msr_index) =20 static void vmx_save_restore_msrs_test(struct kvm_vcpu *vcpu) { + union vmx_ctrl_msr ctls; + const struct kvm_msr_list *feature_list; + bool ctl3_found =3D false; + int i; + vcpu_set_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, 0); vcpu_set_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, -1ull); =20 @@ -65,6 +70,54 @@ static void vmx_save_restore_msrs_test(struct kvm_vcpu *= vcpu) vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_TRUE_EXIT_CTLS); vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS); vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_VMFUNC, -1ull); + + ctls.val =3D kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS); + TEST_ASSERT(!(ctls.set & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS), + "CPU_BASED_ACTIVATE_TERTIARY_CONTROLS should be cleared."); + + feature_list =3D kvm_get_feature_msr_index_list(); + for (i =3D 0; i < feature_list->nmsrs; i++) { + if (feature_list->indices[i] =3D=3D MSR_IA32_VMX_PROCBASED_CTLS3) { + ctl3_found =3D true; + break; + } + } + + if (ctls.clr & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) { + uint64_t kvm_ctls3, ctls3; + + TEST_ASSERT(ctl3_found, + "MSR_IA32_VMX_PROCBASED_CTLS3 was not in feature msr index list."); + + kvm_ctls3 =3D kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS3); + ctls3 =3D vcpu_get_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3); + TEST_ASSERT(kvm_ctls3 =3D=3D ctls3, + "msr values for kvm and vcpu must match."); + + vcpu_set_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, 0); + vcpu_set_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, ctls3); + vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, ctls3); + + /* + * The kvm host should be able to get/set + * MSR_IA32_VMX_PROCBASED_CTLS3 irrespective to the bit + * CPU_BASED_ACTIVATE_TERTIARY_CONTROLS of + * MSR_IA32_VMX_TRUE_PROCBASED_CTLS. + */ + ctls.val =3D vcpu_get_msr(vcpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS); + vcpu_set_msr(vcpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, + ctls.set & ~CPU_BASED_ACTIVATE_TERTIARY_CONTROLS); + vcpu_set_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, 0); + vcpu_set_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, ctls3); + vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, ctls3); + vcpu_set_msr(vcpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, ctls.val); + } else { + TEST_ASSERT(!ctl3_found, + "MSR_IA32_VMX_PROCBASED_CTLS3 was in feature msr index list."); + + TEST_ASSERT(!_vcpu_set_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS3, 0), + "setting MSR_IA32_VMX_PROCBASED_CTLS3 didn't fail."); + } } =20 static void __ia32_feature_control_msr_test(struct kvm_vcpu *vcpu, --=20 2.45.2