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Mon, 27 Oct 2025 11:54:36 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , Subject: [PATCH v4 4/7] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Date: Mon, 27 Oct 2025 11:54:18 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB55:EE_|MN0PR12MB5714:EE_ X-MS-Office365-Filtering-Correlation-Id: 3955622f-cefb-4ebf-2310-08de158a548a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/Z+w2wa/3oQCZAe3Cqjz804bSk0p444ZOtQ8iYS4jLeF8XeZxcWON73Jgvft?= =?us-ascii?Q?87Lo43w/L5NDoZBjWbDEwaFE8sFSJs+WRJXlWfs+QUIhfTRZioT6PAey7VQ6?= =?us-ascii?Q?qmMRFVJ4b/f570UqrJPz2euB5nzISS+nuazF5u7r8tkRwxu12KJnZAvduS0q?= =?us-ascii?Q?n68J6RTo6hzMPYfoOxlp/CimQHE173opBp/EhZ3WYowj07ujWzwone43nM7l?= =?us-ascii?Q?oA0MuTGgF3cX28TXttcUbfAd92rUs5g/5Q6o6V5n0PjQTS2vsGF+gLmLuCCF?= =?us-ascii?Q?udUhVF1cYarhMnFMLxOFKqSpB7AsvyzHS9dRkF6cxJI2ZmKXk9tWBF2RMzah?= =?us-ascii?Q?nbN0hEOMp9h9J42hOA6ORXWrebxRPb4fYjTaNoKRdXQFcG5dmoayC6ZXFKp9?= =?us-ascii?Q?I9N9EbE+u2TQjCJbZ5ybegiZENCWODcQEFO8tuhhONhnocuh2a8X/7u5s6fg?= =?us-ascii?Q?51d/Tbv6uPDu0p+gZEFMqjVxePOZ/d51BnBxNPqBuRE5duBMkxCdTMETJTuG?= =?us-ascii?Q?KiEvurkAq9FgnJl9GQVwx6h6mQZXbXcVlde0D62dFdm7iYqjvRguFg33COgK?= =?us-ascii?Q?cMuhI9xwbjNq1Dy7/GiDfWDtS+KJ7oBSr2WO/MyGLVy/b6WwngWtRsuVL/J1?= =?us-ascii?Q?Xo2Uy8Jfq/4FrRg3oWvuPw+dsmciqu+eI1HSgxj8qMeiWWWkHmhlk0DIirDk?= =?us-ascii?Q?5GEoX5kgJMy1vV5mN//E82QeqA07kRBfSD1STPAjusXYbSkTAThmnh3mBGDb?= =?us-ascii?Q?FNVo07TFpibIH3Mr5Xbj/uy3xp+FSqSgAJgfm6ocUoPkt7xxiitzoahwtMSd?= =?us-ascii?Q?/KSM9k30Kw+tEJ8tbF3cgNUG+W0zwO2HHrwQp+lfSWFyB7skQlQQGlFG9VrI?= =?us-ascii?Q?u9JGgRf5JIGfY6UgVFNjkODlU856Sxtfv0OCtNilXpXjZrb602eSONk1048n?= =?us-ascii?Q?iyyZiH3jbFly5V8l+nQYO4DBWvak+ts1MpOW43X9nOjkf8AUm3prVRSYXnlA?= =?us-ascii?Q?KIYvkTJ4qQFdSuraPWvk8pKOsMcEBkqYUyH8E8zA1W6zWJGeNzFKoJTIR8D7?= =?us-ascii?Q?qlI3eCMOJPQcEygE6Zu8Vlep9QWLtSr8P3/lyy6PqIBxzqZzkczfSmMUjeVS?= =?us-ascii?Q?9S0TwpVrVNYxkiIwH4T5XoodgV0tf6kBFZ4GvSl7tRS1o3GXkBNb9L2IKmhJ?= =?us-ascii?Q?OJztwFPYFz7MstZ17vboW1XVigFwal+MvubDuMEHYgWNok4G7NNzpsU6Bci5?= =?us-ascii?Q?E1zzhnDc98c6R/KStmL5Sc5IxcykPqYyNH0XjeMi0cdei/tX8YmXG+mePCRY?= =?us-ascii?Q?HNk7XUWNzCKS3leu9YZ0O6SjFLl/2bBaBweLdYrx807a02KsflvFik7SgnAS?= =?us-ascii?Q?mlL9gCGxVK/bHplBHP/2inqKJgyMzjNsxfQ8sSHKqyI/+6cKKtU7TJH/4b1v?= =?us-ascii?Q?QPFmPbJspS47G3OrQagJnmRxQ/zAVWMAn3UReyqAqEROKstnPUhahc7uzJ+E?= =?us-ascii?Q?+6CGIQqREMUCxA3YDCNFIs5oJe9IuQFVOvCuT92UxpadHb+U4UteLDZJ8G7e?= =?us-ascii?Q?Z3Z5JcBMlphj0qzYQPo=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2025 18:54:59.9399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3955622f-cefb-4ebf-2310-08de158a548a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB55.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5714 Content-Type: text/plain; charset="utf-8" When a master is attached from an old domain to a new domain, it needs to build an invalidation array to delete and add the array entries from/onto the invalidation arrays of those two domains, passed via the to_merge and to_unref arguments into arm_smmu_invs_merge/unref() respectively. Since the master->num_streams might differ across masters, a memory would have to be allocated when building an to_merge/to_unref array which might fail with -ENOMEM. On the other hand, an attachment to arm_smmu_blocked_domain must not fail so it's the best to avoid any memory allocation in that path. Pre-allocate a fixed size invalidation array for every master. This array will be used as a scratch to fill dynamically when building a to_merge or to_unref invs array. Sort fwspec->ids in an ascending order to fit to the arm_smmu_invs_merge() function. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 +++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 43df0ae89d96f..b8a4bda12b571 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -922,6 +922,14 @@ struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; struct arm_smmu_stream *streams; + /* + * Scratch memory for a to_merge or to_unref array to build a per-domain + * invalidation array. It'll be pre-allocated with enough enries for all + * possible build scenarios. It can be used by only one caller at a time + * until the arm_smmu_invs_merge/unref() finishes. Must be locked by the + * iommu_group mutex. + */ + struct arm_smmu_invs *build_invs; struct arm_smmu_vmaster *vmaster; /* use smmu->streams_mutex */ /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index cc266b47810b0..f01c2a6b40cd5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3686,12 +3686,22 @@ static int arm_smmu_init_sid_strtab(struct arm_smmu= _device *smmu, u32 sid) return 0; } =20 +static int arm_smmu_ids_cmp(const void *_l, const void *_r) +{ + const typeof_member(struct iommu_fwspec, ids[0]) *l =3D _l; + const typeof_member(struct iommu_fwspec, ids[0]) *r =3D _r; + + return cmp_int(*l, *r); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { int i; int ret =3D 0; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + bool ats_supported =3D dev_is_pci(master->dev) && + pci_ats_supported(to_pci_dev(master->dev)); =20 master->streams =3D kcalloc(fwspec->num_ids, sizeof(*master->streams), GFP_KERNEL); @@ -3699,6 +3709,21 @@ static int arm_smmu_insert_master(struct arm_smmu_de= vice *smmu, return -ENOMEM; master->num_streams =3D fwspec->num_ids; =20 + if (!ats_supported) { + /* Base case has 1 ASID entry or maximum 2 VMID entries */ + master->build_invs =3D arm_smmu_invs_alloc(2); + } else { + /* Put the ids into order for sorted to_merge/to_unref arrays */ + sort_nonatomic(fwspec->ids, fwspec->num_ids, + sizeof(fwspec->ids[0]), arm_smmu_ids_cmp, NULL); + /* ATS case adds num_ids of entries, on top of the base case */ + master->build_invs =3D arm_smmu_invs_alloc(2 + fwspec->num_ids); + } + if (IS_ERR(master->build_invs)) { + kfree(master->streams); + return PTR_ERR(master->build_invs); + } + mutex_lock(&smmu->streams_mutex); for (i =3D 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream =3D &master->streams[i]; @@ -3736,6 +3761,7 @@ static int arm_smmu_insert_master(struct arm_smmu_dev= ice *smmu, for (i--; i >=3D 0; i--) rb_erase(&master->streams[i].node, &smmu->streams); kfree(master->streams); + kfree(master->build_invs); } mutex_unlock(&smmu->streams_mutex); =20 @@ -3757,6 +3783,7 @@ static void arm_smmu_remove_master(struct arm_smmu_ma= ster *master) mutex_unlock(&smmu->streams_mutex); =20 kfree(master->streams); + kfree(master->build_invs); } =20 static struct iommu_device *arm_smmu_probe_device(struct device *dev) --=20 2.43.0