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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2025 20:20:57.5951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b09f06d0-ff67-4f89-d6b4-08dd3b2247d7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A345.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8695 Content-Type: text/plain; charset="utf-8" resctrl_late_init() has the __init attribute, but some of the functions called from it do not have the __init attribute. Add the __init attribute to all the functions in the call sequences to maintain consistency throughout. Fixes: 6a445edce657 ("x86/intel_rdt/cqm: Add RDT monitoring initialization") Fixes: def10853930a ("x86/intel_rdt: Add two new resources for L2 Code and = Data Prioritization (CDP)") Fixes: bd334c86b5d7 ("x86/resctrl: Add __init attribute to rdt_get_mon_l3_c= onfig()") Suggested-by: Reinette Chatre Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v11: No changes. v10: Text changes. Added __init attribute to cache_alloc_hsw_probe() Followed function prototype rules (preferred order is storage class before return type). v9: Moved the patch to the begining of the series. Fixed all the call sequences. Added additional Fixed tags. v8: New patch. --- arch/x86/kernel/cpu/resctrl/core.c | 10 +++++----- arch/x86/kernel/cpu/resctrl/internal.h | 2 +- arch/x86/kernel/cpu/resctrl/monitor.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 3d1735ed8d1f..f0a331287979 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -145,7 +145,7 @@ u32 resctrl_arch_system_num_rmid_idx(void) * is always 20 on hsw server parts. The minimum cache bitmask length * allowed for HSW server is always 2 bits. Hardcode all of them. */ -static inline void cache_alloc_hsw_probe(void) +static inline __init void cache_alloc_hsw_probe(void) { struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_L3]; struct rdt_resource *r =3D &hw_res->r_resctrl; @@ -277,7 +277,7 @@ static __init bool __rdt_get_mem_config_amd(struct rdt_= resource *r) return true; } =20 -static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) +static __init void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); union cpuid_0x10_1_eax eax; @@ -296,7 +296,7 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt= _resource *r) r->alloc_capable =3D true; } =20 -static void rdt_get_cdp_config(int level) +static __init void rdt_get_cdp_config(int level) { /* * By default, CDP is disabled. CDP can be enabled by mount parameter @@ -306,12 +306,12 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 -static void rdt_get_cdp_l3_config(void) +static __init void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); } =20 -static void rdt_get_cdp_l2_config(void) +static __init void rdt_get_cdp_l2_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L2); } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 20c898f09b7e..05358e78147b 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -634,7 +634,7 @@ int closids_supported(void); void closid_free(int closid); int alloc_rmid(u32 closid); void free_rmid(u32 closid, u32 rmid); -int rdt_get_mon_l3_config(struct rdt_resource *r); +int __init rdt_get_mon_l3_config(struct rdt_resource *r); void __exit rdt_put_mon_l3_config(void); bool __init rdt_cpu_has(int flag); void mon_event_count(void *info); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 94a1d9780461..1c7b574bf0cd 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -979,7 +979,7 @@ void mbm_setup_overflow_handler(struct rdt_mon_domain *= dom, unsigned long delay_ schedule_delayed_work_on(cpu, &dom->mbm_over, delay); } =20 -static int dom_data_init(struct rdt_resource *r) +static __init int dom_data_init(struct rdt_resource *r) { u32 idx_limit =3D resctrl_arch_system_num_rmid_idx(); u32 num_closid =3D resctrl_arch_get_num_closid(r); @@ -1077,7 +1077,7 @@ static struct mon_evt mbm_local_event =3D { * because as per the SDM the total and local memory bandwidth * are enumerated as part of L3 monitoring. */ -static void l3_mon_evt_init(struct rdt_resource *r) +static __init void l3_mon_evt_init(struct rdt_resource *r) { INIT_LIST_HEAD(&r->evt_list); =20 --=20 2.34.1