From nobody Thu Apr 2 16:58:16 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 585A138B7C4 for ; Tue, 10 Feb 2026 22:13:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770761622; cv=none; b=cDvHg+BuIcf+FWLAkGK0GPTLvZxiTfEEFAH0T2YWZVfdhmjzZktPfLg7KmaNZUDJtO/VbQv76Bh/MLquEejuXyBkbYfJUFFv0f5W0m+T104RKGoqutv79Z1BDLbYauMu1rdUVAfhj+GlQu7B52//43nFYYwOLRH+LjEdU0KxT7g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770761622; c=relaxed/simple; bh=iOg2XKjD/jnBvASIUIGijnOmsOwKYW6UQ4+RkvVcrLc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Dwdug2wMf0e34CMpE9hTtoPWlbXSGVrU+IFmanq0NDanXDGz4qcsFqYZ1awhtnIsUEfMVjXebTooZRMNr1p8JJaAdOog1mStyxsdnwh7BdeC6KIMyvcL5lG7R+koO3idz6LHqXzaNVxARpfWVKVVLd/PhR1AaYR2l40tdyPYG8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=g/oadkep; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="g/oadkep" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770761621; x=1802297621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iOg2XKjD/jnBvASIUIGijnOmsOwKYW6UQ4+RkvVcrLc=; b=g/oadkepIDV1cj/vwsOCpJaDWD6N4cNrzT1x3WAQBwKKjuVY97pYhNaV Gg2jH+HF/YypLAoUySudtZ//Uu4nQQxuLT0tKMRcTd0GwokeM5IIQARBb vHyvkxN7Ohlh4kVFE5MSsKj9lcn3WRtOFCedNIvkgaQd4LKGZTv+D9rFV mkmND2eyNHi5hSDw4LnW4hpknq3MtPp6uyjOHFhyH+Cw9dk8UtNEqGcTD B2jHhpIOvb1bgU76BgOxqBGhgFtqhI58phO4mzNpNGnsZsvkQsk40yL8K TJkaBnYr7wpL3WLTaCJ+96RnApDykCNb1JOYdz2MjQzAiGxq2zmQ19vYX g==; X-CSE-ConnectionGUID: ZMpavvj9SFy+C5k/C84akg== X-CSE-MsgGUID: qIv96OsqQHOV88Ts3/LNdA== X-IronPort-AV: E=McAfee;i="6800,10657,11697"; a="82631568" X-IronPort-AV: E=Sophos;i="6.21,283,1763452800"; d="scan'208";a="82631568" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2026 14:13:41 -0800 X-CSE-ConnectionGUID: s9V8yD4vSWeAVjBFClw4tw== X-CSE-MsgGUID: t9oJi9eZRIerGF4FI4dhug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,283,1763452800"; d="scan'208";a="216374023" Received: from b04f130c83f2.jf.intel.com ([10.165.154.98]) by fmviesa004.fm.intel.com with ESMTP; 10 Feb 2026 14:13:40 -0800 From: Tim Chen To: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot Cc: Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Tim Chen , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Subject: [PATCH v3 17/21] sched/cache: Enable cache aware scheduling for multi LLCs NUMA node Date: Tue, 10 Feb 2026 14:18:57 -0800 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Yu Introduce sched_cache_present to enable cache aware scheduling for multi LLCs NUMA node Cache-aware load balancing should only be enabled if there are more than 1 LLCs within 1 NUMA node. sched_cache_present is introduced to indicate whether this platform supports this topology. Suggested-by: Libo Chen Suggested-by: Adam Li Co-developed-by: Tim Chen Signed-off-by: Tim Chen Signed-off-by: Chen Yu --- Notes: v2->v3: No change. kernel/sched/sched.h | 3 ++- kernel/sched/topology.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index c18e59f320a6..59ac04625842 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -3916,11 +3916,12 @@ static inline void mm_cid_switch_to(struct task_str= uct *prev, struct task_struct #endif /* !CONFIG_SCHED_MM_CID */ =20 #ifdef CONFIG_SCHED_CACHE +DECLARE_STATIC_KEY_FALSE(sched_cache_present); extern int max_llcs; =20 static inline bool sched_cache_enabled(void) { - return false; + return static_branch_unlikely(&sched_cache_present); } #endif extern void init_sched_mm(struct task_struct *p); diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index dae78b5915a7..9104fed25351 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -801,6 +801,7 @@ enum s_alloc { }; =20 #ifdef CONFIG_SCHED_CACHE +DEFINE_STATIC_KEY_FALSE(sched_cache_present); static bool alloc_sd_pref(const struct cpumask *cpu_map, struct s_data *d) { @@ -2604,6 +2605,7 @@ static int build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_att= r *attr) { enum s_alloc alloc_state =3D sa_none; + bool has_multi_llcs =3D false; struct sched_domain *sd; struct s_data d; struct rq *rq =3D NULL; @@ -2731,10 +2733,12 @@ build_sched_domains(const struct cpumask *cpu_map, = struct sched_domain_attr *att * between LLCs and memory channels. */ nr_llcs =3D sd->span_weight / child->span_weight; - if (nr_llcs =3D=3D 1) + if (nr_llcs =3D=3D 1) { imb =3D sd->span_weight >> 3; - else + } else { imb =3D nr_llcs; + has_multi_llcs =3D true; + } imb =3D max(1U, imb); sd->imb_numa_nr =3D imb; =20 @@ -2796,6 +2800,16 @@ build_sched_domains(const struct cpumask *cpu_map, s= truct sched_domain_attr *att =20 ret =3D 0; error: +#ifdef CONFIG_SCHED_CACHE + /* + * TBD: check before writing to it. sched domain rebuild + * is not in the critical path, leave as-is for now. + */ + if (!ret && has_multi_llcs) + static_branch_enable_cpuslocked(&sched_cache_present); + else + static_branch_disable_cpuslocked(&sched_cache_present); +#endif __free_domain_allocs(&d, alloc_state, cpu_map); =20 return ret; --=20 2.32.0