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Thu, 15 Aug 2024 17:55:39 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v12 02/10] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Date: Thu, 15 Aug 2024 17:55:23 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F3:EE_|DM4PR12MB6423:EE_ X-MS-Office365-Filtering-Correlation-Id: d11da687-0a65-457f-3cfb-08dcbd8e3151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Mh/8+Mf9/svXoiuGQ5CMTdhMfq5+Y+ivMJ7w7FBPguKmEWC0MdQNuKNSn32O?= =?us-ascii?Q?p4ZBs6rdrOGQCvYhzWTlYx980NBfvAmOn4rv4EEQPbtuoyUWCQsm5XAqkFQT?= =?us-ascii?Q?iuDKyG6JVAFRoYSdlHsauddQUbZmIfX+i7G+7ojRfqwtp1aspRuzGxqx9LKp?= =?us-ascii?Q?Y48vhgGXBolkptvJ+QBZr5dW9vPCv8N6OWjHI2y7gy4kn5SOdCbD4O0mmxHW?= =?us-ascii?Q?KdyOfPu2G8cyYF3dMBan3bAfSTEJrKqfQX1UndJZgyR+TraVelpd689f6e8J?= =?us-ascii?Q?zUpdnKahFyNRuF549z3cYfqWEvbO3+Nd6dr0ymRaP8NN4mJabf5rs5GClQ6Z?= =?us-ascii?Q?omDY+25t3OAEED7LLt+gzJrg2B4sRURVlIGVPAZIviIiL1SDfiDSBtW+xPpf?= =?us-ascii?Q?8cyNB3X3abzlRthWMTRxu9EwZdc59UDfFz/4ctKZVg6lu6jbOxDgvze81B3Z?= =?us-ascii?Q?M8H5jY2aI7wCvjb12M3ZUXX7MeaJ5psq66zmyrCv3fymJYLEbuhdwuqLlWqt?= =?us-ascii?Q?UiV+0SK0fkjgCW8WYG3/TKus3wkD39fCAurZQWSrGn0MI7DEKWcThC85J9Ec?= =?us-ascii?Q?gic2gV/EcQdIOcHAC/TMDLvV/TiJOWUacG7NWkYH8W3PtlUQcbd4A+wwd4Ug?= =?us-ascii?Q?khwzFvtrAItt8ZOJ7cQOfMsRksQPimCEZ/xVDKjZxQuhwjmpVCnRcP54R6sC?= =?us-ascii?Q?II7JXz5fRRpRgmThGgkWnaVKtYRkwoJvb5XGIcwlSeFSMuPDY/8Gflli1z48?= =?us-ascii?Q?PeV2ip3S5ri1NaQPGr5GVEy22NKoaAWLkNx7t1ZDmemJ1EKsg7Rm0BmqxaHi?= =?us-ascii?Q?PdLKnoJsLWcJ6oaBev8qcHHfTPCEndrKk60JbYggdKPlofowOwPqeFRSSDa0?= =?us-ascii?Q?swrgyiAopriuGBv1R81I2a7L4uGdi78eF3JQrLj/cQU/snoYOntzd47pN4Uk?= =?us-ascii?Q?6kQmHyRx4kpX1+aqr07IxjwXcxjhh7shW9SnEik2UFdaG70+/IALgi67pUu2?= =?us-ascii?Q?meHDa2GwxLHGrcdpma+zhk3UJZDXeqfq9FKE7bwEvAZdLzmZV9kqu7iTbRas?= =?us-ascii?Q?gSZwVWc/aATB8OzIXSPdzncxK7/r62w+kkZoWWMBOe8hlJhPg/wSoFpqRWCh?= =?us-ascii?Q?dJCzLSPK27JpHG9x/R8GcdfFplEh1BMu4xQnZoiom2QQUZC5cxdart7NYgxx?= =?us-ascii?Q?R52azaNJrqTO54Kd4z/31bIF6tNt+gFdJK5XZ4QGUHTDsiKT5+LybhQw+y7v?= =?us-ascii?Q?NExuj8WGPZnnn8xFwdmBro65qxOhuMwAgWT4jXkElPu/TRqgVaRS9Ieixn3i?= =?us-ascii?Q?gi+8z+3Hp+18aeV0aqYXb9Xrg857lkbhcAhvIB+rZUJi+Tbm/aR5e3W8nX2o?= =?us-ascii?Q?cqovZJoNk58Q1Hjfg2cJ7nzi2vocQeVZBpYKkyPdwtJ17hbDr9DQXmhBgMfb?= =?us-ascii?Q?HzjqvixrsC+aJ3m9ysjWBz/Z7KPJqt+2?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 00:55:58.8618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d11da687-0a65-457f-3cfb-08dcbd8e3151 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6423 Content-Type: text/plain; charset="utf-8" There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should call it at all places other than going through arm_smmu_cmdq_build_cmd() separately. This helps the following patch that adds a CS_NONE option. Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, in ARM_SMMU_OPT_MSIPOLL=3Dtrue case, from previously a non-MSI one to now an MSI one that is proven to still work using a hacking test: nvme: Adding to iommu group 10 nvme: --------hacking----------- arm-smmu-v3: unexpected global error reported (0x00000001), this could be serious arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command arm-smmu-v3: skipping command in error state: arm-smmu-v3: 0x0000000000000000 arm-smmu-v3: 0x0000000000000000 nvme: -------recovered---------- nvme nvme0: 72/0/0 default/read/poll queues nvme0n1: p1 p2 Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index f409ead589ff..f481d7be3d4e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -329,16 +329,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct ar= m_smmu_cmdq_ent *ent) cmd[0] |=3D FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); cmd[1] |=3D FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; - case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); - cmd[1] |=3D ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; - } else { - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); - } - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); - break; default: return -ENOENT; } @@ -354,20 +344,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct= arm_smmu_device *smmu) static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device = *smmu, struct arm_smmu_queue *q, u32 prod) { - struct arm_smmu_cmdq_ent ent =3D { - .opcode =3D CMDQ_OP_CMD_SYNC, - }; + cmd[1] =3D 0; + cmd[0] =3D FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { + cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + return; + } =20 /* * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI * payload, so the write will zero the entire command on that platform. */ - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { - ent.sync.msiaddr =3D q->base_dma + Q_IDX(&q->llq, prod) * - q->ent_dwords * 8; - } - - arm_smmu_cmdq_build_cmd(cmd, &ent); + cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); + cmd[1] |=3D (q->base_dma + Q_IDX(&q->llq, prod) * q->ent_dwords * 8) & + CMDQ_SYNC_1_MSIADDR_MASK; } =20 static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -384,9 +377,6 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_de= vice *smmu, u64 cmd[CMDQ_ENT_DWORDS]; u32 cons =3D readl_relaxed(q->cons_reg); u32 idx =3D FIELD_GET(CMDQ_CONS_ERR, cons); - struct arm_smmu_cmdq_ent cmd_sync =3D { - .opcode =3D CMDQ_OP_CMD_SYNC, - }; =20 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); @@ -420,7 +410,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_de= vice *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); =20 /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); =20 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c1454e9758c4..6c5739f6b90f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -518,9 +518,6 @@ struct arm_smmu_cmdq_ent { } resume; =20 #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u64 msiaddr; - } sync; }; }; =20 --=20 2.43.0