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charset="utf-8" On echo and host clock modes, AD4030 and similar devices can do two data bit transitions per clock cycle per active lane. Document how to specify dual data rate (DDR) feature for AD4030 series devices in device tree. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Marcelo Schmitt --- .../bindings/iio/adc/adi,ad4030.yaml | 27 +++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 1e4e025b835f..9adb60629631 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -90,6 +90,13 @@ properties: host - Host. The Host clock mode uses an internal oscillator to cloc= k out the data bits. In this mode, the spi controller is not drivin= g SCLK. =20 + adi,dual-data-rate: + description: + Enable dual data rate (DDR) in which two bits (per active lane) are + transmitted in one clock cycle. This can reduce the serial clock to + 10 MHz while operating at a sample rate of 2 MSPS. + type: boolean + required: - compatible - reg @@ -98,11 +105,21 @@ required: - vio-supply - cnv-gpios =20 -oneOf: - - required: - - ref-supply - - required: - - refin-supply +allOf: + - oneOf: + - required: + - ref-supply + - required: + - refin-supply + # DDR is available only for echo clock mode and host clock mode. + - if: + properties: + adi,clock-mode: + contains: + const: spi + then: + properties: + adi,dual-data-rate: false =20 unevaluatedProperties: false =20 --=20 2.39.2