From nobody Sun Sep 7 12:22:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 720F4CDB465 for ; Mon, 16 Oct 2023 16:39:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234411AbjJPQji (ORCPT ); Mon, 16 Oct 2023 12:39:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234594AbjJPQhv (ORCPT ); Mon, 16 Oct 2023 12:37:51 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBBA972B1; Mon, 16 Oct 2023 09:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697473372; x=1729009372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=75w4Y6RO2208HNHofqgFhmzuuMt1I2A8+tizXHUCKk0=; b=J/qkGV2DZD4GoMJB8PToRJufbwwRUiuFAyPuOIcDWG4xzoTklXWpFXTU yC2IRVL2NdpjHFDcY1BqCHi6eh3o8nfXghZJ1/kJVvFF5CTwghPiXKv3Z P8HSow7Bb5opLFs4uFJiM7qYQQ+Hq2+de7YFcHNE8iaTFN38Jmnb/GX/4 WYhboRW3bFzEbwlM9cIEK3su4uDQVdm7Xe3BSjsbO1m4RIn6TH6wDSa7p yagUTpO4vG1DSbfsz4NPBQP69Eq5H0OKGW3x+qlyg/O+br7hVXfNIrcvT UziJ+1UiKrA/JvhLrZPxv5H6BrJh2PNBcpxI9gbPXxnJPUzjYAop7zaJ+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="364922174" X-IronPort-AV: E=Sophos;i="6.03,229,1694761200"; d="scan'208";a="364922174" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 09:16:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1003006496" X-IronPort-AV: E=Sophos;i="6.03,229,1694761200"; d="scan'208";a="1003006496" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 09:16:13 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Kai Huang , Zhi Wang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v16 114/116] RFC: KVM: x86: Add x86 callback to check cpuid Date: Mon, 16 Oct 2023 09:15:06 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata The x86 backend should check the consistency of KVM_SET_CPUID2 because it has its constraint. Add a callback for it. The backend code will come as another patch. Suggested-by: Sean Christopherson Link: https://lore.kernel.org/lkml/ZDiGpCkXOcCm074O@google.com/ Signed-off-by: Isaku Yamahata --- arch/x86/include/asm/kvm-x86-ops.h | 2 ++ arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c | 20 ++++++++++++-------- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-= x86-ops.h index 8b3c5f2179cf..ba74cb7199b3 100644 --- a/arch/x86/include/asm/kvm-x86-ops.h +++ b/arch/x86/include/asm/kvm-x86-ops.h @@ -20,6 +20,8 @@ KVM_X86_OP(hardware_disable) KVM_X86_OP(hardware_unsetup) KVM_X86_OP_OPTIONAL_RET0(offline_cpu) KVM_X86_OP(has_emulated_msr) +/* TODO: Once all backend implemented this op, remove _OPTIONAL_RET0. */ +KVM_X86_OP_OPTIONAL_RET0(vcpu_check_cpuid) KVM_X86_OP(vcpu_after_set_cpuid) KVM_X86_OP(is_vm_type_supported) KVM_X86_OP_OPTIONAL(max_vcpus); diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index f0674ef1c17e..8ac6f0555ac3 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1619,6 +1619,7 @@ struct kvm_x86_ops { void (*hardware_unsetup)(void); int (*offline_cpu)(void); bool (*has_emulated_msr)(struct kvm *kvm, u32 index); + int (*vcpu_check_cpuid)(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e= 2, int nent); void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu); =20 bool (*is_vm_type_supported)(unsigned long vm_type); diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index da46f284ec65..7ce2fdba8fff 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -136,6 +136,7 @@ static int kvm_check_cpuid(struct kvm_vcpu *vcpu, { struct kvm_cpuid_entry2 *best; u64 xfeatures; + int r; =20 /* * The existing code assumes virtual address is 48-bit or 57-bit in the @@ -155,15 +156,18 @@ static int kvm_check_cpuid(struct kvm_vcpu *vcpu, * enabling in the FPU, e.g. to expand the guest XSAVE state size. */ best =3D cpuid_entry2_find(entries, nent, 0xd, 0); - if (!best) - return 0; - - xfeatures =3D best->eax | ((u64)best->edx << 32); - xfeatures &=3D XFEATURE_MASK_USER_DYNAMIC; - if (!xfeatures) - return 0; + if (best) { + xfeatures =3D best->eax | ((u64)best->edx << 32); + xfeatures &=3D XFEATURE_MASK_USER_DYNAMIC; + if (xfeatures) { + r =3D fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, + xfeatures); + if (r) + return r; + } + } =20 - return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); + return static_call(kvm_x86_vcpu_check_cpuid)(vcpu, entries, nent); } =20 /* Check whether the supplied CPUID data is equal to what is already set f= or the vCPU. */ --=20 2.25.1