From nobody Sun Dec 14 19:00:56 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A2921527BE for ; Fri, 10 May 2024 06:28:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715322536; cv=none; b=mpbvr3ugWO4qgwQWfuTVlMcfQWfxRKrnrv5Sf4XBaG/91oxuQSRnncutTYN8bHjC35n7uvsdLgE8SnMmbCaGXgVg8z0apJU0IXa3NmH1QP8HoCB/bXZVVGN+8FTL9mQQW6SmQigEptARAV94eHG/SkTCixV90Yy4313Xwk7H4Zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715322536; c=relaxed/simple; bh=Oj78+m6G1YczrGzCR+l3AduE2j6RkVKd1tsAt/vLqbI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OIT84YOdn5huY2fGmNOs6KacB2iZKuteGLR4OIkCm5m8EkEAqm/7aqXR4t7ecqePEZsKrn0Qu2inSwE5DL3hONtBNrJyRL0hFyTPhwnyU2HDuahsf3yclxRrFK3b0vc3Ivubg3sAzYgcCH0P7bpT8abuq0BKNz2EYmlo3kpY7s4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KlKiMcip; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2loGTuDo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KlKiMcip"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2loGTuDo" From: Nam Cao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1715322531; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pEdNR+tmiFh46glcNjBAzC77FOgymIT0T+/PVLfSL7s=; b=KlKiMcipyRc94KL8iUYbRAzqDlI4zs8Xq0+0noofqJFZ6+Z03rsQ/tF4lJiwSmnNfts+sU 8VgiEbilBeb7VrQ1a4GLCg4nvx71oFzY60FJ8tiGoXdIc93bIDWulindNSZnSJfMQ+tkCh NQz+rdc35AIjljgR/yO2l6Uw9QVhAQtXnGKob3ZV28kguARX9tRT5SZL2dL1Qjk9Ub7Cde S1Enlqs49Y3EIlnKR+RdNQMFOvnxm6jsNl+Iq0ixzJR6X6bAOLH1khk5XuANTCRhWf9jJm ZPvasPVrCo//Ei8sYPI684zb2CwJPnUb/w+mqTkhMpuRZQT6Knf+kVjHztz/Ug== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1715322531; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pEdNR+tmiFh46glcNjBAzC77FOgymIT0T+/PVLfSL7s=; b=2loGTuDozASFvZvntEdkPWBdOcoOTNEpZ1di8OoSUp64VqGnYUJCfO7Qaj0Z0rr2ckLMSB JV/o/a3JJ/+/jPBQ== To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Nam Cao Subject: [PATCH 3/7] riscv: drop the use of XIP_OFFSET in XIP_FIXUP_OFFSET Date: Fri, 10 May 2024 08:28:41 +0200 Message-Id: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" XIP_OFFSET is the hard-coded offset of writable data section within the kernel. By hard-coding this value, the read-only section of the kernel (which is placed before the writable data section) is restricted in size. As a preparation to remove this hard-coded macro XIP_OFFSET entirely, stop using XIP_OFFSET in XIP_FIXUP_OFFSET. Instead, use CONFIG_PHYS_RAM_BASE and _sdata to do the same thing. While at it, also add a description for XIP_FIXUP_OFFSET. Signed-off-by: Nam Cao Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/xip_fixup.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/xip_fixup.h b/arch/riscv/include/asm/xi= p_fixup.h index b65bf6306f69..9ed2cfae09e0 100644 --- a/arch/riscv/include/asm/xip_fixup.h +++ b/arch/riscv/include/asm/xip_fixup.h @@ -9,8 +9,19 @@ =20 #ifdef CONFIG_XIP_KERNEL .macro XIP_FIXUP_OFFSET reg - REG_L t0, _xip_fixup + /* Fix-up address in Flash into address in RAM early during boot before + * MMU is up. Because generated code "thinks" data is in Flash, but it + * is actually in RAM (actually data is also in Flash, but Flash is + * read-only, thus we need to use the data residing in RAM). + * + * The start of data in Flash is _sdata and the start of data in RAM is + * CONFIG_PHYS_RAM_BASE. So this fix-up essentially does this: + * reg +=3D CONFIG_PHYS_RAM_BASE - _start + */ + li t0, CONFIG_PHYS_RAM_BASE add \reg, \reg, t0 + la t0, _sdata + sub \reg, \reg, t0 .endm .macro XIP_FIXUP_FLASH_OFFSET reg la t0, __data_loc @@ -19,7 +30,6 @@ add \reg, \reg, t0 .endm =20 -_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET _xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET #else .macro XIP_FIXUP_OFFSET reg --=20 2.39.2