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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2025 06:50:55.2609 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e133491d-c662-4316-cfb3-08dd82333231 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF84D37DD5C Content-Type: text/plain; charset="utf-8" The EFR[HATS] bits indicate maximum host translation level supported by IOMMU. Adding support to set the maximum host page table level as indicated by EFR[HATS]. If the HATS=3D11b (reserved), the driver will attempt to use guest page table for DMA API. Reviewed-by: Suravee Suthikulpanit Signed-off-by: Ankit Soni Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/init.c | 16 ++++++++++++++++ drivers/iommu/amd/io_pgtable.c | 4 ++-- drivers/iommu/amd/iommu.c | 2 +- 5 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index bb14c4800dd0..0286120ad4a5 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -42,6 +42,7 @@ int amd_iommu_enable_faulting(unsigned int cpu); extern int amd_iommu_guest_ir; extern enum protection_domain_mode amd_iommu_pgtable; extern int amd_iommu_gpt_level; +extern u8 amd_iommu_hpt_level; extern unsigned long amd_iommu_pgsize_bitmap; extern bool amd_iommu_hatdis; =20 diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 284ff4309660..6bf81197c2c8 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -96,6 +96,7 @@ #define FEATURE_GA BIT_ULL(7) #define FEATURE_HE BIT_ULL(8) #define FEATURE_PC BIT_ULL(9) +#define FEATURE_HATS GENMASK_ULL(11, 10) #define FEATURE_GATS GENMASK_ULL(13, 12) #define FEATURE_GLX GENMASK_ULL(15, 14) #define FEATURE_GAM_VAPIC BIT_ULL(21) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index f71b236c2af2..c713756fa44e 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -152,6 +152,8 @@ bool amd_iommu_dump; bool amd_iommu_irq_remap __read_mostly; =20 enum protection_domain_mode amd_iommu_pgtable =3D PD_MODE_NONE; +/* Host page table level */ +u8 amd_iommu_hpt_level; /* Guest page table level */ int amd_iommu_gpt_level =3D PAGE_MODE_4_LEVEL; =20 @@ -3052,6 +3054,7 @@ static int __init early_amd_iommu_init(void) struct acpi_table_header *ivrs_base; int ret; acpi_status status; + u8 efr_hats; =20 if (!amd_iommu_detected) return -ENODEV; @@ -3096,6 +3099,19 @@ static int __init early_amd_iommu_init(void) FIELD_GET(FEATURE_GATS, amd_iommu_efr) =3D=3D GUEST_PGTABLE_5_LEVEL) amd_iommu_gpt_level =3D PAGE_MODE_5_LEVEL; =20 + efr_hats =3D FIELD_GET(FEATURE_HATS, amd_iommu_efr); + if (efr_hats !=3D 0x3) { + /* + * efr[HATS] bits specify the maximum host translation level + * supported, with LEVEL 4 being initial max level. + */ + amd_iommu_hpt_level =3D efr_hats + PAGE_MODE_4_LEVEL; + } else { + pr_warn_once("Disable host address translation due to invalid max level = (%#x).\n", + efr_hats); + amd_iommu_hatdis =3D true; + } + if (amd_iommu_pgtable =3D=3D PD_MODE_V2) { if (!amd_iommu_v2_pgtbl_supported()) { pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index 26cf562dde11..0d8bc06f63d7 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -132,7 +132,7 @@ static bool increase_address_space(struct amd_io_pgtabl= e *pgtable, goto out; =20 ret =3D false; - if (WARN_ON_ONCE(pgtable->mode =3D=3D PAGE_MODE_6_LEVEL)) + if (WARN_ON_ONCE(pgtable->mode =3D=3D amd_iommu_hpt_level)) goto out; =20 *pte =3D PM_LEVEL_PDE(pgtable->mode, iommu_virt_to_phys(pgtable->root)); @@ -531,7 +531,7 @@ static void v1_free_pgtable(struct io_pgtable *iop) =20 /* Page-table is not visible to IOMMU anymore, so free it */ BUG_ON(pgtable->mode < PAGE_MODE_NONE || - pgtable->mode > PAGE_MODE_6_LEVEL); + pgtable->mode > amd_iommu_hpt_level); =20 free_sub_pt(pgtable->root, pgtable->mode, &freelist); iommu_put_pages_list(&freelist); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0ebc264726da..a2f957ee9110 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2503,7 +2503,7 @@ static int pdom_setup_pgtable(struct protection_domai= n *domain, static inline u64 dma_max_address(enum protection_domain_mode pgtable) { if (pgtable =3D=3D PD_MODE_V1) - return ~0ULL; + return PM_LEVEL_SIZE(amd_iommu_hpt_level); =20 /* V2 with 4/5 level page table */ return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1); --=20 2.43.0