From nobody Thu Nov 14 07:15:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 477E0C6379F for ; Fri, 10 Feb 2023 23:38:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbjBJXiK (ORCPT ); Fri, 10 Feb 2023 18:38:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229830AbjBJXh7 (ORCPT ); Fri, 10 Feb 2023 18:37:59 -0500 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FE0771662; Fri, 10 Feb 2023 15:37:39 -0800 (PST) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1pQcxR-00049I-1C; Sat, 11 Feb 2023 00:37:33 +0100 Date: Fri, 10 Feb 2023 23:35:56 +0000 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Russell King , Heiner Kallweit , Lorenzo Bianconi , Mark Lee , John Crispin , Felix Fietkau , AngeloGioacchino Del Regno , Matthias Brugger , DENG Qingfang , Landen Chao , Sean Wang , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Vladimir Oltean , Florian Fainelli , Andrew Lunn Cc: Jianhui Zhao , =?iso-8859-1?Q?Bj=F8rn?= Mork Subject: [PATCH v4 01/12] net: ethernet: mtk_eth_soc: add support for MT7981 SoC Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MediaTek MT7981 SoC comes with two 1G/2.5G SGMII ports, just like MT7986. In addition MT7981 is equipped with a built-in 1000Base-T PHY which can be used with GMAC1. As many MT7981 boards make use of inverting SGMII signal polarity, add new device-tree attribute 'mediatek,pn_swap' to support them. Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +++++++-- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 31 ++++++++++++++++++++ drivers/net/ethernet/mediatek/mtk_sgmii.c | 10 +++++++ 4 files changed, 73 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/eth= ernet/mediatek/mtk_eth_path.c index 72648535a14d..317e447f4991 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -96,12 +96,20 @@ static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth = *eth, int path) =20 static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path) { - unsigned int val =3D 0; + unsigned int val =3D 0, mask =3D 0, reg =3D 0; bool updated =3D true; =20 switch (path) { case MTK_ETH_PATH_GMAC2_SGMII: - val =3D CO_QPHY_SEL; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) { + reg =3D USB_PHY_SWITCH_REG; + val =3D SGMII_QPHY_SEL; + mask =3D QPHY_SEL_MASK; + } else { + reg =3D INFRA_MISC2; + val =3D CO_QPHY_SEL; + mask =3D val; + } break; default: updated =3D false; @@ -109,7 +117,7 @@ static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth= , int path) } =20 if (updated) - regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val); + regmap_update_bits(eth->infra, reg, mask, val); =20 dev_dbg(eth->dev, "path %s in %s updated =3D %d\n", mtk_eth_path_name(path), __func__, updated); diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 14be6ea51b88..cfb15a84b894 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -4860,6 +4860,26 @@ static const struct mtk_soc_data mt7629_data =3D { }, }; =20 +static const struct mtk_soc_data mt7981_data =3D { + .reg_map =3D &mt7986_reg_map, + .ana_rgc3 =3D 0x128, + .caps =3D MT7981_CAPS, + .hw_features =3D MTK_HW_FEATURES, + .required_clks =3D MT7981_CLKS_BITMAP, + .required_pctl =3D false, + .offload_version =3D 2, + .hash_offset =3D 4, + .foe_entry_size =3D sizeof(struct mtk_foe_entry), + .txrx =3D { + .txd_size =3D sizeof(struct mtk_tx_dma_v2), + .rxd_size =3D sizeof(struct mtk_rx_dma_v2), + .rx_irq_done_mask =3D MTK_RX_DONE_INT_V2, + .rx_dma_l4_valid =3D RX_DMA_L4_VALID_V2, + .dma_max_len =3D MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset =3D 8, + }, +}; + static const struct mtk_soc_data mt7986_data =3D { .reg_map =3D &mt7986_reg_map, .ana_rgc3 =3D 0x128, @@ -4902,6 +4922,7 @@ const struct of_device_id of_mtk_match[] =3D { { .compatible =3D "mediatek,mt7622-eth", .data =3D &mt7622_data}, { .compatible =3D "mediatek,mt7623-eth", .data =3D &mt7623_data}, { .compatible =3D "mediatek,mt7629-eth", .data =3D &mt7629_data}, + { .compatible =3D "mediatek,mt7981-eth", .data =3D &mt7981_data}, { .compatible =3D "mediatek,mt7986-eth", .data =3D &mt7986_data}, { .compatible =3D "ralink,rt5350-eth", .data =3D &rt5350_data}, {}, diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index afc9d52e79bf..7230dcb29315 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -551,11 +551,22 @@ #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 #define SGMII_PHYA_PWD BIT(4) =20 +/* Register to QPHY wrapper control */ +#define SGMSYS_QPHY_WRAP_CTRL 0xec +#define SGMII_PN_SWAP_MASK GENMASK(1, 0) +#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1)) +#define MTK_SGMII_FLAG_PN_SWAP BIT(0) + /* Infrasys subsystem config registers */ #define INFRA_MISC2 0x70c #define CO_QPHY_SEL BIT(0) #define GEPHY_MAC_SEL BIT(1) =20 +/* Top misc registers */ +#define USB_PHY_SWITCH_REG 0x218 +#define QPHY_SEL_MASK GENMASK(1, 0) +#define SGMII_QPHY_SEL 0x2 + /* MT7628/88 specific stuff */ #define MT7628_PDMA_OFFSET 0x0800 #define MT7628_SDM_OFFSET 0x0c00 @@ -736,6 +747,17 @@ enum mtk_clks_map { BIT(MTK_CLK_SGMII2_CDR_FB) | \ BIT(MTK_CLK_SGMII_CK) | \ BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) +#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_C= LK_GP1) | \ + BIT(MTK_CLK_WOCPU0) | \ + BIT(MTK_CLK_SGMII_TX_250M) | \ + BIT(MTK_CLK_SGMII_RX_250M) | \ + BIT(MTK_CLK_SGMII_CDR_REF) | \ + BIT(MTK_CLK_SGMII_CDR_FB) | \ + BIT(MTK_CLK_SGMII2_TX_250M) | \ + BIT(MTK_CLK_SGMII2_RX_250M) | \ + BIT(MTK_CLK_SGMII2_CDR_REF) | \ + BIT(MTK_CLK_SGMII2_CDR_FB) | \ + BIT(MTK_CLK_SGMII_CK)) #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_C= LK_GP1) | \ BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ BIT(MTK_CLK_SGMII_TX_250M) | \ @@ -849,6 +871,7 @@ enum mkt_eth_capabilities { MTK_NETSYS_V2_BIT, MTK_SOC_MT7628_BIT, MTK_RSTCTRL_PPE1_BIT, + MTK_U3_COPHY_V2_BIT, =20 /* MUX BITS*/ MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, @@ -883,6 +906,7 @@ enum mkt_eth_capabilities { #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) +#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) =20 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) @@ -955,6 +979,11 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) =20 +#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY = | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ + MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) + #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) @@ -1068,12 +1097,14 @@ struct mtk_soc_data { * @ana_rgc3: The offset refers to register ANA_RGC3 related to r= egmap * @interface: Currently configured interface mode * @pcs: Phylink PCS structure + * @flags: Flags indicating hardware properties */ struct mtk_pcs { struct regmap *regmap; u32 ana_rgc3; phy_interface_t interface; struct phylink_pcs pcs; + u32 flags; }; =20 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethern= et/mediatek/mtk_sgmii.c index bb00de1003ac..d7ffaaeaf9ab 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -88,6 +88,11 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsig= ned int mode, regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD, SGMII_PHYA_PWD); =20 + if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP) + regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, + SGMII_PN_SWAP_MASK, + SGMII_PN_SWAP_TX_RX); + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) rgc3 =3D RG_PHY_SPEED_3_125G; else @@ -182,6 +187,11 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device= _node *r, u32 ana_rgc3) =20 ss->pcs[i].ana_rgc3 =3D ana_rgc3; ss->pcs[i].regmap =3D syscon_node_to_regmap(np); + + ss->pcs[i].flags =3D 0; + if (of_property_read_bool(np, "mediatek,pnswap")) + ss->pcs[i].flags |=3D MTK_SGMII_FLAG_PN_SWAP; + of_node_put(np); if (IS_ERR(ss->pcs[i].regmap)) return PTR_ERR(ss->pcs[i].regmap); --=20 2.39.1