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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF000001D6.mail.protection.outlook.com (10.167.242.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Wed, 4 Sep 2024 22:23:17 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 4 Sep 2024 17:23:15 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 11/24] x86/resctrl: Remove MSR reading of event configuration value Date: Wed, 4 Sep 2024 17:21:26 -0500 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|LV2PR12MB5800:EE_ X-MS-Office365-Filtering-Correlation-Id: 4de047dc-fbab-4344-a9da-08dccd302ce6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|7416014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:17.3800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4de047dc-fbab-4344-a9da-08dccd302ce6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5800 Content-Type: text/plain; charset="utf-8" The event configuration is domain specific and initialized during domain initialization. The values are stored in struct rdt_hw_mon_domain. It is not required to read the configuration register every time user asks for it. Use the value stored in struct rdt_hw_mon_domain instead. Introduce resctrl_arch_event_config_get() and resctrl_arch_event_config_set() to get/set architecture domain specific mbm_total_cfg/mbm_local_cfg values. Signed-off-by: Babu Moger --- v7: Removed check if (val =3D=3D INVALID_CONFIG_VALUE) as resctrl_arch_even= t_config_get already prints warning. Kept the Event config value definitions as is. v6: Fixed inconstancy with types. Made all the types to u32 for config value. Removed few rdt_last_cmd_puts as it is not necessary. Removed unused config value definitions. Few more updates to commit message. v5: Introduced resctrl_arch_event_config_get and resctrl_arch_event_config_get() based on our discussion. https://lore.kernel.org/lkml/68e861f9-245d-4496-a72e-46fc57d19c62@amd.c= om/ v4: New patch. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 103 ++++++++++++++----------- include/linux/resctrl.h | 4 + 2 files changed, 62 insertions(+), 45 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 299722b3fd90..cc101fbe8683 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1597,10 +1597,57 @@ static int rdtgroup_size_show(struct kernfs_open_fi= le *of, } =20 struct mon_config_info { + struct rdt_mon_domain *d; u32 evtid; u32 mon_config; }; =20 +u32 resctrl_arch_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid) +{ + struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + return hw_dom->mbm_total_cfg; + case QOS_L3_MBM_LOCAL_EVENT_ID: + return hw_dom->mbm_local_cfg; + } + + /* Never expect to get here */ + WARN_ON_ONCE(1); + + return INVALID_CONFIG_VALUE; +} + +void resctrl_arch_event_config_set(void *info) +{ + struct mon_config_info *mon_info =3D info; + struct rdt_hw_mon_domain *hw_dom; + unsigned int index; + + index =3D mon_event_config_index_get(mon_info->evtid); + if (index =3D=3D INVALID_CONFIG_INDEX) + return; + + wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); + + hw_dom =3D resctrl_to_arch_mon_dom(mon_info->d); + + switch (mon_info->evtid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + hw_dom->mbm_total_cfg =3D mon_info->mon_config; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + hw_dom->mbm_local_cfg =3D mon_info->mon_config; + break; + } +} + /** * mon_event_config_index_get - get the hardware index for the * configurable event @@ -1623,33 +1670,11 @@ unsigned int mon_event_config_index_get(u32 evtid) } } =20 -static void mon_event_config_read(void *info) -{ - struct mon_config_info *mon_info =3D info; - unsigned int index; - u64 msrval; - - index =3D mon_event_config_index_get(mon_info->evtid); - if (index =3D=3D INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); - - /* Report only the valid event configuration bits */ - mon_info->mon_config =3D msrval & MAX_EVT_CONFIG_BITS; -} - -static void mondata_config_read(struct rdt_mon_domain *d, struct mon_confi= g_info *mon_info) -{ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_read, mon_info, = 1); -} - static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32= evtid) { - struct mon_config_info mon_info =3D {0}; struct rdt_mon_domain *dom; bool sep =3D false; + u32 val; =20 cpus_read_lock(); mutex_lock(&rdtgroup_mutex); @@ -1658,11 +1683,8 @@ static int mbm_config_show(struct seq_file *s, struc= t rdt_resource *r, u32 evtid if (sep) seq_puts(s, ";"); =20 - memset(&mon_info, 0, sizeof(struct mon_config_info)); - mon_info.evtid =3D evtid; - mondata_config_read(dom, &mon_info); - - seq_printf(s, "%d=3D0x%02x", dom->hdr.id, mon_info.mon_config); + val =3D resctrl_arch_event_config_get(dom, evtid); + seq_printf(s, "%d=3D0x%02x", dom->hdr.id, val); sep =3D true; } seq_puts(s, "\n"); @@ -1693,33 +1715,23 @@ static int mbm_local_bytes_config_show(struct kernf= s_open_file *of, return 0; } =20 -static void mon_event_config_write(void *info) -{ - struct mon_config_info *mon_info =3D info; - unsigned int index; - - index =3D mon_event_config_index_get(mon_info->evtid); - if (index =3D=3D INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); -} =20 static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_mon_domain *d, u32 evtid, u32 val) { struct mon_config_info mon_info =3D {0}; + u32 config_val; =20 /* - * Read the current config value first. If both are the same then + * Check the current config value first. If both are the same then * no need to write it again. */ - mon_info.evtid =3D evtid; - mondata_config_read(d, &mon_info); - if (mon_info.mon_config =3D=3D val) + config_val =3D resctrl_arch_event_config_get(d, evtid); + if (config_val =3D=3D INVALID_CONFIG_VALUE || config_val =3D=3D val) return; =20 + mon_info.d =3D d; + mon_info.evtid =3D evtid; mon_info.mon_config =3D val; =20 /* @@ -1728,7 +1740,8 @@ static void mbm_config_write_domain(struct rdt_resour= ce *r, * are scoped at the domain level. Writing any of these MSRs * on one CPU is observed by all the CPUs in the domain. */ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_write, + smp_call_function_any(&d->hdr.cpu_mask, + resctrl_arch_event_config_set, &mon_info, 1); =20 /* diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index aab22ff8e0c1..757708cf5d3c 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -354,6 +354,10 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_mon_domain *d, */ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d); =20 +void resctrl_arch_event_config_set(void *info); +u32 resctrl_arch_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid); + extern unsigned int resctrl_rmid_realloc_threshold; extern unsigned int resctrl_rmid_realloc_limit; =20 --=20 2.34.1