From nobody Mon Feb 9 01:22:01 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B781EA7CC; Tue, 27 Jan 2026 13:18:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769519933; cv=none; b=cu3ufLJiX9DI0D7USKrBV0aC19hPrtzQykOCVZ0erUry8eorF6KOPLz3AXCEtpQEFzJHYrgJm6ZKGZ98eO70bscbYSn9ZoYbIfsSaulDgozds5zq/h7QouhLbP58BTp7V7eaqT4rTCThd+igsMUQxUkX6AvYJyf26CaY9AWIM1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769519933; c=relaxed/simple; bh=D42JR7u13Ao0gUEQVTk0Kz9ZYGv29KYP29e+BV8Iv+k=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=WBAjWlgznzW9g6OyD0DpjvYKpnvmjqtDiP6K6BuBfQ71hvQNq29mEEQ5HeziIEmoKIw5KlceCkSgnuCpqAyw1dYyxz3GEf0Wgbza6cIMhLpC3ilUy7vMdXAZ09Tvvf3kMwEBE2qL+WoQYIJy6gN1E0F12+Ikmqz4hR/HJ5gbYho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vkiy0-000000000Sn-2NvO; Tue, 27 Jan 2026 13:18:48 +0000 Date: Tue, 27 Jan 2026 13:18:45 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/3] net: dsa: mxl-gsw1xx: configure PCS polarities Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Configure SerDes PCS RX and TX polarities using the newly introduced generic properties. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/Kconfig | 1 + drivers/net/dsa/lantiq/mxl-gsw1xx.c | 38 +++++++++++++++++++++-------- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/lantiq/Kconfig b/drivers/net/dsa/lantiq/Kconfig index bad13817af25..98efeef2661b 100644 --- a/drivers/net/dsa/lantiq/Kconfig +++ b/drivers/net/dsa/lantiq/Kconfig @@ -15,6 +15,7 @@ config NET_DSA_MXL_GSW1XX tristate "MaxLinear GSW1xx Ethernet switch support" select NET_DSA_TAG_MXL_GSW1XX select NET_DSA_LANTIQ_COMMON + select PHY_COMMON_PROPS help This enables support for the Intel/MaxLinear GSW1xx family of 1GE switches. diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index 79cf72cc77be..6284b9afdbbb 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include #include @@ -229,11 +231,17 @@ static int gsw1xx_pcs_phy_xaui_write(struct gsw1xx_pr= iv *priv, u16 addr, 1000, 100000); } =20 -static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) +static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv, phy_interface_t inte= rface) { + struct dsa_port *pcs_port; + unsigned int pol; int ret; u16 val; =20 + pcs_port =3D dsa_to_port(priv->gswip.ds, GSW1XX_SGMII_PORT); + if (!pcs_port) + return -EINVAL; + /* Assert and deassert SGMII shell reset */ ret =3D regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, GSW1XX_RST_REQ_SGMII_SHELL); @@ -260,15 +268,19 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT, GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF); =20 + ret =3D phy_get_rx_polarity(of_fwnode_handle(pcs_port->dn), + phy_modes(interface), + BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), + PHY_POL_NORMAL, &pol); + if (ret) + return ret; + /* RX lane seems to be inverted internally, so bit * GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal * (ie. non-inverted) operation. - * - * TODO: Take care of inverted RX pair once generic property is - * available */ - - val |=3D GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; + if (pol =3D=3D PHY_POL_NORMAL) + val |=3D GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; =20 ret =3D regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val); if (ret < 0) @@ -277,9 +289,15 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) val =3D FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL, GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF); =20 - /* TODO: Take care of inverted TX pair once generic property is - * available - */ + ret =3D phy_get_tx_polarity(of_fwnode_handle(pcs_port->dn), + phy_modes(interface), + BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), + PHY_POL_NORMAL, &pol); + if (ret) + return ret; + + if (pol =3D=3D PHY_POL_INVERT) + val |=3D GSW1XX_SGMII_PHY_TX0_CFG3_INVERT; =20 ret =3D regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val); if (ret < 0) @@ -336,7 +354,7 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, u= nsigned int neg_mode, priv->tbi_interface =3D PHY_INTERFACE_MODE_NA; =20 if (!reconf) - ret =3D gsw1xx_pcs_reset(priv); + ret =3D gsw1xx_pcs_reset(priv, interface); =20 if (ret) return ret; --=20 2.52.0