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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 21:13:36.9004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e39b8a1d-afcc-4e69-3cec-08de5931f155 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8086 Content-Type: text/plain; charset="utf-8" Add the documentation and example to setup Global Memory Bandwidth Allocation (GMBA) in resctrl filesystem. Signed-off-by: Babu Moger --- Documentation/filesystems/resctrl.rst | 43 +++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index 94187dd3c244..6ff6162719e8 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -28,6 +28,7 @@ SMBA (Slow Memory Bandwidth Allocation) "" BMEC (Bandwidth Monitoring Event Configuration) "" ABMC (Assignable Bandwidth Monitoring Counters) "" SDCIAE (Smart Data Cache Injection Allocation Enforcement) "" +GMBA (Global Memory Bandwidth Allocation) "" =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Historically, new features were made visible by default in /proc/cpuinfo. = This @@ -960,6 +961,21 @@ Memory bandwidth domain is L3 cache. =20 MB:=3Dbw_MiBps0;=3Dbw_MiBps1;... =20 +Global Memory bandwidth Allocation +----------------------------------- + +AMD hardware supports Global Memory Bandwidth Allocation (GMBA) provides +a mechanism for software to specify bandwidth limits for groups of threads +that span across multiple QoS domains. This collection of QOS domains is +referred to as GMBA control domain. The GMBA control domain is created by +setting the same GMBA limits in one or more QoS domains. Setting the defau= lt +max_bandwidth excludes the QoS domain from being part of GMBA control doma= in. + +Global Memory b/w domain is L3 cache. +:: + + GMB:=3Dbandwidth;=3Dbandwidth;... + Slow Memory Bandwidth Allocation (SMBA) --------------------------------------- AMD hardware supports Slow Memory Bandwidth Allocation (SMBA). @@ -997,8 +1013,8 @@ which you wish to change. E.g. Reading/writing the schemata file (on AMD systems) -------------------------------------------------- Reading the schemata file will show the current bandwidth limit on all -domains. The allocated resources are in multiples of one eighth GB/s. -When writing to the file, you need to specify what cache id you wish to +domains. The allocated resources are in multiples of 1/8 GB/s. When +writing to the file, you need to specify what cache id you wish to configure the bandwidth limit. =20 For example, to allocate 2GB/s limit on the first cache id: @@ -1014,6 +1030,29 @@ For example, to allocate 2GB/s limit on the first ca= che id: MB:0=3D2048;1=3D 16;2=3D2048;3=3D2048 L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff =20 +Reading/writing the schemata file (on AMD systems) with GMBA feature +-------------------------------------------------------------------- +Reading the schemata file will show the current bandwidth limit on all +domains. The allocated resources are in multiples of 1 GB/s. The GMBA +control domain is created by setting the same GMBA limits in one or more +QoS domains. + +For example, to configure a GMBA domain consisting of domains 0 and 2 +with an 8 GB/s limit: + +:: + + # cat schemata + GMB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + MB:0=3D4096;1=3D4096;2=3D4096;3=3D4096 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "GMB:0=3D8;2=3D8" > schemata + # cat schemata + GMB:0=3D 8;1=3D2048;2=3D 8;3=3D2048 + MB:0=3D4096;1=3D4096;2=3D4096;3=3D4096 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + Reading/writing the schemata file (on AMD systems) with SMBA feature -------------------------------------------------------------------- Reading and writing the schemata file is the same as without SMBA in --=20 2.34.1