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Wed, 08 Jan 2025 01:41:31 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2c27b54sm14879005e9.0.2025.01.08.01.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 01:41:31 -0800 (PST) Date: Wed, 8 Jan 2025 12:41:28 +0300 From: Dan Carpenter To: Jesse Zhang Cc: Alex Deucher , Christian =?iso-8859-1?Q?K=F6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Hawking Zhang , Tim Huang , "Jesse.zhang@amd.com" , Likun Gao , Mario Limonciello , Yang Wang , Le Ma , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH] drm/amdgpu: Fix shift type in amdgpu_debugfs_sdma_sched_mask_set() Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline X-Mailer: git-send-email haha only kidding Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The "mask" and "val" variables are type u64. The problem is that the BIT() macros are type unsigned long which is just 32 bits on 32bit systems. It's unlikely that people will be using this driver on 32bit kernels and even if they did we only use the lower AMDGPU_MAX_SDMA_INSTANCES (16) bits. So this bug does not affect anything in real life. Still, for correctness sake, u64 bit masks should use BIT_ULL(). Fixes: d2e3961ae371 ("drm/amdgpu: add amdgpu_sdma_sched_mask debugfs") Signed-off-by: Dan Carpenter --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_sdma.c index 632295bf3875..174badca27e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -362,13 +362,13 @@ static int amdgpu_debugfs_sdma_sched_mask_set(void *d= ata, u64 val) if (!adev) return -ENODEV; =20 - mask =3D (1 << adev->sdma.num_instances) - 1; + mask =3D BIT_ULL(adev->sdma.num_instances) - 1; if ((val & mask) =3D=3D 0) return -EINVAL; =20 for (i =3D 0; i < adev->sdma.num_instances; ++i) { ring =3D &adev->sdma.instance[i].ring; - if (val & (1 << i)) + if (val & BIT_ULL(i)) ring->sched.ready =3D true; else ring->sched.ready =3D false; --=20 2.45.2