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Wed, 15 Oct 2025 12:43:08 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , Subject: [PATCH v3 7/7] iommu/arm-smmu-v3: Perform per-domain invalidations using arm_smmu_invs Date: Wed, 15 Oct 2025 12:42:52 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009B:EE_|BL3PR12MB6620:EE_ X-MS-Office365-Filtering-Correlation-Id: 505b05b4-9bc4-46bc-55dc-08de0c231ca3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?sAS5afMRve61y0TXBIsN8mLRQAOoDJc8vkwOwq0vW4JeVLLvqHvEBv3get7+?= =?us-ascii?Q?qQqvo5wY6R2tWryqn9lSUznSckWbY5egdVxV2Ivm+g3UJ+CARj1fQonSV7fo?= =?us-ascii?Q?Uthyw/Nr3ua1+2bXWm5v9AWh9UH/Hd0B1BMgzOhBh3anIFtb2A78RewcKn0D?= =?us-ascii?Q?q659aCEtPFCyS3rILNg3bzvw3RxvPWnJbVfFtO9GIlSdTECaEnjPFnTzGqX3?= =?us-ascii?Q?ByaVwm+D0ggbXua03n5sPWyndR77Beu0BWdNKGXxb5R3J+LnErBU8wM5YmK/?= =?us-ascii?Q?/xnJv6F9QQ+dH8NK6Ob+TMCc0bk+XwpNEbHrHjHJjYwzkh+TFQ5b8UOWjwHf?= =?us-ascii?Q?1nnXgukkvYBXDJBn1BW46Ib7WgNJeTSjeBbh1m0F72+Rig3jf/WJwRrji/GF?= =?us-ascii?Q?XB+UJQMHM3/4TfKD8WXFlCB5kHQfW5I8+3uKNR8KN/bwF2BkAMfTGX5K+ynh?= =?us-ascii?Q?9twGoaq+rVBbxlDm44rDwqKpW2EbxzmVtVpQ1IK329Tfw0qcCQEiCYPsRcBe?= =?us-ascii?Q?H8DeGjrf9QixXxD0JlcR10g+XsQpFVtJVlF/b0B1pUkuvyxxHm/CED1+yo7E?= =?us-ascii?Q?EtOZGq0t0xMOYztXG1I0MiV22B7lr0CahzVUahFB291a0nwOCL1Q55RiA4S4?= =?us-ascii?Q?KiIjmdU6oBPH2n00L2aeZLzra4a6LTwP1wOOSSZRjMBxZLLtbf86b0ZG2rwL?= =?us-ascii?Q?tuGhiASxOXvh7WLcnP2Vc6VjZsnS6rQFaz6kFbCmNn+I0W3hbLSINk0Df+Vo?= =?us-ascii?Q?qV3Aw/VhWeOSlC2mPJVtYEnknOt5Zom14EN3PXU86MaWKVo5FjM3u9Kfty89?= =?us-ascii?Q?39T6IQxG9OTtKsCvD1Hzknaq2DQMTzh5aRFqsYhxAIDBT5BzFE+httnCMkD0?= =?us-ascii?Q?oQneMZd1rpXBW4uvM47WKbqcrYKfyKKLHmUoiXhkMb3x5i58mmaFRZntQpj3?= =?us-ascii?Q?6quWAgXqC/n1rg+8GUVwk0Kijly5wY6c4LwmWY/ZIXgP+QWo5Q0zE1gNE+BI?= =?us-ascii?Q?eklEJe9gOBJ9HM8+4IcADfXF5m7NyvJidJ9yJarA7XcB0Wlv/tDJfc80OGZ0?= =?us-ascii?Q?HqEcd32Th7Jlp8o93fCj7otEIvrMuEFkRbpd4ae65s8+6kwE20QrYJUTMZSu?= =?us-ascii?Q?YVKw1IzNuMFEBvsLieponH40rkZt3scuw/WbB50BiKNvYDFW1oJCr9XqbhU8?= =?us-ascii?Q?T2W3vpVyMMV3YA4yeacEhTKQdTtJg/17rXkKTPeE/4bEB5mSs2ELxL34yHEk?= =?us-ascii?Q?6vVPW5hTB1spp+53lmx7ky2Pa1UIg0xLVH2YFVEXZuCLjovZ+HekOkcr99Bl?= =?us-ascii?Q?NUv4l/cuOSE5MRpNQvaaizj8fkaT76+RkhVR9JHPSCthElagN8ePphZhmw+f?= =?us-ascii?Q?pbJOIslA7gZeiF2K1psTeTq0fZ3nKsTQqpJCaFhKdrr8wB4tPuWrK/OQAc8s?= =?us-ascii?Q?WgOhBBTroBp+IQiCvgkHyGt6CrAns3QMFGhK1p/TZjCqYF0pWBG+EMA75YDN?= =?us-ascii?Q?OX4xZunQcA8Q2jnD7oMg6driJLi4faeWBqwE2700kZTAQ2W4ZJp/e3ESdsPL?= =?us-ascii?Q?MatjUz/SFTGc7FHgV3c=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2025 19:43:27.5542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 505b05b4-9bc4-46bc-55dc-08de0c231ca3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6620 Content-Type: text/plain; charset="utf-8" Replace the old invalidation functions with arm_smmu_domain_inv_range() in all the existing invalidation routines. And deprecate the old functions. The new arm_smmu_domain_inv_range() handles the CMDQ_MAX_TLBI_OPS as well, so drop it in the SVA function. Since arm_smmu_cmdq_batch_add_range() has only one caller now, and it must be given a valid size, add a WARN_ON_ONCE to catch any missed case. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 - .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 29 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 165 +----------------- 3 files changed, 11 insertions(+), 190 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ab166de50f3e1..2b24e3a9bc8d4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1071,13 +1071,6 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old); =20 -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain); -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size); - void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size, unsigned int granule, bool leaf); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index fc601b494e0af..048b53f79b144 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -122,15 +122,6 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_sva_cd); =20 -/* - * Cloned from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, this - * is used as a threshold to replace per-page TLBI commands to issue in the - * command queue with an address-space TLBI command, when SMMU w/o a range - * invalidation feature handles too many per-page TLBI commands, which will - * otherwise result in a soft lockup. - */ -#define CMDQ_MAX_TLBI_OPS (1 << (PAGE_SHIFT - 3)) - static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier= *mn, struct mm_struct *mm, unsigned long start, @@ -146,21 +137,8 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs= (struct mmu_notifier *mn, * range. So do a simple translation here by calculating size correctly. */ size =3D end - start; - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { - if (size >=3D CMDQ_MAX_TLBI_OPS * PAGE_SIZE) - size =3D 0; - } else { - if (size =3D=3D ULONG_MAX) - size =3D 0; - } - - if (!size) - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - else - arm_smmu_tlb_inv_range_asid(start, size, smmu_domain->cd.asid, - PAGE_SIZE, false, smmu_domain); =20 - arm_smmu_atc_inv_domain(smmu_domain, start, size); + arm_smmu_domain_inv_range(smmu_domain, start, size, PAGE_SIZE, false); } =20 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct = *mm) @@ -191,8 +169,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) @@ -301,7 +278,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domai= n *domain) /* * Ensure the ASID is empty in the iommu cache before allowing reuse. */ - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); + arm_smmu_domain_inv(smmu_domain); =20 /* * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e74c788c23673..776e1ec88da7a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1250,16 +1250,6 @@ struct arm_smmu_invs *arm_smmu_invs_purge(struct arm= _smmu_invs *invs, EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_purge); =20 /* Context descriptor manipulation functions */ -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, - .tlbi.asid =3D asid, - }; - - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); -} =20 /* * Based on the value of ent report which bits of the STE the HW will acce= ss. It @@ -2414,74 +2404,10 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_= master *master, return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); } =20 -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size) -{ - struct arm_smmu_master_domain *master_domain; - int i; - unsigned long flags; - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D CMDQ_OP_ATC_INV, - }; - struct arm_smmu_cmdq_batch cmds; - - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) - return 0; - - /* - * Ensure that we've completed prior invalidation of the main TLBs - * before we read 'nr_ats_masters' in case of a concurrent call to - * arm_smmu_enable_ats(): - * - * // unmap() // arm_smmu_enable_ats() - * TLBI+SYNC atomic_inc(&nr_ats_masters); - * smp_mb(); [...] - * atomic_read(&nr_ats_masters); pci_enable_ats() // writel() - * - * Ensures that we always see the incremented 'nr_ats_masters' count if - * ATS was enabled at the PCI device before completion of the TLBI. - */ - smp_mb(); - if (!atomic_read(&smmu_domain->nr_ats_masters)) - return 0; - - arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); - - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_for_each_entry(master_domain, &smmu_domain->devices, - devices_elm) { - struct arm_smmu_master *master =3D master_domain->master; - - if (!master->ats_enabled) - continue; - - if (master_domain->nested_ats_flush) { - /* - * If a S2 used as a nesting parent is changed we have - * no option but to completely flush the ATC. - */ - arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); - } else { - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, - &cmd); - } - - for (i =3D 0; i < master->num_streams; i++) { - cmd.atc.sid =3D master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); - } - } - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); - - return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); -} - /* IO_PGTABLE API */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd; =20 /* * NOTE: when io-pgtable is in non-strict mode, we may get here with @@ -2490,14 +2416,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); - } - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu, @@ -2509,7 +2428,7 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_= smmu_device *smmu, unsigned long end =3D iova + size, num_pages =3D 0, tg =3D pgsize; size_t inv_range =3D granule; =20 - if (!size) + if (WARN_ON_ONCE(!size)) return; =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { @@ -2564,76 +2483,6 @@ static void arm_smmu_cmdq_batch_add_range(struct arm= _smmu_device *smmu, } } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_batch cmds; - size_t pgsize; - - /* Get the leaf page size */ - pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); - - arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); - arm_smmu_cmdq_batch_add_range(smmu, &cmds, cmd, iova, size, granule, - pgsize); - arm_smmu_cmdq_batch_submit(smmu, &cmds); -} - -static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .tlbi =3D { - .leaf =3D leaf, - }, - }; - - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->cd.asid; - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); - - if (smmu_domain->nest_parent) { - /* - * When the S2 domain changes all the nested S1 ASIDs have to be - * flushed too. - */ - cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; - arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); - } - - /* - * Unfortunately, this can't be leaf-only since we may have - * zapped an entire table. - */ - arm_smmu_atc_inv_domain(smmu_domain, iova, size); -} - -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA, - .tlbi =3D { - .asid =3D asid, - .leaf =3D leaf, - }, - }; - - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); -} - static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t= size, size_t granule) { @@ -2828,7 +2677,9 @@ static void arm_smmu_tlb_inv_page_nosync(struct iommu= _iotlb_gather *gather, static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size, size_t granule, void *cookie) { - arm_smmu_tlb_inv_range_domain(iova, size, granule, false, cookie); + struct arm_smmu_domain *smmu_domain =3D cookie; + + arm_smmu_domain_inv_range(smmu_domain, iova, size, granule, false); } =20 static const struct iommu_flush_ops arm_smmu_flush_ops =3D { @@ -4072,9 +3923,9 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *= domain, if (!gather->pgsize) return; =20 - arm_smmu_tlb_inv_range_domain(gather->start, - gather->end - gather->start + 1, - gather->pgsize, true, smmu_domain); + arm_smmu_domain_inv_range(smmu_domain, gather->start, + gather->end - gather->start + 1, + gather->pgsize, true); } =20 static phys_addr_t --=20 2.43.0