From nobody Tue Sep 29 07:39:15 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B19173B14BA; Tue, 11 Aug 2026 06:46:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786430816; cv=none; b=eCotJY3Jwzgjr58o8z6V+C4nAizCGd4+mAsFsP43Rp1777OjNL45JW+euvAkl+TgISoK0lHZrtjWOMYOURgRdBpWJ/XW8C7wS4vcIyKPj+tHY04ke0bUL7jxLJvN50d/cBEBaDaWBqiIt3NcE4ovgRucp7dKgGiVVpK0vEl7uMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786430816; c=relaxed/simple; bh=Pd+Nydszg0VLcwlJdQVfG1xhy5KZ4Er5r8GXP45p7Ts=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HF4+s9yrAqBqCR26n5BgOLUuxFl3jUNS4EZ+pf985XS14WHawvj/Wgf1OibzXys7qGlTOz8Pyh7m9Ajjna1Q2JVbxgoFtws6r6G1N5TOV6CpvqD1lADUdoOpxfuTUUt7pQ05h72JauWkO/o6UpVFvzAKUD0oHqLjBGGfyrn7FVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: 6c1ffac8955011f1aa26b74ffac11d73-20260811 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:9a85338c-678d-400a-9cd4-bfdf04068745,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:e7bac3a,CLOUDID:a1e2bc4faf5dd41e4fe73d5d993c1801,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|865|898,TC:nil,Content:0|15|50 ,EDM:-3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,O SA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 6c1ffac8955011f1aa26b74ffac11d73-20260811 X-User: liuxixin@kylinos.cn Received: from [127.0.1.1] [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 1551363430; Tue, 11 Aug 2026 14:46:46 +0800 From: Xixin Liu To: linux-riscv@lists.infradead.org Cc: atish.patra@linux.dev, anup@brainfault.org, will@kernel.org, mark.rutland@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, liuxixin@kylinos.cn Subject: [PATCH v2 1/1] perf: RISC-V: check cpu_hw_evt before dereference in overflow IRQ Date: Tue, 11 Aug 2026 11:51:00 +0800 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: patches/scripts/send-local.py Content-Type: text/plain; charset="utf-8" The overflow IRQ handler dereferences cpu_hw_evt before the null check. Move the check first. Defensive only; the cookie is valid on the normal path today. Fixes: a8625217a054 ("drivers/perf: riscv: Implement SBI PMU snapshot funct= ion") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu --- drivers/perf/riscv_pmu_sbi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index dfc886dee5ad..f0dd9d2645b4 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1050,11 +1050,13 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, voi= d *dev) u64 overflowed_ctrs =3D 0; struct cpu_hw_events *cpu_hw_evt =3D dev; u64 start_clock =3D sched_clock(); - struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; + struct riscv_pmu_snapshot_data *sdata; =20 if (WARN_ON_ONCE(!cpu_hw_evt)) return IRQ_NONE; =20 + sdata =3D cpu_hw_evt->snapshot_addr; + /* Firmware counter don't support overflow yet */ fidx =3D find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS); if (fidx =3D=3D RISCV_MAX_COUNTERS) { --=20 2.43.0