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Tue, 15 Sep 2026 15:12:07 -0400 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v2 01/15] iio: adc: ad4134: Sign extend sample data Date: Tue, 15 Sep 2026 16:11:59 -0300 Message-ID: <7083358e62e3edfeeba0201aefd8d3195ee951d0.1789494473.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=JekpPkKV c=1 sm=1 tr=0 ts=6aa99894 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=TOduCJ2NwqVHWOW4apYA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfX1diqo2UsveOF kTcn9gAmL2KjPNyNDdMKfLnwlVJljkXIDY3fYYqU2b9INF2ES3DPZMcKyfGQSmkZMFwHQcxTT+U sJEpkKBrO9XfAzoFTNYBWKCF53c/dh4ob38IqHQmBma6v/0uPDByA0vIwOk0Hg4HncBgwO2Rxfk 5NBl4SMxgUN2HDzI0pO0UW0GwOr4c6vbH5RIggQpV5RoYSTnnj+dxlOn07oxJsOT7DJzpAi15kx HG1TYLtj2y6NlQrwxs8NTtac0Y5reid2/RoGo6SoFZS3Mjuaa12eTyZnu09s5e68igc+eyFcLrh YopZmOnsBtoXxM8sPp8btieIOYjse7IfriyE5YsUiKCm9UdQe0xZgeLUMB9kyhjYwDnYvtKYdwT i/5yhHVvOFxRvJeaQJx2jDZczlcrXmkGj60+L7H6KXQhFi6Z9x46eED9ef5xxJQr6DEY/9YGlCv YIxRqVt3psFCy5DTMkg== X-Proofpoint-GUID: BiAI0m3T7Y7GHRzPngG8tZZxOfhKN53x X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfX4Bx/HFo1P7FF Btxy82nWFmovnF2WgLkW+KW9aLmTs/AI90nr3n5kj+We2Fizw/hplNN9eaDG0ct+IfbHGaQ5UjH 8PzzmDmZkt5zEPjDUK0g2Cy/zacj3HAwXz9sT0OC5kWo3wIdgaNE X-Proofpoint-ORIG-GUID: BiAI0m3T7Y7GHRzPngG8tZZxOfhKN53x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150280 Content-Type: text/plain; charset="utf-8" Sign extend ADC sample data for correct delivery of negative ADC input difference. Fixes: e0bc6d7e2584 ("iio: adc: Initial support for AD4134") Signed-off-by: Marcelo Schmitt --- New patch in v2. drivers/iio/adc/ad4134.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 0490218bb0e9..7d40c0521bb3 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -172,6 +172,7 @@ static int ad4134_data_read(struct ad4134_state *st, un= signed int reg, unsigned int *val) { unsigned int i; + u32 sample; int ret; =20 /* @@ -196,8 +197,9 @@ static int ad4134_data_read(struct ad4134_state *st, un= signed int reg, * Clock out data from all channels to avoid that. */ if (i =3D=3D AD4134_VREG_CH(reg)) - *val =3D get_unaligned_be24(st->rx_buf); + sample =3D get_unaligned_be24(st->rx_buf); } + *val =3D sign_extend32(sample, AD4134_CHAN_PRECISION_BITS - 1); =20 return 0; } --=20 2.53.0 From nobody Fri Sep 25 06:46:12 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E6534C1505; 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Tue, 15 Sep 2026 15:12:27 -0400 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Andy Shevchenko Subject: [PATCH v2 02/15] iio: Fix typo in vendor name Date: Tue, 15 Sep 2026 16:12:19 -0300 Message-ID: <8ba81bb20d92fbfd8e4b7ce80093223fcb8534b0.1789494473.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: acmET71vuCDuDkpOAtCg5QR3cmCUW1vY X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfXzrJl48BBNmbN WE3bkth3W7d2Xb4lyvRSd6jkU165o0zrgQZTrE2jQjlQX9vFqI/SqaEojMk6tYx92RXW6iktHAQ C76CzvDW3BCC00TG5W6y45kRrn8g9V/MoZqq5tzym2Vlz2S8Jybr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfXx4AEmdsSHePY xC+55szdiAMHY/kzTOv+KGOSEOkY6nmxOqKApwqrbJjBAU4npEpOC/V4cl4RNMsMdQM3rxFXTw1 JHeNChvmqm1tgT0ZDtn6JDLjO2jWlBbyD0lFPrNwxWuGtkFW2di234fhtkvOy5ejz8dWx08iUSx bhJ0fPStRbXTDHDUR+/KPGyjSJhAhoEKqyS0vD2lnQOjKIsn4Q5VrN8Nts/pw/0ONJwiyl8n5f2 e1IV2iRNsmiRCdFZBISy5dMJLzoUzGlm4u+BuZ6OHUGWEaMMqXCKxt1F9a3SuLuCIIN9SYH8Mhc DF4WKgnQPoykpus8I74gXa8nlxNZH0eSPa+pNkvW1TjjcPUug9STzeIoaegENR9xZtpUemdpLv2 XqUKndOpKq0TQCyDeVpDBuXHFcjFOILeDTCanMGQsFw/7CGQCObuUfAyplWE9gesIJA5Jhm7XRd R8KsLBGizRNBZ0XZVlg== X-Authority-Analysis: v=2.4 cv=HZeB3SE8 c=1 sm=1 tr=0 ts=6aa998aa cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=QyXUC8HyAAAA:8 a=gAnH3GRIAAAA:8 a=MCMPggia4XBponqUwisA:9 X-Proofpoint-GUID: acmET71vuCDuDkpOAtCg5QR3cmCUW1vY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150280 Content-Type: text/plain; charset="utf-8" Correct a typo in vendor company name: "Analog Device" -> "Analog Devices". Reviewed-by: Andy Shevchenko Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Now also fixing Analog Devices possessive suffix usage. Documentation/iio/ade9000.rst | 2 +- Documentation/iio/adis16475.rst | 2 +- Documentation/iio/adis16480.rst | 2 +- Documentation/iio/adis16550.rst | 2 +- Documentation/iio/adxl313.rst | 2 +- Documentation/iio/adxl345.rst | 2 +- Documentation/iio/adxl380.rst | 2 +- drivers/iio/adc/Kconfig | 12 ++++++------ drivers/iio/dac/ad3552r.c | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/Documentation/iio/ade9000.rst b/Documentation/iio/ade9000.rst index 72737b5ec59c..f41660005223 100644 --- a/Documentation/iio/ade9000.rst +++ b/Documentation/iio/ade9000.rst @@ -4,7 +4,7 @@ ADE9000/ADE9078 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's ADE9000 and ADE9078 energy measurement +This driver supports Analog Devices' ADE9000 and ADE9078 energy measurement ICs on SPI bus. =20 1. Supported devices diff --git a/Documentation/iio/adis16475.rst b/Documentation/iio/adis16475.= rst index 89a388490ab7..0e004f016199 100644 --- a/Documentation/iio/adis16475.rst +++ b/Documentation/iio/adis16475.rst @@ -4,7 +4,7 @@ ADIS16475 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's IMUs on SPI bus. +This driver supports Analog Devices' IMUs on SPI bus. =20 1. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Documentation/iio/adis16480.rst b/Documentation/iio/adis16480.= rst index cce5f3e01741..7c259070aaaf 100644 --- a/Documentation/iio/adis16480.rst +++ b/Documentation/iio/adis16480.rst @@ -4,7 +4,7 @@ ADIS16480 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's IMUs on SPI bus. +This driver supports Analog Devices' IMUs on SPI bus. =20 1. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Documentation/iio/adis16550.rst b/Documentation/iio/adis16550.= rst index c9bbc0a857b0..c0d5a975e6ca 100644 --- a/Documentation/iio/adis16550.rst +++ b/Documentation/iio/adis16550.rst @@ -4,7 +4,7 @@ ADIS16550 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's IMUs on SPI bus. +This driver supports Analog Devices' IMUs on SPI bus. =20 1. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Documentation/iio/adxl313.rst b/Documentation/iio/adxl313.rst index 3641193bf647..c448f10745e7 100644 --- a/Documentation/iio/adxl313.rst +++ b/Documentation/iio/adxl313.rst @@ -4,7 +4,7 @@ ADXL313 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's ADXL313 on SPI/I2C bus. +This driver supports Analog Devices' ADXL313 on SPI/I2C bus. =20 1. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Documentation/iio/adxl345.rst b/Documentation/iio/adxl345.rst index 0aa33a852412..28c71fbd45e5 100644 --- a/Documentation/iio/adxl345.rst +++ b/Documentation/iio/adxl345.rst @@ -4,7 +4,7 @@ ADXL345 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's ADXL345/375 on SPI/I2C bus. +This driver supports Analog Devices' ADXL345/375 on SPI/I2C bus. =20 1. Supported Devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Documentation/iio/adxl380.rst b/Documentation/iio/adxl380.rst index a1c249dc2e51..969ded211cc9 100644 --- a/Documentation/iio/adxl380.rst +++ b/Documentation/iio/adxl380.rst @@ -4,7 +4,7 @@ ADXL380 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -This driver supports Analog Device's ADXL380/382 on SPI/I2C bus. +This driver supports Analog Devices' ADXL380/382 on SPI/I2C bus. =20 1. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 0aca02962947..7f90fea3d1f0 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -105,7 +105,7 @@ config AD4080 called ad4080. =20 config AD4130 - tristate "Analog Device AD4130 ADC Driver" + tristate "Analog Devices AD4130 ADC Driver" depends on SPI depends on GPIOLIB select IIO_BUFFER @@ -121,7 +121,7 @@ config AD4130 called ad4130. =20 config AD4134 - tristate "Analog Device AD4134 ADC Driver" + tristate "Analog Devices AD4134 ADC Driver" depends on SPI select REGMAP_SPI select CRC8 @@ -133,7 +133,7 @@ config AD4134 called ad4134_spi. =20 config AD4170_4 - tristate "Analog Device AD4170-4 ADC Driver" + tristate "Analog Devices AD4170-4 ADC Driver" depends on SPI select REGMAP_SPI select IIO_BUFFER @@ -164,7 +164,7 @@ config AD4691 called ad4691. =20 config AD4695 - tristate "Analog Device AD4695 ADC Driver" + tristate "Analog Devices AD4695 ADC Driver" depends on SPI select IIO_BUFFER select IIO_BUFFER_DMAENGINE @@ -179,7 +179,7 @@ config AD4695 called ad4695. =20 config AD4851 - tristate "Analog Device AD4851 DAS Driver" + tristate "Analog Devices AD4851 DAS Driver" depends on SPI depends on PWM select REGMAP_SPI @@ -347,7 +347,7 @@ config AD7380 called ad7380. =20 config AD7405 - tristate "Analog Device AD7405 ADC Driver" + tristate "Analog Devices AD7405 ADC Driver" depends on IIO_BACKEND help Say yes here to build support for Analog Devices AD7405, ADUM7701, diff --git a/drivers/iio/dac/ad3552r.c b/drivers/iio/dac/ad3552r.c index 16db94fef9d4..039af514adde 100644 --- a/drivers/iio/dac/ad3552r.c +++ b/drivers/iio/dac/ad3552r.c @@ -696,6 +696,6 @@ static struct spi_driver ad3552r_driver =3D { module_spi_driver(ad3552r_driver); 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charset="utf-8" Drop unused name space that somehow remained being included by the device driver. Signed-off-by: Marcelo Schmitt --- No changes since v1. drivers/iio/adc/ad4134.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 7d40c0521bb3..3c759b89d331 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -498,4 +498,3 @@ module_spi_driver(ad4134_driver); MODULE_AUTHOR("Marcelo Schmitt "); MODULE_DESCRIPTION("Analog Devices AD4134 SPI driver"); MODULE_LICENSE("GPL"); -MODULE_IMPORT_NS("IIO_AD4134"); --=20 2.53.0 From nobody Fri Sep 25 06:46:12 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 559604CDA09; Tue, 15 Sep 2026 19:13:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789499617; 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Tue, 15 Sep 2026 15:13:14 -0400 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Andy Shevchenko Subject: [PATCH v2 04/15] iio: adc: ad4134: Update include list to comply with IWYU principles Date: Tue, 15 Sep 2026 16:13:06 -0300 Message-ID: <051b56eec727b0bbb05be6a154efdf57497a95ae.1789494473.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: ApVEzS7ef5Sed-iu66o8oamXfdX3tC62 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfXxiR/qkaLD+9p zvd0bV9Jb+NGsXiStnq59nwGIN28ykEI3+ZM8Ps/iRi9nzPzq1Srh2NSpiinoiHsoFRHchqPg23 7DeBPNMiwJjIGg5XaVCpxqyVZowj3ATlCN+JzKaE+1Esb25KQecJ8tblBFeeRbE/vAgNEt7i+ma rf57DmB2f1b9l3g2thBwcbXwGJ5S8aEYc1VRTeiPbk0tGxCXXeIJc0ksPTluR41KHLKHFyNYAGg bxfm4FuYtXdXJfaOF2CnvYjwV4YLlzYL6ygN2WRxV5es03tXb23Yx77DUfl8ZMcwTom7VTeeovG 4YWu08/JaEktcKM0vqRZo+503oMRXaYiqVB/fXAQ69MYDP1Hphmyc1QfN/eIqWr3mVjXGrn00Ev 8F22Wcn7ecXr+5CrNSinyBbRp3z3da3Zrwa+Y08adoUvDjksYJfPEMD9OHbm8nmDp+drLMDtUyD d8sAqjS5jxGwC9BJfbg== X-Authority-Analysis: v=2.4 cv=V9HoQuni c=1 sm=1 tr=0 ts=6aa998d9 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=uXIjobp8t2wMuQ0fPvqm:22 a=QyXUC8HyAAAA:8 a=gAnH3GRIAAAA:8 a=gWXB6eRzw52pz-VW4roA:9 X-Proofpoint-ORIG-GUID: ApVEzS7ef5Sed-iu66o8oamXfdX3tC62 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfX/1/5X6NxX7OY xWQLmMLZTvZyYqenTGZDOCAYD5LtdG5NMCMeITksIpbUeRp/0mSeDX1iIIPqqqvseZ/KY9D3g6S XcYiBfZk3+vPRTbo6lwAjn778gWO+GIt/wDx7982rEPbf3dG4215 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150280 Content-Type: text/plain; charset="utf-8" Add includes that were missing (according to include-what-you-use tool) to comply with include what is used principles. Namely, add time64.h for USEC_PER_SEC. Remove time.h which is covered by time64.h and iio/types.h which is covered by iio/iio.h. While updating the list, organize it to follow current IIO include list convention. Reviewed-by: Andy Shevchenko Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - bits.h is implied by bitops.h so not adding that to the include list. drivers/iio/adc/ad4134.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 3c759b89d331..7400bd145d8a 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -14,18 +14,18 @@ #include #include #include -#include -#include #include #include #include #include #include -#include +#include #include #include #include =20 +#include + #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC) =20 #define AD4134_REG_READ_MASK BIT(7) --=20 2.53.0 From nobody Fri Sep 25 06:46:12 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD3124CE699; Tue, 15 Sep 2026 19:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Protect single-sample read operations from going wrong if two or more of them run concurrently. Serialize the data read operation so to avoid single-sample read requests disrupting each other. Reviewed-by: Andy Shevchenko Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Added {} to delimit scoped mutex usage context in single-sample read. - Used pahole to reduce memory holes in ad4134_state struct. drivers/iio/adc/ad4134.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 7400bd145d8a..7773b7af349b 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -98,6 +100,11 @@ struct ad4134_state { struct regmap *regmap; unsigned long sys_clk_hz; struct gpio_desc *odr_gpio; + /* + * Synchronize access to members the of driver state, and ensure + * atomicity of consecutive register access operations. + */ + struct mutex lock; int refin_mv; /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -257,7 +264,9 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, int ret; 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charset="utf-8" When AD4134 has its SPI CRC feature enabled, one extra byte (the CRC code) is sent through SPI for both ends to verify the integrity of data transfers. Though, when CRC is not enabled, SPI transfers can be shorter. Signed-off-by: Marcelo Schmitt --- No changes since v1. drivers/iio/adc/ad4134.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 7773b7af349b..b4db20b80c44 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -106,6 +106,7 @@ struct ad4134_state { */ struct mutex lock; int refin_mv; + bool crc_en; /* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. @@ -159,7 +160,7 @@ static int ad4134_reg_write(void *context, unsigned int= reg, unsigned int val) struct spi_transfer xfer =3D { .tx_buf =3D st->tx_buf, .rx_buf =3D st->rx_buf, - .len =3D AD4134_SPI_MAX_XFER_LEN, + .len =3D st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2, }; int ret; =20 @@ -169,7 +170,7 @@ static int ad4134_reg_write(void *context, unsigned int= reg, unsigned int val) if (ret) return ret; =20 - if (st->rx_buf[2] !=3D st->tx_buf[2]) + if (st->crc_en && st->rx_buf[2] !=3D st->tx_buf[2]) dev_dbg(&st->spi->dev, "reg write CRC check failed\n"); =20 return 0; @@ -217,7 +218,7 @@ static int ad4134_register_read(struct ad4134_state *st= , unsigned int reg, struct spi_transfer xfer =3D { .tx_buf =3D st->tx_buf, .rx_buf =3D st->rx_buf, - .len =3D AD4134_SPI_MAX_XFER_LEN, + .len =3D st->crc_en ? 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charset="utf-8" AD4134 supports four types of programmable digital filters that allow users to choose between different output data rates and input bandwidths. Enable basic digital filter configuration by providing a way to select which filter type is activated for each channel. Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Tidy up code for filter select support.=20 drivers/iio/adc/ad4134.c | 76 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index b4db20b80c44..30c7b1d1bc67 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -63,6 +63,9 @@ #define AD4134_PW_DOWN_CTRL_REG 0x13 #define AD4134_DEVICE_STATUS_REG 0x15 #define AD4134_ODR_VAL_INT_LSB_REG 0x16 +#define AD4134_CHAN_DIG_FILTER_SEL_REG 0x1E +#define AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(ch) (GENMASK(1, 0) << 2 * (ch)) + #define AD4134_CH3_OFFSET_MSB_REG 0x3E #define AD4134_AIN_OR_ERROR_REG 0x48 =20 @@ -80,12 +83,47 @@ #define AD4134_SPI_CRC_INIT_VALUE 0xA5 static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE]; =20 +enum ad4134_filter_type { + AD4134_WIDEBAND, + AD4134_SINC6, + AD4134_SINC3, + AD4134_SINC3_REJ60, +}; + +static const char * const ad4134_filt_names[] =3D { + [AD4134_WIDEBAND] =3D "wideband", + [AD4134_SINC6] =3D "sinc6", + [AD4134_SINC3] =3D "sinc3", + [AD4134_SINC3_REJ60] =3D "sinc3+rej60", +}; + +static int ad4134_get_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan); + +static int ad4134_set_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + unsigned int val); + +static const struct iio_enum ad4134_filter_type_enum =3D { + .items =3D ad4134_filt_names, + .num_items =3D ARRAY_SIZE(ad4134_filt_names), + .get =3D ad4134_get_filter_type, + .set =3D ad4134_set_filter_type, +}; + +static const struct iio_chan_spec_ext_info ad4134_filter_type_ext_info[] = =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ad4134_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ad4134_filter_type_enum), + { } +}; + #define AD4134_CHANNEL(_index) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ .channel =3D (_index), \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .ext_info =3D ad4134_filter_type_ext_info, \ } =20 static const struct iio_chan_spec ad4134_chan_set[] =3D { @@ -115,6 +153,44 @@ struct ad4134_state { u8 tx_buf[AD4134_SPI_MAX_XFER_LEN]; }; =20 +static int ad4134_set_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + unsigned int val) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int mask, reg_val; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + + mask =3D AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(chan->channel); + reg_val =3D field_prep(mask, val); + return regmap_update_bits(st->regmap, AD4134_CHAN_DIG_FILTER_SEL_REG, + mask, reg_val); +} + +static int ad4134_get_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int mask, reg_val; + int ret; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + ret =3D regmap_read(st->regmap, AD4134_CHAN_DIG_FILTER_SEL_REG, ®_val); + if (ret) + return ret; + + mask =3D AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(chan->channel); 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charset="utf-8" Enable users to run buffered data captures triggered by IIO trigger device. Add an IIO timestamp channel so each data scan is provided with measurement time information. Require single-read operations to be in IIO device direct access mode to prevent buffered and single-shot data captures to disrupt each other. Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Fixed IIO scan buffer size and single-read loop. - No longer memcpy() with same pointer for source and destination. - Always delimit guard()() with a blank line. drivers/iio/adc/Kconfig | 2 ++ drivers/iio/adc/ad4134.c | 75 +++++++++++++++++++++++++++++++++++----- 2 files changed, 68 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 7f90fea3d1f0..8787b2339f2c 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -125,6 +125,8 @@ config AD4134 depends on SPI select REGMAP_SPI select CRC8 + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER help Say yes here to build support for Analog Devices AD4134 SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 30c7b1d1bc67..0b6843bf8a9e 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -26,7 +26,10 @@ #include #include =20 +#include #include +#include +#include =20 #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC) =20 @@ -124,6 +127,14 @@ static const struct iio_chan_spec_ext_info ad4134_filt= er_type_ext_info[] =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ .ext_info =3D ad4134_filter_type_ext_info, \ + .scan_index =3D (_index), \ + .scan_type =3D { \ + .format =3D IIO_SCAN_FORMAT_SIGNED_INT, \ + .realbits =3D AD4134_CHAN_PRECISION_BITS, \ + .storagebits =3D 32, \ + .shift =3D 8, \ + .endianness =3D IIO_BE, \ + }, \ } =20 static const struct iio_chan_spec ad4134_chan_set[] =3D { @@ -131,6 +142,7 @@ static const struct iio_chan_spec ad4134_chan_set[] =3D= { AD4134_CHANNEL(1), AD4134_CHANNEL(2), AD4134_CHANNEL(3), + IIO_CHAN_SOFT_TIMESTAMP(4), }; =20 struct ad4134_state { @@ -149,7 +161,10 @@ struct ad4134_state { * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. */ - u8 rx_buf[AD4134_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN); + union { + u8 reg[AD4134_SPI_MAX_XFER_LEN]; + u32 scan[ARRAY_SIZE(ad4134_chan_set)]; + } rx_buf __aligned(IIO_DMA_MINALIGN); u8 tx_buf[AD4134_SPI_MAX_XFER_LEN]; }; =20 @@ -235,7 +250,7 @@ static int ad4134_reg_write(void *context, unsigned int= reg, unsigned int val) struct ad4134_state *st =3D context; struct spi_transfer xfer =3D { .tx_buf =3D st->tx_buf, - .rx_buf =3D st->rx_buf, + .rx_buf =3D st->rx_buf.reg, .len =3D st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2, }; int ret; @@ -246,7 +261,7 @@ static int ad4134_reg_write(void *context, unsigned int= reg, unsigned int val) if (ret) return ret; =20 - if (st->crc_en && st->rx_buf[2] !=3D st->tx_buf[2]) + if (st->crc_en && st->rx_buf.reg[2] !=3D st->tx_buf[2]) dev_dbg(&st->spi->dev, "reg write CRC check failed\n"); =20 return 0; @@ -269,8 +284,8 @@ static int ad4134_data_read(struct ad4134_state *st, un= signed int reg, * interface. Now we read data from all channels but keep only the bits * from the requested one. */ - for (i =3D 0; i < ARRAY_SIZE(ad4134_chan_set); i++) { - ret =3D spi_write_then_read(st->spi, NULL, 0, st->rx_buf, + for (i =3D 0; i < AD4134_NUM_CHANNELS; i++) { + ret =3D spi_write_then_read(st->spi, NULL, 0, st->rx_buf.reg, BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS)); if (ret) return ret; @@ -281,7 +296,7 @@ static int ad4134_data_read(struct ad4134_state *st, un= signed int reg, * Clock out data from all channels to avoid that. */ if (i =3D=3D AD4134_VREG_CH(reg)) - sample =3D get_unaligned_be24(st->rx_buf); + sample =3D get_unaligned_be24(st->rx_buf.reg); } *val =3D sign_extend32(sample, AD4134_CHAN_PRECISION_BITS - 1); =20 @@ -293,7 +308,7 @@ static int ad4134_register_read(struct ad4134_state *st= , unsigned int reg, { struct spi_transfer xfer =3D { .tx_buf =3D st->tx_buf, - .rx_buf =3D st->rx_buf, + .rx_buf =3D st->rx_buf.reg, .len =3D st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2, }; unsigned int inst; @@ -306,10 +321,10 @@ static int ad4134_register_read(struct ad4134_state *= st, unsigned int reg, if (ret) return ret; =20 - *val =3D st->rx_buf[1]; + *val =3D st->rx_buf.reg[1]; =20 /* Check CRC */ - if (st->crc_en && st->rx_buf[2] !=3D st->tx_buf[2]) + if (st->crc_en && st->rx_buf.reg[2] !=3D st->tx_buf[2]) dev_dbg(&st->spi->dev, "reg read CRC check failed\n"); =20 return 0; @@ -333,6 +348,37 @@ static const struct regmap_config ad4134_regmap_config= =3D { .max_register =3D AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)), }; =20 +static irqreturn_t ad4134_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int i =3D 0; + int ret; + + gpiod_set_value_cansleep(st->odr_gpio, 1); + fsleep(1); + gpiod_set_value_cansleep(st->odr_gpio, 0); + + for (unsigned int ch =3D 0; ch < AD4134_NUM_CHANNELS; ch++) { + ret =3D spi_write_then_read(st->spi, NULL, 0, &st->rx_buf.scan[ch], + BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS)); + if (ret) + goto err_out; + + if (test_bit(ch, indio_dev->active_scan_mask) && ch !=3D i) + memcpy(&st->rx_buf.scan[i++], &st->rx_buf.scan[ch], + sizeof(st->rx_buf.scan[ch])); + } + + iio_push_to_buffers_with_ts(indio_dev, &st->rx_buf.scan, + sizeof(st->rx_buf.scan), pf->timestamp); + +err_out: + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; +} + static int ad4134_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -342,6 +388,10 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, =20 switch (info) { case IIO_CHAN_INFO_RAW: { + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + guard(mutex)(&st->lock); =20 gpiod_set_value_cansleep(st->odr_gpio, 1); @@ -546,6 +596,13 @@ static int ad4134_probe(struct spi_device *spi) return dev_err_probe(dev, ret, "failed to setup minimum I/O mode\n"); =20 + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4134_trigger_handler, + NULL); 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charset="utf-8" Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations. Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Set default for adi,spi-mode property. - Added '#daisy-chained-devices' property. - Documented constraints for adi,spi-mode + #daisy-chained-devices combinat= ions. .../bindings/iio/adc/adi,ad4134.yaml | 51 ++++++++++++++++--- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index ea6d7e026419..012e09decf7a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -131,6 +131,26 @@ properties: enum: [ free-running, gated ] default: gated =20 + adi,spi-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ] + default: no-cs + description: | + This property indicates the SPI wiring configuration. + * no-cs: The datasheet calls this "minimum I/O mode". In this mode, = the CS + line is not used (tied to GND). + * 4-wire: Specifies a conventional SPI wiring configuration. + * one-channel-chain: In this mode, the DOUT0 line of one chip is con= nected + to DOUT2 of the next chip upstream in the chain. Only the data int= erface + of the upmost device in the stream is in direct connection with the + digital host. + * two-channel-chain: In this mode, the DOUT0 and DOUT1 lines of one = chip + are respectively connected to DOUT2 and DOUT3 of the next chip ups= tream + in the chain. Only the data interface of the upmost device in the = stream + is in direct connection with the digital host. + + '#daisy-chained-devices': true + required: - compatible - reg @@ -141,13 +161,30 @@ required: - clocks - clock-names =20 -oneOf: - - required: - - ldoin-supply - - required: - - avdd1v8-supply - - dvdd1v8-supply - - clkvdd-supply +allOf: + - oneOf: + - required: + - ldoin-supply + - required: + - avdd1v8-supply + - dvdd1v8-supply + - clkvdd-supply + + - oneOf: + - required: [adi,spi-mode, '#daisy-chained-devices'] + properties: + adi,spi-mode: + const: one-channel-chain + spi-rx-bus-width: + const: <1> + - required: [adi,spi-mode, '#daisy-chained-devices'] + properties: + adi,spi-mode: + const: two-channel-chain + spi-rx-bus-width: + const: <1>, <1> + - properties: + '#daisy-chained-devices': false =20 unevaluatedProperties: false =20 --=20 2.53.0 From nobody Fri Sep 25 06:46:12 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 736BC37F316; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: lZe5CNz8QYCUGGdTdYaC1F1IDeLv1gtf X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfX1PZP3xIghWKC EOUDgDKBlZLNOBj1WUJEQq17VinnawuIGvRkzeRTHcGD/sp+/QloIixEquu21TibFwodURWwHTe G53uA7Hswd+pg4EVN34FVf0F7BHjNgDzxgSxVw1BIJYVkp3CzjUj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfX2GX3qALSonMG VcyeL9QmOlx+aZ54GJVEoVzJ7a7M6ZZYoIQvEVgKFtWNn6bi7DROBePMLco9QGfmCzo8lGR04o7 OIHuwLldE6NCI6G04lctHbflmHPqZIStcqa9VLwpwF4jDaObxKmakgemK8jpgF6/iNKcNFagh1f ezDm814Gr9Etfo1TUheu+6LSomfk+I3X/s7y3cek7ycfc3+u16TMuhElA+UadWJZrA/u0ODN3R7 HrCyVX6jrw9zOMMrTZTd/e3WHYB1oJM7pv7k/W7HZYNSW3oLpOJ/kPQR+Kbgd3CYHps6RPMvga0 7soHdJUVNwFt0edKYOonRiG+uBkHoA0jmO0q4zc51Mmz8IIuVQTWrvbjU2nSoSwMqHdThC9PlHC 7H6dd8EOE910eukM00/5LS+uJxI3MjczNPdzJ5XM5Dlxmh+cDVWQuNyiAbj33BUqlHKtI33HIhb emvxxlJzEhdwzBJsMnw== X-Authority-Analysis: v=2.4 cv=HZeB3SE8 c=1 sm=1 tr=0 ts=6aa9994d cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=YjmlrVWy-zMJPE8JoxkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: lZe5CNz8QYCUGGdTdYaC1F1IDeLv1gtf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150280 The AD4134 design has two data interfaces. One interface allows register access for device configuration while the other (separate interface) provides ADC sample data. One way of handling both peripheral interfaces is to merge them into a single SPI interface by switching between register access and sample access according to device user requests. Though, such solution requires extra hardware, external to the ADC chip. The access mode switch can be done with an external multiplexer selecting either AD4134 SDO or AD4134 DOUT0 to connect to the controller. The external multiplexer becomes part of hardware requested for AD4134 device operation and thus must be provided for operating the peripheral in such merged interface schema. Still, there are alternative ways of handling the two AD4134 data interfaces so the multiplexer is not always required. Signed-off-by: Marcelo Schmitt --- New patch. Detailed reasoning for the external multiplexer usage. Before coming to the current solution, the following configuration was trie= d. +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface | | | | for register SCLK |<--------------------------| SCLK | | access CS |<--------------------------| CS | | SDI |<--------------------------| SDO | | SDO |---+ | | | | | | | | Data interface DOUT0 |---+---------------------->| SDI0 | | for ADC data DOUT1 |-------------------------->| SDI1 | | read back DOUT2 |-------------------------->| SDI2 | | DOUT3 |-------------------------->| SDI3 | | DCLK |<--------------------------| DCLK | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the da= ta line, causing register reads to fail.=20 Alternatively, we could have something like +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface | | | | for register SCLK |<--------------------------| SCLK | | access CS |<--------------------------| CS | | SDI |<--------------------------| SDO | | SDO |-------------------------->| SDI0 | | | | | | Data interface DOUT0 |-------------------------->| SDI1 | | for ADC data DOUT1 |-------------------------->| SDI2 | | read back DOUT2 |-------------------------->| SDI3 | | DOUT3 |-------------------------->| SDI4 | | DCLK |<--------------------------| DCLK | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ The downside of the above is the peripheral would need fine-grained config = of controller SDI lines to only read SDI0 for register access, and only read S= DI1, SDI2, SDI3, SDI4 for ADC sample data (currently available SPI_MULTI_LANE_MODE_STRIPE reads from all SDI lines). The currently proposed solution looks like the following +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface SCLK |<------------------------| SCLK | | for register CS |<------------------------| CS | | access SDI |<------------------------| SDO | | SDO |------->|=C2=AF=C2=AF=C2=AF=C2=AF\ | = | | | |MUX >--------->| SDI0 | | Data interface DOUT0 |------->|____/ | | | for ADC sample | ^ | | | data read DOUT1 |------------------------>| SDI1 | | DOUT2 |------------------------>| SDI2 | | DOUT3 |------------------------>| SDI3 | | DCLK |<------------------------| DCLK | | ODR |<----------------+ +->| Offload Trigger | +-----------------------+ | | | +-----------------+ | | +--| PWM1 | | +-------| PWM0 | | +-------| GPIO0 | +--------------| GPIO1 | +-----------------+ By being able to mux between AD4134 SDO and AD4134 DOUT0, the peripheral ca= n be connected to a single bus such that controllers able to read from multiple = lines will be able to gather ADC sample data from all SDI lines (SPI_MULTI_LANE_M= ODE_STRIPE). With that, AD4134 maximum data throughput can be supported with what is alr= eady available from the SPI core. See additional details on the AD4134 IIO documentation (patch 15). Yet another possibility would be to have the peripheral connecting to two b= uses. +-----------------------+ +-----------------+ | AD4134 | | SPI Controller A| | | | | | SPI interface SCLK |<--------------------------| SCLK | | for register CS |<--------------------------| CS | | access SDI |<--------------------------| SDO | | SDO |-------------------------->| SDI | | | +-----------------+ | | | SPI Controller B| | | | | | Data interface DOUT0 |-------------------------->| SDI0 | | for ADC sample DOUT1 |-------------------------->| SDI1 | | data read DOUT2 |-------------------------->| SDI2 | | DOUT3 |-------------------------->| SDI3 | | DCLK |<--------------------------| DCLK | | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ That may be a fallback option if what's currently being proposed fails to c= omply to Linux code standards. .../devicetree/bindings/iio/adc/adi,ad4134.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index 012e09decf7a..d89134ce4af6 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -104,6 +104,20 @@ properties: GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mo= de. maxItems: 1 =20 + mux-states: + description: + mux controller node to route SDO and DOUT0 signals from peripheral to + controller. + maxItems: 2 + + mux-state-names: + description: + mux state names for routing SDO and DOUT0 signals from peripheral to + controller. + items: + - const: data_read + - const: reg_access + adi,asrc-mode: $ref: /schemas/types.yaml#/definitions/string description: --=20 2.53.0 From nobody Fri Sep 25 06:46:12 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3A3D44684C; Tue, 15 Sep 2026 19:15:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789499758; cv=none; b=L+9R9HjlsKCBcREf95ht3Iocf7h3bQqZCnmJVPWseR6wrmBTn77y50d61PWmcV6y8asGJdukB3e7lFmV2QCiXbOzvzsgl7dWhAW5Lof7g2ZqIkQPyFijQae3VomH3YERh4p8bLYxeb9TJIrO3pa96LhnBr9DUKffWmzdpbzhNbQ= ARC-Message-Signature: i=1; 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Tue, 15 Sep 2026 15:15:46 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Tue, 15 Sep 2026 15:15:46 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Tue, 15 Sep 2026 15:15:46 -0400 Received: from work.maxim-ic.internal ([10.66.6.190]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 68FJFWS2028215; Tue, 15 Sep 2026 15:15:35 -0400 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v2 11/15] iio: adc: ad4134: Support SPI 4-wire mode Date: Tue, 15 Sep 2026 16:15:27 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=JekpPkKV c=1 sm=1 tr=0 ts=6aa99963 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=nUXYPE43oIPXbmalCEMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfX/8e+wtgJ1JSR vs3DnKNZxr7DXAv0MmKmCQSXjVTL6xVmdDaN+hntIFp04HBR/8PgVMuA96rN9HMpQy7FQZwJRjh T8kzOwZK7UthByPNYOs35KXMbQJnD722DP1TTrTMvwVDxLp34ZffTx8RXjQVVe2qlI2KqqL0x/q u12izSdRdqHZj2zRmRkfZq3QNJtDPScF5Inx/kuFm38Xoao9CrH0QmCTy9NiG7+tkFqSXeVhJ4k f7GFt6KZm1SnappxVijP8YqVHYul4zMw12EK1aIlLBdDKnpsZuv8P1H9561epyBbn4utDsAH5wt /sc4asiz8pt6N9jhpnlHJuccWpP54xYec3Gf8wyLmel16k2X//wDnRxqHtklLj0zHeeTIew7q1G wGOGea9uXdB4GATNPEXGnZ5o1ZDhjs1F3daf0qDn662Lk9e3ebSofDaSH0zr82zZosLB6A5xEMu clL+zVN1zyzpasLxnHg== X-Proofpoint-GUID: iCIGWbefCtVKAAV6HLtJJZfaTsNaT1xq X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI4MCBTYWx0ZWRfXyu+M11UTFybD OqDVMvlEIjYWUrUpAi8itSg302qb+ylHlK0v9fTtTDn6+eoT0LAMujxwU5tgw4OsLovb+ak0QKr kv/Pq4MN/GoE8U+k9d6YRV24bMyPkvCn+3ekGEp4EoWI/+nKa09X X-Proofpoint-ORIG-GUID: iCIGWbefCtVKAAV6HLtJJZfaTsNaT1xq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150280 AD4134 devices can be wired in a few different ways. So far, only minimum I/O mode was supported. While minimum I/O mode allows interfacing with AD4134 with a reduced number of wires, that wiring configuration is not optimal for high-throughput data acquisition. Extend AD4134 support to enable interfacing in SPI 4-wire configuration. Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Fail on unsupported adi,spi-mode. - Now properly initializing access mode mutex. - Highlighted usage of hardware external to AD4134 chip. - Added comment about mux state switch logic. - Suggestive name for auxiliary local variables. - Updated preparation flow for ad4134_data_read(). - Used pahole to reduce memory holes in ad4134_state struct. Detailed reasoning for the external multiplexer usage. Before coming to the current solution, the following configuration was trie= d. +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface | | | | for register SCLK |<--------------------------| SCLK | | access CS |<--------------------------| CS | | SDI |<--------------------------| SDO | | SDO |---+ | | | | | | | | Data interface DOUT0 |---+---------------------->| SDI0 | | for ADC data DOUT1 |-------------------------->| SDI1 | | read back DOUT2 |-------------------------->| SDI2 | | DOUT3 |-------------------------->| SDI3 | | DCLK |<--------------------------| DCLK | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the da= ta line, causing register reads to fail.=20 Alternatively, we could have something like +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface | | | | for register SCLK |<--------------------------| SCLK | | access CS |<--------------------------| CS | | SDI |<--------------------------| SDO | | SDO |-------------------------->| SDI0 | | | | | | Data interface DOUT0 |-------------------------->| SDI1 | | for ADC data DOUT1 |-------------------------->| SDI2 | | read back DOUT2 |-------------------------->| SDI3 | | DOUT3 |-------------------------->| SDI4 | | DCLK |<--------------------------| DCLK | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ The downside of the above is the peripheral would need fine-grained config = of controller SDI lines to only read SDI0 for register access, and only read S= DI1, SDI2, SDI3, SDI4 for ADC sample data (currently available SPI_MULTI_LANE_MODE_STRIPE reads from all SDI lines). The currently proposed solution looks like the following +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface SCLK |<------------------------| SCLK | | for register CS |<------------------------| CS | | access SDI |<------------------------| SDO | | SDO |------->|=C2=AF=C2=AF=C2=AF=C2=AF\ | = | | | |MUX >--------->| SDI0 | | Data interface DOUT0 |------->|____/ | | | for ADC sample | ^ | | | data read DOUT1 |------------------------>| SDI1 | | DOUT2 |------------------------>| SDI2 | | DOUT3 |------------------------>| SDI3 | | DCLK |<------------------------| DCLK | | ODR |<----------------+ +->| Offload Trigger | +-----------------------+ | | | +-----------------+ | | +--| PWM1 | | +-------| PWM0 | | +-------| GPIO0 | +--------------| GPIO1 | +-----------------+ By being able to mux between AD4134 SDO and AD4134 DOUT0, the peripheral ca= n be connected to a single bus such that controllers able to read from multiple = lines will be able to gather ADC sample data from all SDI lines (SPI_MULTI_LANE_M= ODE_STRIPE). With that, AD4134 maximum data throughput can be supported with what is alr= eady available from the SPI core. See additional details on the AD4134 IIO documentation (patch 15). Yet another possibility would be to have the peripheral connecting to two b= uses. +-----------------------+ +-----------------+ | AD4134 | | SPI Controller A| | | | | | SPI interface SCLK |<--------------------------| SCLK | | for register CS |<--------------------------| CS | | access SDI |<--------------------------| SDO | | SDO |-------------------------->| SDI | | | +-----------------+ | | | SPI Controller B| | | | | | Data interface DOUT0 |-------------------------->| SDI0 | | for ADC sample DOUT1 |-------------------------->| SDI1 | | data read DOUT2 |-------------------------->| SDI2 | | DOUT3 |-------------------------->| SDI3 | | DCLK |<--------------------------| DCLK | | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ That may be a fallback option if what's currently being proposed fails to c= omply to Linux code standards. drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4134.c | 194 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 190 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 8787b2339f2c..3b0216e75678 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -127,6 +127,7 @@ config AD4134 select CRC8 select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select MULTIPLEXER help Say yes here to build support for Analog Devices AD4134 SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 0b6843bf8a9e..cc6bc325f6ee 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -72,6 +74,9 @@ #define AD4134_CH3_OFFSET_MSB_REG 0x3E #define AD4134_AIN_OR_ERROR_REG 0x48 =20 +#define AD4134_SDO_INPUT 0 +#define AD4134_DOUT0_INPUT 1 + /* * AD4134 register map ends at address 0x48 and there is no register for * retrieving ADC sample data. Though, to make use of Linux regmap API both @@ -86,6 +91,17 @@ #define AD4134_SPI_CRC_INIT_VALUE 0xA5 static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE]; =20 +enum ad4134_spi_mode { + AD4134_SPI_MODE_NO_CS, /* datasheet calls this "minimum I/O mode" */ + AD4134_SPI_MODE_4_WIRE, +}; + +/* maps adi,spi-mode property value to enum */ +static const char * const ad4134_spi_modes[] =3D { + [AD4134_SPI_MODE_NO_CS] =3D "no-cs", + [AD4134_SPI_MODE_4_WIRE] =3D "4-wire", +}; + enum ad4134_filter_type { AD4134_WIDEBAND, AD4134_SINC6, @@ -155,6 +171,12 @@ struct ad4134_state { * atomicity of consecutive register access operations. */ struct mutex lock; + /* + * Ensure atomicity of access mode switch operations. + */ + struct mutex access_mode_lock; + struct mux_state *mux_st[2]; /* For external multiplexer control */ + enum ad4134_spi_mode spi_mode; int refin_mv; bool crc_en; /* @@ -230,6 +252,85 @@ static const struct regmap_access_table ad4134_regmap_= wr_table =3D { .n_yes_ranges =3D ARRAY_SIZE(ad4134_regmap_wr_range), }; =20 +/* + * This function controls a multiplexer OUTSIDE OF AD4134 SILICON. + * When AD4134 SDO and DOUT0 pins are multiplexed, this function changes t= he + * multiplexer state to route SDO to the SPI controller. See AD4134 IIO + * documentation for details. + */ +static int ad4134_set_register_access(struct ad4134_state *st) +{ + int ret; + + guard(mutex)(&st->access_mode_lock); + + st->spi->mode =3D SPI_MODE_0; + ret =3D spi_setup(st->spi); + if (ret) + return ret; + + ret =3D mux_state_deselect(st->mux_st[AD4134_DOUT0_INPUT]); + if (ret) + dev_err(&st->spi->dev, "error on DOUT0 deselect: %d\n", ret); + + /* + * Try to update the multiplexer state to route SDO to the SPI + * controller. If the SDO mux state is BUSY (i.e. locked), that means + * the desired state is already selected and we should not block here. + */ + ret =3D mux_state_try_select(st->mux_st[AD4134_SDO_INPUT]); + if (ret && ret !=3D -EBUSY) + return ret; + + return 0; +} + +/* + * This function controls a multiplexer OUTSIDE OF AD4134 SILICON. + * When AD4134 SDO and DOUT0 pins are multiplexed, this function changes t= he + * multiplexer state to route DOUT0 to the SPI controller. On failure, fall + * back to routing SDO to the controller and return an errno. See AD4134 I= IO + * documentation for details. + */ +static int ad4134_set_sample_access(struct ad4134_state *st) +{ + struct device *dev =3D &st->spi->dev; + int mux_state_ret, ret; + + guard(mutex)(&st->access_mode_lock); + + ret =3D mux_state_deselect(st->mux_st[AD4134_SDO_INPUT]); + if (ret) + dev_err(&st->spi->dev, "error on SDO deselect: %d\n", ret); + + ret =3D mux_state_try_select(st->mux_st[AD4134_DOUT0_INPUT]); + if (ret) { + dev_err(&st->spi->dev, "error on DOUT0 select: %d\n", ret); + return mux_state_select(st->mux_st[AD4134_SDO_INPUT]); + } + + /* + * Data output on the DOUT lines is sampled on the falling edge + * (SPI mode 1). + */ + st->spi->mode =3D SPI_MODE_1; + ret =3D spi_setup(st->spi); + if (ret) { + dev_err(&st->spi->dev, "failed to setup SPI mode 1: %d\n", ret); + mux_state_ret =3D mux_state_deselect(st->mux_st[AD4134_DOUT0_INPUT]); + if (mux_state_ret) + dev_err(dev, "error on DOUT0 deselect: %d\n", mux_state_ret); + + mux_state_ret =3D mux_state_select(st->mux_st[AD4134_SDO_INPUT]); + if (mux_state_ret) + dev_err(dev, "error on SDO select: %d\n", mux_state_ret); + + return ret; + } + + return 0; +} + static int ad4134_calc_spi_crc(u8 inst, u8 data) { u8 buf[] =3D { inst, data }; @@ -333,9 +434,24 @@ static int ad4134_register_read(struct ad4134_state *s= t, unsigned int reg, static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *= val) { struct ad4134_state *st =3D context; + int ret, access_ret; =20 - if (reg >=3D AD4134_CH_VREG(0)) - return ad4134_data_read(st, reg, val); + if (reg >=3D AD4134_CH_VREG(0)) { + if (st->spi_mode =3D=3D AD4134_SPI_MODE_NO_CS) + return ad4134_data_read(st, reg, val); + + ret =3D ad4134_set_sample_access(st); + if (ret) + return ret; + + ret =3D ad4134_data_read(st, reg, val); + + access_ret =3D ad4134_set_register_access(st); + if (access_ret) + dev_err(&st->spi->dev, "access mode error: %d\n", access_ret); + + return ret; + } =20 return ad4134_register_read(st, reg, val); } @@ -379,6 +495,21 @@ static irqreturn_t ad4134_trigger_handler(int irq, voi= d *p) return IRQ_HANDLED; } =20 +static int ad4134_buffer_postenable(struct iio_dev *indio_dev) +{ + return ad4134_set_sample_access(iio_priv(indio_dev)); +} + +static int ad4134_buffer_predisable(struct iio_dev *indio_dev) +{ + return ad4134_set_register_access(iio_priv(indio_dev)); +} + +static const struct iio_buffer_setup_ops ad4134_buffer_setup_ops =3D { + .postenable =3D &ad4134_buffer_postenable, + .predisable =3D &ad4134_buffer_predisable, +}; + static int ad4134_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -586,15 +717,68 @@ static int ad4134_probe(struct spi_device *spi) if (ret) return ret; =20 + ret =3D devm_mutex_init(dev, &st->access_mode_lock); + if (ret) + return ret; + st->regmap =3D devm_regmap_init(dev, NULL, st, &ad4134_regmap_config); if (IS_ERR(st->regmap)) return dev_err_probe(dev, PTR_ERR(st->regmap), "failed to initialize regmap"); =20 - ret =3D ad4134_min_io_mode_setup(st); - if (ret) + ret =3D device_property_match_property_string(dev, "adi,spi-mode", + ad4134_spi_modes, + ARRAY_SIZE(ad4134_spi_modes)); + if (ret =3D=3D -EINVAL) { + /* Default to no-cs mode if adi,spi-mode is not specified */ + if (!device_property_present(dev, "adi,spi-mode")) + st->spi_mode =3D AD4134_SPI_MODE_NO_CS; + else + return dev_err_probe(dev, ret, + "unsupported adi,spi-mode\n"); + } else if (ret < 0) { return dev_err_probe(dev, ret, - "failed to setup minimum I/O mode\n"); + "getting adi,spi-mode property failed\n"); + } else { + st->spi_mode =3D ret; + } + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_NO_CS) { + /* + * The support hardware for AD4134 may have a multiplexer for + * selecting between AD4134 SDO and AD4134 DOUT0. If that mux + * is set but the user still wants to run AD4134 in minimum I/O + * mode, then DOUT0 is not used and the multiplexer OUTSIDE OF + * AD4134 SILICON must be set to select AD4134 SDO. See AD4134 + * IIO documentation for details. + */ + st->mux_st[AD4134_SDO_INPUT] =3D + devm_mux_state_get_optional_selected(dev, "reg_access"); + if (IS_ERR(st->mux_st[AD4134_SDO_INPUT])) + return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_SDO_INPUT]), + "failed to get reg_access mux-state\n"); + + ret =3D ad4134_min_io_mode_setup(st); + if (ret) + return dev_err_probe(dev, ret, + "failed to setup minimum I/O mode\n"); + } else { + /* + * This controls a multiplexer OUTSIDE OF AD4134 SILICON. + * See AD4134 IIO documentation for details. + */ + st->mux_st[AD4134_SDO_INPUT] =3D devm_mux_state_get_selected(dev, "reg_a= ccess"); + if (IS_ERR(st->mux_st[AD4134_SDO_INPUT])) + return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_SDO_INPUT]), + "failed to get reg_access mux-state\n"); + + st->mux_st[AD4134_DOUT0_INPUT] =3D devm_mux_state_get(dev, "data_read"); + if (IS_ERR(st->mux_st[AD4134_DOUT0_INPUT])) + return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_DOUT0_INPUT]), + "failed to get data_read mux-state\n"); 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charset="utf-8" Advanced setups may connect a PWM signal to AD4134 ODR pin for faster output data rates. Acked-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- No changes since v1. Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index d89134ce4af6..ad67d1cdacec 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -104,6 +104,10 @@ properties: GPIO connected to ODR pin. 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charset="utf-8" Add device tree example for AD4134 operation in 4-wire SPI mode with 4 lines to transfer data samples to the host controller. Signed-off-by: Marcelo Schmitt --- No changes since v1. .../bindings/iio/adc/adi,ad4134.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index ad67d1cdacec..133996917ee2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -243,4 +243,46 @@ examples: =20 }; }; + - | + #include + + ad4134_sdo_dout0_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&gpio0 100 GPIO_ACTIVE_HIGH>; + }; + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4134"; + reg =3D <0>; + + spi-max-frequency =3D <1000000>; + spi-rx-bus-width =3D <1>, <1>, <1>, <1>; /* 4 lanes of 1 bit e= ach */ + + pwms =3D <&ad4134_odr_generator 1 1000000 0>; + reset-gpios =3D <&gpio0 86 GPIO_ACTIVE_LOW>; + odr-gpios =3D <&gpio0 87 GPIO_ACTIVE_HIGH>; + powerdown-gpios =3D <&gpio0 88 GPIO_ACTIVE_LOW>; + + clocks =3D <&sys_clk>; + clock-names =3D "clkin"; + + avdd5-supply =3D <&avdd5>; + dvdd5-supply =3D <&dvdd5>; + iovdd-supply =3D <&iovdd>; + refin-supply =3D <&refin>; + avdd1v8-supply =3D <&avdd1v8>; + dvdd1v8-supply =3D <&dvdd1v8>; + clkvdd-supply =3D <&clkvdd>; + + mux-states =3D <&ad4134_sdo_dout0_mux 0>, <&ad4134_sdo_dout0_m= ux 1>; + mux-state-names =3D "data_read", "reg_access"; + + adi,spi-mode =3D "4-wire"; + }; + }; ... --=20 2.53.0 From nobody Fri Sep 25 06:46:12 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 511064CB8C2; Tue, 15 Sep 2026 19:16:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789499813; 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charset="utf-8" Make use of SPI transfer offloading to speed up data capture, enabling data acquisition at faster sample rates (up to 1.496 MSPS). Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - Error out on min I/O + offload config (currently not being supported). - Improved PWM setup readability, update allowed scan_mask codestyle. - Preserved triggered buffer setup callbacks. - Used pahole to reduce memory holes in ad4134_state struct. We can't drop target_ns and use odr_wf.duty_length_ns directly because pwm_..._waveform...() may round waveform parameters. Same reasoning applies= to offload_offset_ns. drivers/iio/adc/Kconfig | 5 + drivers/iio/adc/ad4134.c | 387 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 383 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3b0216e75678..12ef9a053f04 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -123,9 +123,14 @@ config AD4130 config AD4134 tristate "Analog Devices AD4134 ADC Driver" depends on SPI + depends on PWM select REGMAP_SPI + select SPI_OFFLOAD + select SPI_OFFLOAD_TRIGGER_PWM select CRC8 select IIO_BUFFER + select IIO_BUFFER_DMA + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER select MULTIPLEXER help diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index cc6bc325f6ee..94d979c61501 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -19,9 +20,12 @@ #include #include #include +#include #include #include #include +#include +#include #include #include #include @@ -29,11 +33,16 @@ #include =20 #include +#include +#include #include #include #include =20 #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC) +#define AD4134_DCLK_RISING_OFFSET_NS 8 +#define AD4134_MIN_ODR_FREQ_HZ 10 +#define AD4134_MAX_ODR_FREQ_HZ (1496 * HZ_PER_KHZ) =20 #define AD4134_REG_READ_MASK BIT(7) #define AD4134_SPI_MAX_XFER_LEN 3 @@ -64,6 +73,7 @@ #define AD4134_DIG_IF_CFG_REG 0x12 #define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0) #define AD4134_DATA_FORMAT_SINGLE_CH_MODE 0x0 +#define AD4134_DATA_FORMAT_QUAD_CH_PARALLEL 0x2 =20 #define AD4134_PW_DOWN_CTRL_REG 0x13 #define AD4134_DEVICE_STATUS_REG 0x15 @@ -116,6 +126,10 @@ static const char * const ad4134_filt_names[] =3D { [AD4134_SINC3_REJ60] =3D "sinc3+rej60", }; =20 +static const int ad4134_max_samp_freq_range_Hz[3] =3D { + AD4134_MIN_ODR_FREQ_HZ, 1, AD4134_MAX_ODR_FREQ_HZ, +}; + static int ad4134_get_filter_type(struct iio_dev *indio_dev, struct iio_chan_spec const *chan); =20 @@ -161,6 +175,39 @@ static const struct iio_chan_spec ad4134_chan_set[] = =3D { IIO_CHAN_SOFT_TIMESTAMP(4), }; =20 +/* + * Hardcoded 32-bit storagebits and CPU endianness because the currently + * available HDL only supports that configuration. + */ +#define AD4134_OFFLOAD_CHANNEL(_index) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (_index), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .ext_info =3D ad4134_filter_type_ext_info, \ + .scan_index =3D (_index), \ + .scan_type =3D { \ + .format =3D IIO_SCAN_FORMAT_SIGNED_INT, \ + .realbits =3D AD4134_CHAN_PRECISION_BITS, \ + .storagebits =3D 32, \ + .endianness =3D IIO_CPU, \ + }, \ +} + +/* + * It's not possible for software to record when offloaded SPI transfers r= un so + * no additional timestamp channel is added. + */ +static const struct iio_chan_spec ad4134_offload_chan_set[] =3D { + AD4134_OFFLOAD_CHANNEL(0), + AD4134_OFFLOAD_CHANNEL(1), + AD4134_OFFLOAD_CHANNEL(2), + AD4134_OFFLOAD_CHANNEL(3), +}; + struct ad4134_state { struct spi_device *spi; struct regmap *regmap; @@ -178,6 +225,14 @@ struct ad4134_state { struct mux_state *mux_st[2]; /* For external multiplexer control */ enum ad4134_spi_mode spi_mode; int refin_mv; + struct spi_message msg; + struct spi_transfer xfers; + struct spi_offload_trigger_config offload_trigger_config; + struct spi_offload_trigger *offload_trigger; + struct spi_offload *offload; + struct pwm_waveform odr_wf; + struct pwm_device *odr_pwm; + unsigned int odr_hz; bool crc_en; /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -464,6 +519,91 @@ static const struct regmap_config ad4134_regmap_config= =3D { .max_register =3D AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)), }; =20 +static int ad4134_update_conversion_rate(struct ad4134_state *st, + unsigned int freq_Hz) +{ + struct spi_offload_trigger_config config =3D st->offload_trigger_config; + struct pwm_waveform odr_wf =3D { }; + u64 offload_period_ns; + u64 offload_offset_ns; + u64 odr_high_time_ns; + unsigned int count; + u64 target_ns; + int ret; + + if (!in_range(freq_Hz, AD4134_MIN_ODR_FREQ_HZ, AD4134_MAX_ODR_FREQ_HZ)) + return -ERANGE; + + odr_wf.period_length_ns =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq_Hz); + /* + * Set the PWM duty cycle to keep ODR high for at least minimum required + * time. If the rounded PWM's value is less than the minimum required, + * increase the target value by 10 and attempt to round the waveform + * again, until the minimum (or try count limit) is reached. + */ + odr_high_time_ns =3D div64_ul(6ULL * NSEC_PER_SEC, st->sys_clk_hz); + target_ns =3D 0; + count =3D 100; + do { + target_ns +=3D 10; /* Increment by PWM duty cycle period */ + odr_wf.duty_length_ns =3D target_ns; + ret =3D pwm_round_waveform_might_sleep(st->odr_pwm, &odr_wf); + if (ret) + return ret; + } while (count-- && odr_wf.duty_length_ns < odr_high_time_ns); + + /* Check the minimum ODR high time is met */ + if (odr_wf.duty_length_ns < odr_high_time_ns) + return -EDOM; + + if (odr_wf.period_length_ns < 2 * odr_high_time_ns) + return -EDOM; + + /* + * Configure SPI offload PWM trigger. + * For gated DCLK, the minimum required time between ODR rising edge + * and DCLK rising edge is the sum of ODR high time and ODR falling + * edge to DCLK rising edge time. Delay the offload trigger for at least + * that amount of time so the ADC sample data will be available when the + * SPI transfer begin. + * + * Use the same period as ODR PWM to avoid timing issues. + * Convert back from period to frequency for the SPI offload API. + */ + offload_period_ns =3D odr_wf.period_length_ns; + config.periodic.frequency_hz =3D DIV_ROUND_UP_ULL(HZ_PER_GHZ, offload_per= iod_ns); + offload_offset_ns =3D odr_high_time_ns + AD4134_DCLK_RISING_OFFSET_NS; + count =3D 100; + do { + config.periodic.offset_ns =3D offload_offset_ns; + ret =3D spi_offload_trigger_validate(st->offload_trigger, &config); + if (ret) + return ret; + + offload_offset_ns +=3D 10; + } while (count-- && config.periodic.offset_ns < odr_high_time_ns + + AD4134_DCLK_RISING_OFFSET_NS); + + /* Check the minimum ODR to DCLK delay is met */ + if (config.periodic.offset_ns < odr_high_time_ns + AD4134_DCLK_RISING_OFF= SET_NS) + return -EDOM; + + /* Check the PWM periods remain the same */ + offload_period_ns =3D DIV_ROUND_UP_ULL(HZ_PER_GHZ, config.periodic.freque= ncy_hz); + if (odr_wf.period_length_ns !=3D offload_period_ns) + return -EDOM; + + ret =3D pwm_set_waveform_might_sleep(st->odr_pwm, &odr_wf, false); + if (ret) + return ret; + + st->offload_trigger_config =3D config; + st->odr_wf =3D odr_wf; + st->odr_hz =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, odr_wf.period_length_ns); + + return 0; +} + static irqreturn_t ad4134_trigger_handler(int irq, void *p) { struct iio_poll_func *pf =3D p; @@ -549,6 +689,44 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, *val2 =3D AD4134_CHAN_PRECISION_BITS - 1; =20 return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D st->odr_hz; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad4134_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals =3D (int *)ad4134_max_samp_freq_range_Hz; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + default: + return -EINVAL; + } +} + +static int ad4134_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4134_update_conversion_rate(st, val); default: return -EINVAL; } @@ -600,6 +778,176 @@ static const struct iio_info ad4134_info =3D { .debugfs_reg_access =3D ad4134_debugfs_reg_access, }; =20 +static const struct iio_info ad4134_offload_info =3D { + .read_raw =3D ad4134_read_raw, + .read_avail =3D ad4134_read_avail, + .write_raw =3D ad4134_write_raw, + .debugfs_reg_access =3D ad4134_debugfs_reg_access, +}; + +static void ad4134_prepare_offload_msg(struct iio_dev *indio_dev) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int base_len =3D roundup_pow_of_two(BITS_TO_BYTES(AD4134_CHAN_PR= ECISION_BITS)); + unsigned int bpw =3D AD4134_CHAN_PRECISION_BITS; + + st->xfers.cs_off =3D 1; + st->xfers.bits_per_word =3D bpw; + st->xfers.len =3D base_len * st->spi->num_rx_lanes; + if (st->spi->num_rx_lanes > 1) + st->xfers.multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + + st->xfers.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + + spi_message_init_with_transfers(&st->msg, &st->xfers, 1); +} + +static int ad4134_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + int ret, access_ret; + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_4_WIRE) { + ret =3D ad4134_set_sample_access(st); + if (ret) + return ret; + } + + ad4134_prepare_offload_msg(indio_dev); + st->msg.offload =3D st->offload; + ret =3D spi_optimize_message(st->spi, &st->msg); + if (ret) + goto out_set_register_input; + + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &st->offload_trigger_config); + if (ret) + goto out_unoptimize; + + return 0; + +out_unoptimize: + spi_unoptimize_message(&st->msg); + +out_set_register_input: + access_ret =3D ad4134_set_register_access(st); + if (access_ret) + dev_err(&st->spi->dev, "reg input select error: %d\n", access_ret); + + return ret; +} + +static int ad4134_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + int ret =3D 0; + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_4_WIRE) + ret =3D ad4134_set_register_access(st); + + spi_unoptimize_message(&st->msg); + + return ret; +} + +static const struct iio_buffer_setup_ops ad4134_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4134_offload_buffer_postenable, + .predisable =3D &ad4134_offload_buffer_predisable, +}; + +static int ad4134_pwm_get(struct ad4134_state *st) +{ + struct device *dev =3D &st->spi->dev; + + st->odr_pwm =3D devm_pwm_get(dev, NULL); + if (IS_ERR(st->odr_pwm)) + return dev_err_probe(dev, PTR_ERR(st->odr_pwm), + "failed to get ODR PWM\n"); + + return 0; +} + +static const struct spi_offload_config ad4134_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + +static int ad4134_offload_buffer_setup(struct iio_dev *indio_dev, struct s= pi_device *spi) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + struct device *dev =3D &spi->dev; + struct dma_chan *rx_dma; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + + st->offload_trigger_config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + +/* The chip converts and outputs all 4 channels on each sample request */ +static const unsigned long ad4134_scan_masks[] =3D { + BIT(3) | BIT(2) | BIT(1) | BIT(0), + 0 +}; + +static int ad4134_offload_setup(struct iio_dev *indio_dev, struct ad4134_s= tate *st) +{ + struct device *dev =3D &st->spi->dev; + int ret; + + ret =3D ad4134_pwm_get(st); + if (ret) + return ret; + + ret =3D ad4134_offload_buffer_setup(indio_dev, st->spi); + if (ret) + return ret; + + /* + * Start with a sampling rate slower than 374 kSPS because that is the + * maximum rate supported with wideband filter (default on power up). + */ + st->odr_hz =3D 250 * HZ_PER_KHZ; + ret =3D ad4134_update_conversion_rate(st, st->odr_hz); + if (ret) + return dev_err_probe(dev, ret, "failed to set sampling freq\n"); + + indio_dev->setup_ops =3D &ad4134_offload_buffer_setup_ops; + indio_dev->available_scan_masks =3D ad4134_scan_masks; + + switch (st->spi->num_rx_lanes) { + case 1: + return regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG, + AD4134_DIF_IF_CFG_FORMAT_MASK, + FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK, + AD4134_DATA_FORMAT_SINGLE_CH_MODE)); + case 4: + return regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG, + AD4134_DIF_IF_CFG_FORMAT_MASK, + FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK, + AD4134_DATA_FORMAT_QUAD_CH_PARALLEL)); + default: + return dev_err_probe(dev, -EINVAL, + "unsupported number of spi-rx-bus-width elements: %d\n", + st->spi->num_rx_lanes); + } + + return 0; +} + static const char * const ad4143_required_regulators[] =3D { "avdd5", "dvdd5", "iovdd", }; @@ -693,10 +1041,7 @@ static int ad4134_probe(struct spi_device *spi) st->spi =3D spi; =20 indio_dev->name =3D "ad4134"; - indio_dev->channels =3D ad4134_chan_set; - indio_dev->num_channels =3D ARRAY_SIZE(ad4134_chan_set); indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->info =3D &ad4134_info; =20 ret =3D ad4134_regulator_setup(st); if (ret) @@ -780,12 +1125,35 @@ static int ad4134_probe(struct spi_device *spi) indio_dev->setup_ops =3D &ad4134_buffer_setup_ops; } =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - ad4134_trigger_handler, - NULL); - if (ret) - return ret; + st->offload =3D devm_spi_offload_get(dev, spi, &ad4134_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + /* Fall back to low speed usage when no SPI offload is available. */ + if (ret =3D=3D -ENODEV) { + indio_dev->info =3D &ad4134_info; + indio_dev->channels =3D ad4134_chan_set; + indio_dev->num_channels =3D ARRAY_SIZE(ad4134_chan_set); + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4134_trigger_handler, + st->spi_mode !=3D AD4134_SPI_MODE_NO_CS ? + &ad4134_buffer_setup_ops : NULL); + if (ret) + return ret; + } else if (ret) { + return dev_err_probe(dev, ret, "failed to get offload\n"); + } else { + if (st->spi_mode =3D=3D AD4134_SPI_MODE_NO_CS) + return dev_err_probe(dev, -EPROTONOSUPPORT, + "Unsupported min I/O + offload config\n"); + + indio_dev->info =3D &ad4134_offload_info; + indio_dev->channels =3D ad4134_offload_chan_set; + indio_dev->num_channels =3D ARRAY_SIZE(ad4134_offload_chan_set); + ret =3D ad4134_offload_setup(indio_dev, st); + if (ret) + return dev_err_probe(dev, ret, + "failed to setup SPI offload\n"); + } =20 /* Bump precision to 24-bit */ ret =3D regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG, @@ -831,3 +1199,4 @@ module_spi_driver(ad4134_driver); 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Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2: - More accurate multiplexer control signal portrayal in connection diagrams. Documentation/iio/ad4134.rst | 130 +++++++++++++++++++++++++++++++++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 132 insertions(+) create mode 100644 Documentation/iio/ad4134.rst diff --git a/Documentation/iio/ad4134.rst b/Documentation/iio/ad4134.rst new file mode 100644 index 000000000000..7910cd665ad6 --- /dev/null +++ b/Documentation/iio/ad4134.rst @@ -0,0 +1,130 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD4134 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Device driver for Analog Devices Inc. AD4134 and similar ADCs. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* `AD4134 `_ +* `AD7134 `_ + +Wiring connections +------------------ + +AD4134 and similar ADCs can operate in a few different wiring configuratio= ns. +Because AD4134 also supports control modes other than through SPI protocol, +the following pins must be statically set for all of the wiring modes desc= ribed +below. + ++----------------------------+----------------------+--------------------+ +| Pin Function | Level | Description | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| PIN/SPI | High | SPI control mode | ++----------------------------+----------------------+--------------------+ +| MODE | Low | ASRC slave mode | ++----------------------------+----------------------+--------------------+ +| DEC0/DCLKI | Low | DCLK input | ++----------------------------+----------------------+--------------------+ +| DEC1/DCLKMODE | Low | Gated DCLK | ++----------------------------+----------------------+--------------------+ + +Minimum I/O mode +^^^^^^^^^^^^^^^^ + +The minimum I/O mode wiring allows AD4134 register and data access with the +conventional set of SPI bus lines. In this mode, the peripheral CS pin mus= t be +tied to GND. A possible connection schema that sets AD4134 digital interfa= ce for +minimum I/O mode is:: + + +------------+ +-------------+ + | AD4134 | | SPI | + | | | Controller | + | DCLK |<--+ | | + | SCLK |<--+---- | SCLK | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | ODR |<--------| GPIO | + | CS |----+ | | + +------------+ | +-------------+ + V + GND + +Set ``adi,spi-mode =3D "no-cs"`` in device tree to indicate the device is +connected in minimum I/O wiring configuration. + +SPI 4-wire mode - single lane +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The conventional SPI 4-wire configuration except a multiplexer is used to +select between SDO (for register data) and DOUT0 (for ADC sample data).:: + + +-----------------------+ +-----------------+ + | AD4134 | | SPI Controller | + | | | | + | SPI interface | | | + | for register SCLK |<------------------------| SCLK | + | access CS |<------------------------| CS | + | SDI |<------------------------| SDO | + | SDO |------->|=C2=AF=C2=AF=C2=AF=C2=AF\ | = | + | Data interface | |MUX >--------->| SDI | + | for ADC sample DOUT0 |------->|____/ | | + | data read | ^ | | + | | | | | + | DCLK |<------------------------| DCLK | + | ODR |<----------------+ +->| Offload Trigger | + +-----------------------+ | | | +-----------------+ + | | +--| PWM1 | + | +-------| PWM0 | + | +-------| GPIO0 | + +--------------| GPIO1 | + +-----------------+ + +Set ``adi,spi-mode =3D "4-wire"`` in device tree to indicate the device is +connected in SPI 4-wire configuration. + +For SPI offload operation, a PWM is connected to the ADC ODR pin. The ``pw= ms`` +firmware property specifies the PWM that is connected to the ADC. The SPI +offload will have a ``trigger-sources`` property to indicate the SPI offlo= ad +(PWM) trigger source. + +To achieve high sample rates while meeting ADC timing requirements, an off= set +must be added between the rising edges of PWM0 and PWM1 to delay the SPI +transfer until ADC sample data is available. This requires a specialized P= WM +controller that can provide such an offset. The `AD4134-FMC HDL project`_= , for +example, can be configured to sample AD4134 at high speed sample rates. + +.. _AD4134-FMC HDL project: https://analogdevicesinc.github.io/hdl/project= s/ad4134_fmc/index.html + +SPI 4-wire mode - multi-lane +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Maximum throughput rate can be achieved by reading 4 input lines simultane= ously.:: + + +-----------------------+ +-----------------+ + | AD4134 | | SPI Controller | + | | | | + | SPI interface SCLK |<------------------------| SCLK | + | for register CS |<------------------------| CS | + | access SDI |<------------------------| SDO | + | SDO |------->|=C2=AF=C2=AF=C2=AF=C2=AF\ | = | + | | |MUX >--------->| SDI0 | + | Data interface DOUT0 |------->|____/ | | + | for ADC sample | ^ | | + | data read DOUT1 |------------------------>| SDI1 | + | DOUT2 |------------------------>| SDI2 | + | DOUT3 |------------------------>| SDI3 | + | DCLK |<------------------------| DCLK | + | ODR |<----------------+ +->| Offload Trigger | + +-----------------------+ | | | +-----------------+ + | | +--| PWM1 | + | +-------| PWM0 | + | +-------| GPIO0 | + +--------------| GPIO1 | + +-----------------+ + +Each of SDI0 to SDI3 connect to a different SPI controller deserializer +(``spi-rx-bus-width =3D <1>, <1>, <1>, <1>``). diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index b02b879b053a..e4ec8a05dded 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers ad4000 ad4030 ad4062 + ad4134 ad4691 ad4695 ad7191 diff --git a/MAINTAINERS b/MAINTAINERS index 214aeee7642e..ca2c8667cdfb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1533,6 +1533,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +F: Documentation/iio/ad4134.rst F: drivers/iio/adc/ad4134.c =20 ANALOG DEVICES INC AD4170-4 DRIVER --=20 2.53.0