From nobody Fri Sep 25 12:03:20 2026 Received: from out198-3.us.a.mail.aliyun.com (out198-3.us.a.mail.aliyun.com [47.90.198.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1A6538C40C; Sun, 13 Sep 2026 06:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281861; cv=none; b=oaHZAdLFsX47KPwZ1Kk4W9WhqtWSQpJOnlKf4j+0eSqkO/obGsZShTFpEcd9Q1DtFTBk217MxLq6AjGrYJxjY1F53GHQhsrJmy8r4C4QDQM12Zqh+uDOw60uYnhZuue3RNC+0UECWf5GJuCAJ3wN8ZfzZY6cc9+wcc9jStVHNGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281861; c=relaxed/simple; bh=wAfoApbiKg4FZ0HY+eTjuhQKVqQcrN2b3NJl72iRBF8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XccSIMQ5CBLC4AANytC11hl47icBqtpHsPPsr8fpHCL+mxFrO3gE16gwpM706PzOYbyBEIAKxN3q8rbV+R+ldu61xB4EJGr7akpL/1ppaKvdxvPyo2242OrpLhWIDFHgR/w1qPob0oFlh2EKhQ3v8SjADscKC3Rsq1d2kJcOzJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2039089|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.0302074-0.000243454-0.969549;FP=17183902916247750647|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033022149254;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.jCORvlD_1789281834; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvlD_1789281834 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:43:55 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/8] KVM: x86: Provide INVLPG linear address to intercept handlers Date: Sun, 13 Sep 2026 14:43:41 +0800 Message-ID: X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" INVLPG's memory operand is decoded with NoAccess, and thus src_val does not contain the operand address. Intercept handlers therefore cannot construct exit state that reports the linear address from the existing x86_instruction_info fields. Add get_invlpg_linear_addr() to compute the address through __linearize(), using the same flags as em_invlpg(), and pass the result through x86_instruction_info. Signed-off-by: Tina Zhang --- arch/x86/kvm/emulate.c | 18 ++++++++++++++++++ arch/x86/kvm/kvm_emulate.h | 1 + 2 files changed, 19 insertions(+) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 8071b372d233..1dfece6af81e 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -410,6 +410,9 @@ static int em_salc(struct x86_emulate_ctxt *ctxt) _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ }) =20 +static u64 get_invlpg_linear_addr(struct x86_emulate_ctxt *ctxt, + enum x86_intercept intercept); + static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, enum x86_intercept intercept, enum x86_intercept_stage stage) @@ -427,6 +430,7 @@ static int emulator_check_intercept(struct x86_emulate_= ctxt *ctxt, .src_type =3D ctxt->src.type, .dst_type =3D ctxt->dst.type, .ad_bytes =3D ctxt->ad_bytes, + .invlpg_linear_addr =3D get_invlpg_linear_addr(ctxt, intercept), .rip =3D ctxt->eip, .next_rip =3D ctxt->_eip, }; @@ -702,6 +706,20 @@ static __always_inline int __linearize(struct x86_emul= ate_ctxt *ctxt, return emulate_gp(ctxt, 0); } =20 +static u64 get_invlpg_linear_addr(struct x86_emulate_ctxt *ctxt, + enum x86_intercept intercept) +{ + unsigned int max_size; + unsigned long linear =3D 0; + + if (intercept !=3D x86_intercept_invlpg) + return 0; + + __linearize(ctxt, ctxt->src.addr.mem, &max_size, 1, ctxt->mode, + &linear, X86EMUL_F_INVLPG); + return linear; +} + static int linearize(struct x86_emulate_ctxt *ctxt, struct segmented_address addr, unsigned size, bool write, diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 3e375af15c03..d05558ef28ae 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -51,6 +51,7 @@ struct x86_instruction_info { u8 src_type; /* type of source operand */ u8 dst_type; /* type of destination operand */ u8 ad_bytes; /* size of src/dst address */ + u64 invlpg_linear_addr; /* linear address, if INVLPG */ u64 rip; /* rip of the instruction */ u64 next_rip; /* rip following the instruction */ }; --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out28-123.mail.aliyun.com (out28-123.mail.aliyun.com [115.124.28.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428E53542F8; Sun, 13 Sep 2026 06:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281844; cv=none; b=Werj0Y1eUuLHjSvbFaKWabO1dVT3DjUsNYC7gRzN6CR1Ry0VHHgcCra6N+gQxtuRNGcKInOKKizLkS9XV+80LCDCKQMB23i7TyRtdpnVs34cPdG6zLN8i3M+7BpSv2THI2S7FFfbHdi8AuHj7kBJU/qaMMfBT9okGydSq2phAkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281844; c=relaxed/simple; bh=fGdNZ8wbUnDKryPWMhczDMu4D0+aE0A/tqw1KK2pfK8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ESSo3KIIrHdbxD1mlFCDoHcF1qdYOikOn01xzPzDhyihBPeZePOmOM2b2msnO+NA4AaPkXNlfyUpwVNONWOXrKSoXJl4QA7b4RoqaEec/q8ul8nZxkDlTMe9W3WzasWEGweo1QRFwcPZnES9JPiycbA27bASdP7wPRLEj5xrjnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.5486717|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.130133-0.00141973-0.868447;FP=4970688693919567799|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037028158;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.jCORvm0_1789281835; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvm0_1789281835 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:43:56 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/8] KVM: nSVM: Synthesize DecodeAssists EXITINFO for emulated intercepts Date: Sun, 13 Sep 2026 14:43:42 +0800 Message-ID: X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the x86 emulator encounters an instruction intercepted by L1, svm_check_intercept() synthesizes a nested VM-Exit without fresh hardware DecodeAssist state. Populate the architectural EXITINFO1 field when DecodeAssists is exposed to L1. Provide the GPR number for MOV CR/DR, the interrupt vector for INTn, and the linear address for INVLPG. Leave EXITINFO1 clear for CLTS, LMSW, SMSW, selective CR0 writes, and INVLPGA; the INVLPGA address remains in guest rAX. Leave EXITINFO1 unchanged when DecodeAssists is not exposed, and leave unrelated intercepts unchanged. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/svm.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ea647938a2a6..6834e1101bb6 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4837,6 +4837,7 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu, int vmexit, ret =3D X86EMUL_CONTINUE; struct __x86_intercept icpt_info; struct vmcb *vmcb =3D svm->vmcb; + bool decode_assists; =20 if (info->intercept >=3D ARRAY_SIZE(x86_intercept_map)) goto out; @@ -4846,14 +4847,26 @@ static int svm_check_intercept(struct kvm_vcpu *vcp= u, if (stage !=3D icpt_info.stage) goto out; =20 + decode_assists =3D guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS); + switch (icpt_info.exit_code) { case SVM_EXIT_READ_CR0: if (info->intercept =3D=3D x86_intercept_cr_read) icpt_info.exit_code +=3D info->modrm_reg; + + if (decode_assists) + vmcb->control.exit_info_1 =3D + info->intercept =3D=3D x86_intercept_cr_read ? + BIT_ULL(63) | (info->modrm_rm & 0xf) : 0; break; case SVM_EXIT_WRITE_CR0: { unsigned long cr0, val; =20 + if (decode_assists) + vmcb->control.exit_info_1 =3D + info->intercept =3D=3D x86_intercept_cr_write ? + BIT_ULL(63) | (info->modrm_rm & 0xf) : 0; + /* * Adjust the exit code accordingly if a CR other than CR0 is * being written, and skip straight to the common handling as @@ -4891,13 +4904,30 @@ static int svm_check_intercept(struct kvm_vcpu *vcp= u, */ cr0 =3D vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; val =3D info->src_val & ~SVM_CR0_SELECTIVE_MASK; - if (cr0 ^ val) + if (cr0 ^ val) { icpt_info.exit_code =3D SVM_EXIT_CR0_SEL_WRITE; + if (decode_assists) + vmcb->control.exit_info_1 =3D 0; + } break; } case SVM_EXIT_READ_DR0: case SVM_EXIT_WRITE_DR0: icpt_info.exit_code +=3D info->modrm_reg; + if (decode_assists) + vmcb->control.exit_info_1 =3D info->modrm_rm & 0xf; + break; + case SVM_EXIT_SWINT: + if (decode_assists) + vmcb->control.exit_info_1 =3D info->src_val & 0xff; + break; + case SVM_EXIT_INVLPG: + if (decode_assists) + vmcb->control.exit_info_1 =3D info->invlpg_linear_addr; + break; + case SVM_EXIT_INVLPGA: + if (decode_assists) + vmcb->control.exit_info_1 =3D 0; break; case SVM_EXIT_MSR: if (info->intercept =3D=3D x86_intercept_wrmsr) --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out28-147.mail.aliyun.com (out28-147.mail.aliyun.com [115.124.28.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93A743CAE73; Sun, 13 Sep 2026 06:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281850; cv=none; b=HQDQuOS7UqlnZOpfQaUm60gGCdBSRUUeRsD9xUlBNcD3vzst7X9WjW3nz8hAhx0WgOBx4mL+3GLiGVDHkr9B+ylm50M/WdHA7I/ZdCcGY7GMO+7CDY2s7hLCAwbKfBRieGFcURFN0t2NUvyNc4cz39SoZg+V1xNBdODLKrOe+U0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281850; c=relaxed/simple; bh=RWba314owZ9Uv8BnWcX3Nxln4T+NcIItSeFQNF3m61I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W1ATtGbIEDDYbOfeKJswNoI+OOZZHI39D4zWIakIom+gdEBlXSqj0n+oTRMsX2YtGvhN0RKZ/EkGch/nRdc8Xy4JZ5Y7paNua/erxT/Uxm8i+XA5uMNG+8Ctu6txBXlki+sErKds+xgHIzKQYGaLYqw58kCyMYpkBqrsZUMfJs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436349|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.00351209-0.000496702-0.995991;FP=16636718210716602107|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037032089;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.jCORvmi_1789281836; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvmi_1789281836 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:43:56 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/8] KVM: nSVM: Track valid hardware DecodeAssist bytes Date: Sun, 13 Sep 2026 14:43:43 +0800 Message-ID: <37a1f336c303c78bbf942b1babcde828899968f6.1789281096.git.zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" VMCB02 instruction bytes are valid only for the hardware VM-Exit that populated them. Track whether VMCB02 contains instruction bytes for the data #PF or #NPF currently being reflected to L1 so that stale bytes are not copied to VMCB12. Invalidate VMCB02's instruction-byte state when preparing VMCB02, normally in response to an emulated VMRUN. Mark the bytes as valid only when the current VMCB02 exit is a data #PF or #NPF. Opcode exits and instruction-fetch faults are excluded by inspecting the exit state. A subsequent change will use this state when propagating hardware DecodeAssist instruction bytes to VMCB12. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/nested.c | 38 +++++++++++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 3 +++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 73f37b050d0a..1cc3af8247f2 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -35,6 +35,35 @@ =20 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK =20 +static void nested_svm_invalidate_insn_bytes(struct vmcb *vmcb) +{ + vmcb->control.insn_len =3D 0; +} + +static bool nested_svm_vmexit_supports_insn_bytes(const struct vmcb *vmcb) +{ + u64 exit_code =3D vmcb->control.exit_code; + + if (exit_code !=3D SVM_EXIT_NPF && + exit_code !=3D SVM_EXIT_EXCP_BASE + PF_VECTOR) + return false; + + return !(vmcb->control.exit_info_1 & PFERR_FETCH_MASK); +} + +static void nested_svm_set_vmcb02_insn_bytes_valid(struct vcpu_svm *svm) +{ + svm->nested.vmcb02_insn_bytes_valid =3D + static_cpu_has(X86_FEATURE_DECODEASSISTS) && + nested_svm_vmexit_supports_insn_bytes(svm->nested.vmcb02.ptr); +} + +static void nested_svm_invalidate_vmcb02_insn_bytes(struct vcpu_svm *svm) +{ + nested_svm_invalidate_insn_bytes(svm->nested.vmcb02.ptr); + svm->nested.vmcb02_insn_bytes_valid =3D false; +} + static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, struct x86_exception *fault, bool from_hardware) @@ -68,6 +97,10 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu *= vcpu, (fault->error_code & ~PFERR_GUEST_FAULT_STAGE_MASK); vmcb->control.exit_info_2 =3D fault->address; =20 + if (from_hardware) + nested_svm_set_vmcb02_insn_bytes_valid(svm); + else + svm->nested.vmcb02_insn_bytes_valid =3D false; nested_svm_vmexit(svm); } =20 @@ -869,6 +902,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm) * Filled at exit: exit_code, exit_info_1, exit_info_2, exit_int_info, * exit_int_info_err, next_rip, insn_len, insn_bytes. */ + nested_svm_invalidate_vmcb02_insn_bytes(svm); =20 if (guest_cpu_cap_has(vcpu, X86_FEATURE_VGIF) && (vmcb12_ctrl->int_ctl & V_GIF_ENABLE_MASK)) @@ -1649,8 +1683,10 @@ int nested_svm_exit_handled(struct vcpu_svm *svm) =20 vmexit =3D nested_svm_intercept(svm); =20 - if (vmexit =3D=3D NESTED_EXIT_DONE) + if (vmexit =3D=3D NESTED_EXIT_DONE) { + nested_svm_set_vmcb02_insn_bytes_valid(svm); nested_svm_vmexit(svm); + } =20 return vmexit; } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index e958943b8162..1e12ef1105c0 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -243,6 +243,9 @@ struct svm_nested_state { * on its side. */ bool force_msr_bitmap_recalc; + + /* True if VMCB02 has instruction bytes for the current nested exit. */ + bool vmcb02_insn_bytes_valid; }; =20 struct vcpu_sev_es_state { --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out28-170.mail.aliyun.com (out28-170.mail.aliyun.com [115.124.28.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D70C4356750; Sun, 13 Sep 2026 06:49:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.170 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.0743695|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.00574879-0.000771639-0.99348;FP=12601474251787808763|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033032053168;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.jCORvnL_1789281837; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvnL_1789281837 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:43:57 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/8] KVM: nSVM: Propagate hardware DecodeAssist bytes to VMCB12 Date: Sun, 13 Sep 2026 14:43:44 +0800 Message-ID: <40f8ac084021e48fbadd5697ef16f674554a4480.1789281096.git.zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DecodeAssists provides instruction bytes for nested page faults and intercepted page faults caused by data accesses. When the feature is exposed to L1, copy fresh hardware-provided instruction bytes from VMCB02 to VMCB12 for these exits. Leave the VMCB12 instruction-byte state untouched when DecodeAssists is not exposed. Otherwise, invalidate the state for instruction-fetch page faults, unrelated exits, and exits without fresh hardware bytes. Signed-off-by: Tina Zhang Reviewed-by: Jim Mattson --- arch/x86/kvm/svm/nested.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 1cc3af8247f2..fba230058870 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -40,6 +40,20 @@ static void nested_svm_invalidate_insn_bytes(struct vmcb= *vmcb) vmcb->control.insn_len =3D 0; } =20 +static void nested_svm_copy_insn_bytes(struct vmcb *to, + const struct vmcb *from) +{ + u8 insn_len =3D from->control.insn_len; + + if (WARN_ON_ONCE(insn_len > sizeof(from->control.insn_bytes))) { + nested_svm_invalidate_insn_bytes(to); + return; + } + + memcpy(to->control.insn_bytes, from->control.insn_bytes, insn_len); + to->control.insn_len =3D insn_len; +} + static bool nested_svm_vmexit_supports_insn_bytes(const struct vmcb *vmcb) { u64 exit_code =3D vmcb->control.exit_code; @@ -64,6 +78,27 @@ static void nested_svm_invalidate_vmcb02_insn_bytes(stru= ct vcpu_svm *svm) svm->nested.vmcb02_insn_bytes_valid =3D false; } =20 +static void nested_svm_update_vmcb12_insn_bytes(struct kvm_vcpu *vcpu, + struct vmcb *vmcb12, + const struct vmcb *vmcb02) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS)) + goto out; + + if (!nested_svm_vmexit_supports_insn_bytes(vmcb02) || + !svm->nested.vmcb02_insn_bytes_valid) { + nested_svm_invalidate_insn_bytes(vmcb12); + goto out; + } + + nested_svm_copy_insn_bytes(vmcb12, vmcb02); + +out: + svm->nested.vmcb02_insn_bytes_valid =3D false; +} + static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, struct x86_exception *fault, bool from_hardware) @@ -1331,6 +1366,8 @@ static int nested_svm_vmexit_update_vmcb12(struct kvm= _vcpu *vcpu) if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS)) vmcb12->control.next_rip =3D vmcb02->control.next_rip; =20 + nested_svm_update_vmcb12_insn_bytes(vcpu, vmcb12, vmcb02); + if (nested_vmcb12_has_lbrv(vcpu)) svm_copy_lbrs(&vmcb12->save, &vmcb02->save); =20 --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out198-11.us.a.mail.aliyun.com (out198-11.us.a.mail.aliyun.com [47.90.198.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89CFB3C2BB9; Sun, 13 Sep 2026 06:44:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281866; cv=none; b=kI5HUNk5jQT/9+ruWVnGb8CqbeLYSBFT2elMCuhstwhA/s2z/40gswQ98vfO0KLr3KcUot0at+2tJqaWFUtzUAEUr4tawxGYC0HDoV/lJhXmawF4dLhklogTRCJIKRl69vLGGXfG8kmMP1AbSdLc+9yVREh1abMkpOj6oL9rqQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281866; c=relaxed/simple; bh=iA+Vk9W9LXUSStGGuXFWXeIo2zpYZVW/xu3f6c5kbAQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c+2t0Pu2bc4JYqPObg4DlN9v9rN684fkGR44OzLwEh4rCwcwD/kT+JtRoKPRlvqEi7tcQgdxPZWmyZgV6iYRj+nNBRvQ13GAfMwe63Kr3oLSdTsVNfQRgP07M+xNFr+vUg3G6ApWO/nEvZtIBMU5QxNPJYEXqQn9k1Yzl0RzSdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436279|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.0253741-0.00363635-0.97099;FP=16890027095934979837|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033023018039;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.jCORvnr_1789281837; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvnr_1789281837 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:43:58 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/8] KVM: nSVM: Fetch DecodeAssist bytes for synthesized faults Date: Sun, 13 Sep 2026 14:43:45 +0800 Message-ID: <2cb3eb8fa88f2992b895b68010874fa3261c3a37.1789281096.git.zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hardware-reflected #NPF and #PF VM-Exits can propagate instruction bytes from VMCB02, but KVM-synthesized exits have no hardware-provided state for the current exit. Add kvm_fetch_guest_virt() as a wrapper around the generic guest virtual memory helper that applies instruction-fetch permissions. When a synthesized data #NPF or #PF has no valid VMCB02 instruction bytes, fetch up to 15 bytes from L2's RIP while constructing VMCB12. Preserve the bytes already read if a subsequent read cannot be completed. Limit each read to the current page so that linear address boundaries can be checked before continuing. Outside 64-bit mode, truncate each address to 32 bits and limit the window at the code-segment limit. In 64-bit mode, stop at a non-canonical address. Do not attempt the fallback for SEV guests, as KVM cannot read encrypted guest memory directly. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/nested.c | 64 +++++++++++++++++++++++++++++++++++++-- arch/x86/kvm/x86.c | 23 +++++++++++--- arch/x86/kvm/x86.h | 3 ++ 3 files changed, 83 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index fba230058870..5cb6a9d6907b 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -78,22 +78,80 @@ static void nested_svm_invalidate_vmcb02_insn_bytes(str= uct vcpu_svm *svm) svm->nested.vmcb02_insn_bytes_valid =3D false; } =20 +static u8 nested_svm_get_insn_bytes_len(struct kvm_vcpu *vcpu, u8 max_byte= s) +{ + if (!is_64_bit_mode(vcpu)) { + u32 eip =3D kvm_rip_read(vcpu); + u32 limit =3D to_svm(vcpu)->vmcb->save.cs.limit; + + if (eip > limit) + return 0; + max_bytes =3D min_t(u64, max_bytes, (u64)limit - eip + 1); + } + + return max_bytes; +} + +static u8 nested_svm_fetch_insn_bytes(struct kvm_vcpu *vcpu, u8 *bytes, + u8 max_bytes) +{ + struct x86_exception e; + gva_t rip =3D kvm_get_linear_rip(vcpu); + u8 count =3D 0; + + max_bytes =3D nested_svm_get_insn_bytes_len(vcpu, max_bytes); + + while (count < max_bytes) { + gva_t addr =3D rip + count; + u8 chunk; + + if (!is_64_bit_mode(vcpu)) + addr =3D (u32)addr; + else if (is_noncanonical_address(addr, vcpu, 0)) + break; + + /* + * Read one page at a time to recheck the linear address at each + * boundary. + */ + chunk =3D min_t(unsigned int, max_bytes - count, + PAGE_SIZE - offset_in_page(addr)); + if (kvm_fetch_guest_virt(vcpu, addr, bytes + count, + chunk, &e) !=3D X86EMUL_CONTINUE) + break; + count +=3D chunk; + } + + return count; +} + static void nested_svm_update_vmcb12_insn_bytes(struct kvm_vcpu *vcpu, struct vmcb *vmcb12, const struct vmcb *vmcb02) { struct vcpu_svm *svm =3D to_svm(vcpu); + const u8 max_bytes =3D sizeof(vmcb12->control.insn_bytes); =20 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS)) goto out; =20 - if (!nested_svm_vmexit_supports_insn_bytes(vmcb02) || - !svm->nested.vmcb02_insn_bytes_valid) { + if (!nested_svm_vmexit_supports_insn_bytes(vmcb02)) { nested_svm_invalidate_insn_bytes(vmcb12); goto out; } =20 - nested_svm_copy_insn_bytes(vmcb12, vmcb02); + if (svm->nested.vmcb02_insn_bytes_valid) { + nested_svm_copy_insn_bytes(vmcb12, vmcb02); + goto out; + } + + if (!is_sev_guest(vcpu)) + vmcb12->control.insn_len =3D + nested_svm_fetch_insn_bytes(vcpu, + vmcb12->control.insn_bytes, + max_bytes); + else + nested_svm_invalidate_insn_bytes(vmcb12); =20 out: svm->nested.vmcb02_insn_bytes_valid =3D false; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4b3681796c75..735b67781d55 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4848,9 +4848,24 @@ static int kvm_read_guest_virt_helper(gva_t addr, vo= id *val, unsigned int bytes, } =20 /* used for instruction fetching */ -static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, - gva_t addr, void *val, unsigned int bytes, - struct x86_exception *exception) +int kvm_fetch_guest_virt(struct kvm_vcpu *vcpu, gva_t addr, void *val, + unsigned int bytes, struct x86_exception *exception) +{ + u64 access =3D PFERR_FETCH_MASK; + + if (kvm_x86_call(get_cpl)(vcpu) =3D=3D 3) + access |=3D PFERR_USER_MASK; + + memset(exception, 0, sizeof(*exception)); + return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, + exception); +} +EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_fetch_guest_virt); + +static int emulator_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, + gva_t addr, void *val, + unsigned int bytes, + struct x86_exception *exception) { struct kvm_vcpu *vcpu =3D emul_to_vcpu(ctxt); struct kvm_pagewalk *gva_walk =3D &vcpu->arch.gva_walk; @@ -5817,7 +5832,7 @@ static const struct x86_emulate_ops emulate_ops =3D { .write_gpr =3D emulator_write_gpr, .read_std =3D emulator_read_std, .write_std =3D emulator_write_std, - .fetch =3D kvm_fetch_guest_virt, + .fetch =3D emulator_fetch_guest_virt, .read_emulated =3D emulator_read_emulated, .write_emulated =3D emulator_write_emulated, .cmpxchg_emulated =3D emulator_cmpxchg_emulated, diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 0f5919b092e4..f03419a79a11 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -356,6 +356,9 @@ static inline void adjust_tsc_offset_host(struct kvm_vc= pu *vcpu, s64 adjustment) int kvm_read_guest_virt(struct kvm_vcpu *vcpu, gva_t addr, void *val, unsigned int bytes, struct x86_exception *exception); +int kvm_fetch_guest_virt(struct kvm_vcpu *vcpu, gva_t addr, void *val, + unsigned int bytes, + struct x86_exception *exception); =20 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, unsigned int bytes, --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out28-100.mail.aliyun.com (out28-100.mail.aliyun.com [115.124.28.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CC383CCFC3; Sun, 13 Sep 2026 06:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281850; cv=none; b=P2DpiQnA6LoKweagfgAHYcnzAc5CQt/27MFH0GlVlodHiE77WEglCZHZL89sZfsXtI5JKnQW0z51XTbxun9AptgMQej9QMDIud9JSUk0nAUSYT4oilUOA1GbpQ9hNBjM4gtIoKCbCv7ob+1+GcYIRYtTbJrN22D4Y+yxHFXOlRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvoa_1789281838 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:43:58 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/8] KVM: nSVM: Use emulator bytes for synthesized nested #NPF Date: Sun, 13 Sep 2026 14:43:46 +0800 Message-ID: X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Preserve the bytes used by the emulator when synthesizing a data #NPF. Reuse the fetch cache only when the fault is the current emulator exception, identified by fault =3D=3D &ctxt->exception. Add an emulator accessor to copy cached instruction bytes, checking the RIP and cache bounds. These checks alone do not establish that the cache belongs to the current emulation. Write the cached bytes directly to VMCB02 and fetch any missing tail through the instruction-fetch helper. If the tail cannot be read, report only the bytes already available. For SEV guests, retain only the cached bytes because KVM cannot fetch plaintext guest instructions. Signed-off-by: Tina Zhang Reviewed-by: Jim Mattson --- arch/x86/kvm/emulate.c | 22 ++++++++++++++++++++++ arch/x86/kvm/kvm_emulate.h | 3 +++ arch/x86/kvm/svm/nested.c | 34 ++++++++++++++++++++++++++++++++-- 3 files changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 1dfece6af81e..5017a9aa1d4b 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -913,6 +913,28 @@ static __always_inline int do_insn_fetch_bytes(struct = x86_emulate_ctxt *ctxt, return X86EMUL_CONTINUE; } =20 +/* + * The caller is responsible for ensuring that the fetch cache belongs to + * the current instruction. Matching EIP alone does not guarantee this. + */ +unsigned int x86_emulator_copy_insn_bytes(struct x86_emulate_ctxt *ctxt, + unsigned long eip, u8 *bytes, + unsigned int max_bytes) +{ + unsigned int nr_bytes; + + if (!ctxt || ctxt->eip !=3D eip || + ctxt->fetch.end < ctxt->fetch.data || + ctxt->fetch.end > ctxt->fetch.data + sizeof(ctxt->fetch.data)) + return 0; + + nr_bytes =3D min_t(unsigned int, ctxt->fetch.end - ctxt->fetch.data, + max_bytes); + memcpy(bytes, ctxt->fetch.data, nr_bytes); + return nr_bytes; +} +EXPORT_SYMBOL_FOR_KVM_INTERNAL(x86_emulator_copy_insn_bytes); + /* Fetch next part of the instruction being emulated. */ #define insn_fetch(_type, _ctxt) \ ({ _type _x; \ diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index d05558ef28ae..5361d42e6e05 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -528,6 +528,9 @@ enum x86_intercept { }; =20 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_le= n, int emulation_type); +unsigned int x86_emulator_copy_insn_bytes(struct x86_emulate_ctxt *ctxt, + unsigned long eip, u8 *bytes, + unsigned int max_bytes); bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt); #define EMULATION_FAILED -1 #define EMULATION_OK 0 diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 5cb6a9d6907b..2dc515d73eb6 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -93,13 +93,13 @@ static u8 nested_svm_get_insn_bytes_len(struct kvm_vcpu= *vcpu, u8 max_bytes) } =20 static u8 nested_svm_fetch_insn_bytes(struct kvm_vcpu *vcpu, u8 *bytes, - u8 max_bytes) + u8 count, u8 max_bytes) { struct x86_exception e; gva_t rip =3D kvm_get_linear_rip(vcpu); - u8 count =3D 0; =20 max_bytes =3D nested_svm_get_insn_bytes_len(vcpu, max_bytes); + count =3D min(count, max_bytes); =20 while (count < max_bytes) { gva_t addr =3D rip + count; @@ -125,6 +125,31 @@ static u8 nested_svm_fetch_insn_bytes(struct kvm_vcpu = *vcpu, u8 *bytes, return count; } =20 +static void nested_svm_prepare_synthesized_insn_bytes(struct kvm_vcpu *vcp= u) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + struct vmcb *vmcb02 =3D svm->nested.vmcb02.ptr; + struct x86_emulate_ctxt *ctxt =3D vcpu->arch.emulate_ctxt; + u8 max_bytes =3D sizeof(vmcb02->control.insn_bytes); + u8 count; + + nested_svm_invalidate_vmcb02_insn_bytes(svm); + + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS)) + return; + + max_bytes =3D nested_svm_get_insn_bytes_len(vcpu, max_bytes); + count =3D x86_emulator_copy_insn_bytes(ctxt, kvm_rip_read(vcpu), + vmcb02->control.insn_bytes, max_bytes); + if (!is_sev_guest(vcpu)) + count =3D nested_svm_fetch_insn_bytes(vcpu, + vmcb02->control.insn_bytes, + count, max_bytes); + vmcb02->control.insn_len =3D count; + + svm->nested.vmcb02_insn_bytes_valid =3D true; +} + static void nested_svm_update_vmcb12_insn_bytes(struct kvm_vcpu *vcpu, struct vmcb *vmcb12, const struct vmcb *vmcb02) @@ -149,6 +174,7 @@ static void nested_svm_update_vmcb12_insn_bytes(struct = kvm_vcpu *vcpu, vmcb12->control.insn_len =3D nested_svm_fetch_insn_bytes(vcpu, vmcb12->control.insn_bytes, + 0, max_bytes); else nested_svm_invalidate_insn_bytes(vmcb12); @@ -163,6 +189,8 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu = *vcpu, { struct vcpu_svm *svm =3D to_svm(vcpu); struct vmcb *vmcb =3D svm->vmcb; + struct x86_emulate_ctxt *ctxt =3D vcpu->arch.emulate_ctxt; + bool from_emulation =3D ctxt && fault =3D=3D &ctxt->exception; u64 fault_stage; =20 /* @@ -192,6 +220,8 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu = *vcpu, =20 if (from_hardware) nested_svm_set_vmcb02_insn_bytes_valid(svm); + else if (from_emulation && !(fault->error_code & PFERR_FETCH_MASK)) + nested_svm_prepare_synthesized_insn_bytes(vcpu); else svm->nested.vmcb02_insn_bytes_valid =3D false; nested_svm_vmexit(svm); --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out28-51.mail.aliyun.com (out28-51.mail.aliyun.com [115.124.28.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 908D338C2B8; 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charset="utf-8" Advertise DecodeAssists to L1 now that KVM virtualizes the guest-visible DecodeAssist state in VMCB12: EXITINFO1 decode data for MOV CR/DR, INTn, and INVLPG exits, plus instruction bytes for nested page faults and intercepted #PF exits. INVLPGA's linear address remains available directly from the saved guest rAX, as required by the APM. Expose the feature only when supported by hardware, as KVM still relies on hardware DecodeAssists for VM-Exits that are reflected directly from L2. With DecodeAssists exposed, QEMU configurations that require the feature (e.g. "-cpu ...,+decodeassists,...,enforce") are no longer rejected. Signed-off-by: Tina Zhang Reviewed-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 1 + arch/x86/kvm/svm/svm.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ddb022cb203a..b644e45eac71 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1208,6 +1208,7 @@ void kvm_initialize_cpu_caps(void) VENDOR_F(NPT), VENDOR_F(VMCBCLEAN), VENDOR_F(FLUSHBYASID), + VENDOR_F(DECODEASSISTS), VENDOR_F(NRIPS), VENDOR_F(TSCRATEMSR), VENDOR_F(V_VMSAVE_VMLOAD), diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 6834e1101bb6..c91561a9a49f 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5560,6 +5560,8 @@ static __init void svm_set_cpu_caps(void) */ kvm_cpu_cap_set(X86_FEATURE_FLUSHBYASID); =20 + kvm_cpu_cap_check_and_set(X86_FEATURE_DECODEASSISTS); + if (nrips) kvm_cpu_cap_set(X86_FEATURE_NRIPS); =20 --=20 2.43.7 From nobody Fri Sep 25 12:03:20 2026 Received: from out28-76.mail.aliyun.com (out28-76.mail.aliyun.com [115.124.28.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC8B73CE4B1; Sun, 13 Sep 2026 06:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.76 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281851; cv=none; b=IyNdYt30ra1faqGn+Nun8Kjiz8bFpyqDxZ/8Mo0P27+XcputPf9UvUiQUTblPDy1ezasfvG+sl6OjRmmPOyuu6DGeddEpERgdew9NgdW2brKB6VSKuHlHa2ifUbs/Q63T1so/ZLsh3lWpfffI487DmcjmIigkyzyvpwO+QSjJPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789281851; c=relaxed/simple; bh=dW4DJNLMCH4uZFukJQIzEui5AYhWPdLIA68PknajtkA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ITUQfnH2nU1A25Owt6Do8z2GzD8A5m6kUfWtlAcHBT855NqeQ7qEZsyuqiXJxs9Zby7QFZs8sKVcogUpianb4btmcMwKa4Yyx6qZW14DTWoTKzUPHSIDIqdg0MSO+IdbzIMccT2jChT35P38z2JFIJ7UMckz9Cd9hl4gVb8/mFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00168881-1.14418e-05-0.9983;FP=10359167794406952873|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037006180;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.jCORvpt_1789281839; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.jCORvpt_1789281839 cluster:ay29) by smtp.aliyun-inc.com; Sun, 13 Sep 2026 14:44:00 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 8/8] KVM: selftests: Add nested SVM DecodeAssists test Date: Sun, 13 Sep 2026 14:43:48 +0800 Message-ID: <016ecb3a3187b20fac299f1c2cb15aac01358412.1789281096.git.zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a focused nested SVM selftest for DecodeAssists. Verify that KVM exposes the feature to L1 and synthesizes EXITINFO for representative MOV CR/DR, CLTS, INTn, INVLPG, and INVLPGA intercepts. Exercise instruction bytes for hardware and synthesized #NPF/#PF exits. Cover a synthesized #NPF that follows a hardware #NPF in the same emulated instruction, an unreadable instruction tail that leaves only the cached opcode, and the absence of bytes for an instruction-fetch #PF. Modify the MOVSB opcode while its MMIO read is pending to verify that the emulator's cached bytes are preserved. Inject a userspace #PF while an MMIO read is pending. Verify that after MMIO completion, L1 receives instruction bytes from the current RIP, not the previous instruction's emulator cache. The synthesized OUTSB #NPF and userspace-injected #PF cases run by default. The forced-emulation #PF and instruction-intercept cases require kvm.force_emulation_prefix=3D1. Signed-off-by: Tina Zhang --- tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/include/x86/processor.h | 1 + .../kvm/x86/svm_nested_decode_assists_test.c | 547 ++++++++++++++++++ 3 files changed, 549 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86/svm_nested_decode_assis= ts_test.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 96bab7002d39..bb55a8c32c42 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -118,6 +118,7 @@ TEST_GEN_PROGS_x86 +=3D x86/vmx_preemption_timer_test TEST_GEN_PROGS_x86 +=3D x86/svm_vmcall_test TEST_GEN_PROGS_x86 +=3D x86/svm_int_ctl_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_clear_efer_svme +TEST_GEN_PROGS_x86 +=3D x86/svm_nested_decode_assists_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_shutdown_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_soft_inject_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_vmcb12_gpa diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 6e6f70035508..e9d745a2c131 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -220,6 +220,7 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 4) +#define X86_FEATURE_DECODEASSISTS KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 7) #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 10) #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 12) #define X86_FEATURE_V_VMSAVE_VMLOAD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX= , 15) diff --git a/tools/testing/selftests/kvm/x86/svm_nested_decode_assists_test= .c b/tools/testing/selftests/kvm/x86/svm_nested_decode_assists_test.c new file mode 100644 index 000000000000..9f729e8542f2 --- /dev/null +++ b/tools/testing/selftests/kvm/x86/svm_nested_decode_assists_test.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Test KVM's virtualization of SVM DecodeAssists for nested guests. + */ + +#include "test_util.h" +#include "kvm_util.h" +#include "processor.h" +#include "svm_util.h" + +#define TEST_INT_VECTOR 0x81 + +/* Any canonical virtual address that is never mapped by the selftest VM. = */ +#define PF_TEST_GVA BIT_ULL(40) +#define PF_FETCH_TEST_GVA BIT_ULL(41) + +#define OUTSB_OPCODE 0x6e +#define MOVSB_OPCODE 0xa4 +#define NOP_OPCODE 0x90 +#define BOUNDARY_OUTSB_CODE_SIZE 15 +#define TEST_IOPM_SIZE (3 * PAGE_SIZE) + +static u8 npf_target[PAGE_SIZE] __aligned(PAGE_SIZE); +static u8 mmio_source[PAGE_SIZE] __aligned(PAGE_SIZE); +static u8 boundary_outsb_code[2 * PAGE_SIZE] __aligned(PAGE_SIZE); + +static void l2_read_code(void) +{ + asm volatile("mov (%0), %%rax" : : "r"(&npf_target) : "rax", "memory"); + GUEST_FAIL("L2 read did not cause a nested page fault"); +} + +static void l2_outsb_code(void) +{ + asm volatile("mov %0, %%rsi\n\t" + "mov $0x80, %%dx\n\t" + "outsb" + : : "r"(&npf_target) : "rsi", "rdx", "memory"); + GUEST_FAIL("L2 OUTSB did not cause a nested page fault"); +} + +extern u8 l2_movsb_insn[]; + +static void l2_movsb_code(void) +{ + asm volatile("mov %0, %%rsi\n\t" + "mov %1, %%rdi\n\t" + "l2_movsb_insn:\n\t" + "movsb" + : : "r"(&mmio_source), "r"(&npf_target) + : "rsi", "rdi", "memory"); + GUEST_FAIL("L2 MOVSB did not cause a nested page fault"); +} + +extern u8 l2_userspace_pf_insn[]; + +static void l2_userspace_pf_code(void) +{ + asm volatile("movzbl (%0), %%eax\n\t" + "l2_userspace_pf_insn:\n\t" + "nop" + : : "r"(&mmio_source) : "rax", "memory"); + GUEST_FAIL("Userspace-injected #PF was not intercepted by L1"); +} + +static void l2_pf_code(void) +{ + asm volatile("mov (%0), %%rax" + : : "r"(PF_TEST_GVA) : "rax", "memory"); + GUEST_FAIL("L2 access to an unmapped VA did not #PF"); +} + +static void l2_fep_pf_code(void) +{ + asm volatile(KVM_FEP "mov (%0), %%rax" + : : "r"(PF_TEST_GVA) : "rax", "memory"); + GUEST_FAIL("L2 forced-emulated access to an unmapped VA did not #PF"); +} + +static void l2_fep_mov_from_cr4_code(void) +{ + asm volatile(KVM_FEP "mov %%cr4, %%r10" : : : "r10"); + GUEST_FAIL("L2 forced-emulated MOV-from-CR4 was not intercepted"); +} + +static void l2_fep_mov_to_dr7_code(void) +{ + asm volatile("mov %%dr7, %%rax\n\t" + "mov %%rax, %%rbx\n\t" + KVM_FEP "mov %%rbx, %%dr7" : : : "rax", "rbx"); + GUEST_FAIL("L2 forced-emulated MOV-to-DR7 was not intercepted"); +} + +static void l2_fep_clts_code(void) +{ + asm volatile(KVM_FEP "clts" : : : "memory"); + GUEST_FAIL("L2 forced-emulated CLTS was not intercepted"); +} + +static void l2_fep_int_code(void) +{ + asm volatile(KVM_FEP "int %0" : : "i"(TEST_INT_VECTOR)); + GUEST_FAIL("L2 forced-emulated INTn was not intercepted"); +} + +static void l2_fep_invlpg_code(void) +{ + asm volatile(KVM_FEP "invlpg (%0)" : : "r"(&npf_target) : "memory"); + GUEST_FAIL("L2 forced-emulated INVLPG was not intercepted"); +} + +static void l2_fep_invlpga_code(void) +{ + asm volatile(KVM_FEP "invlpga" + : : "a"(&npf_target), "c"(0) : "memory"); + GUEST_FAIL("L2 forced-emulated INVLPGA was not intercepted"); +} + +struct instruction_intercept_test { + const char *name; + void (*code)(void); + u64 intercept; + u32 intercept_cr; + u32 intercept_dr; + u64 exit_code; + u64 exit_info_1; + u64 exit_info_1_mask; + bool check_rax; + u64 rax; +}; + +static const struct instruction_intercept_test instruction_intercept_tests= [] =3D { + { + .name =3D "MOV-from-CR4", + .code =3D l2_fep_mov_from_cr4_code, + .intercept_cr =3D BIT(INTERCEPT_CR4_READ), + .exit_code =3D SVM_EXIT_READ_CR4, + .exit_info_1 =3D BIT_ULL(63) | 10, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "MOV-to-DR7", + .code =3D l2_fep_mov_to_dr7_code, + .intercept_dr =3D BIT(INTERCEPT_DR7_WRITE), + .exit_code =3D SVM_EXIT_WRITE_DR7, + .exit_info_1 =3D 3, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "CLTS", + .code =3D l2_fep_clts_code, + .intercept_cr =3D BIT(INTERCEPT_CR0_WRITE), + .exit_code =3D SVM_EXIT_WRITE_CR0, + .exit_info_1_mask =3D BIT_ULL(63), + }, { + .name =3D "INTn", + .code =3D l2_fep_int_code, + .intercept =3D BIT_ULL(INTERCEPT_INTn), + .exit_code =3D SVM_EXIT_SWINT, + .exit_info_1 =3D TEST_INT_VECTOR, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "INVLPG", + .code =3D l2_fep_invlpg_code, + .intercept =3D BIT_ULL(INTERCEPT_INVLPG), + .exit_code =3D SVM_EXIT_INVLPG, + .exit_info_1 =3D (u64)&npf_target, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "INVLPGA", + .code =3D l2_fep_invlpga_code, + .intercept =3D BIT_ULL(INTERCEPT_INVLPGA), + .exit_code =3D SVM_EXIT_INVLPGA, + .exit_info_1_mask =3D ~0ULL, + .check_rax =3D true, + .rax =3D (u64)&npf_target, + }, +}; + +static void assert_decode_assist_insn_bytes(struct vmcb *vmcb) +{ + GUEST_ASSERT(vmcb->control.insn_len); + GUEST_ASSERT(vmcb->control.insn_len <=3D + sizeof(vmcb->control.insn_bytes)); + GUEST_ASSERT(!memcmp(vmcb->control.insn_bytes, + (void *)vmcb->save.rip, + vmcb->control.insn_len)); +} + +static void assert_full_decode_assist_insn_bytes(struct vmcb *vmcb) +{ + GUEST_ASSERT_EQ(vmcb->control.insn_len, + sizeof(vmcb->control.insn_bytes)); + assert_decode_assist_insn_bytes(vmcb); +} + +static void prepare_l2_for_vmrun(struct svm_test_data *svm, gva_t rip) +{ + struct vmcb *vmcb =3D svm->vmcb; + + vmcb->save.rip =3D rip; + vmcb->save.rsp =3D (u64)svm->stack; +} + +static void run_intercept_test(struct svm_test_data *svm, + const struct instruction_intercept_test *test) +{ + struct vmcb *vmcb =3D svm->vmcb; + struct vmcb_control_area *control =3D &vmcb->control; + u64 expected_exit_info_1 =3D test->exit_info_1 & test->exit_info_1_mask; + + control->intercept |=3D test->intercept; + control->intercept_cr |=3D test->intercept_cr; + control->intercept_dr |=3D test->intercept_dr; + + control->exit_info_1 =3D ~0ULL; + prepare_l2_for_vmrun(svm, (u64)test->code); + + run_guest(vmcb, svm->vmcb_gpa); + + __GUEST_ASSERT(control->exit_code =3D=3D test->exit_code, + "%s: expected exit code %#lx, got %#lx", + test->name, (unsigned long)test->exit_code, + (unsigned long)control->exit_code); + __GUEST_ASSERT((control->exit_info_1 & test->exit_info_1_mask) =3D=3D + expected_exit_info_1, + "%s: expected EXITINFO1 %#lx with mask %#lx, got %#lx", + test->name, (unsigned long)expected_exit_info_1, + (unsigned long)test->exit_info_1_mask, + (unsigned long)control->exit_info_1); + __GUEST_ASSERT(!control->insn_len, + "%s: expected no instruction bytes, got %u", + test->name, control->insn_len); + + if (test->check_rax) + __GUEST_ASSERT(vmcb->save.rax =3D=3D test->rax, + "%s: expected rAX %#lx, got %#lx", + test->name, (unsigned long)test->rax, + (unsigned long)vmcb->save.rax); + + control->intercept &=3D ~test->intercept; + control->intercept_cr &=3D ~test->intercept_cr; + control->intercept_dr &=3D ~test->intercept_dr; +} + +static void test_instruction_intercepts(struct svm_test_data *svm) +{ + int i; + + if (!is_forced_emulation_enabled) + return; + + for (i =3D 0; i < ARRAY_SIZE(instruction_intercept_tests); i++) + run_intercept_test(svm, &instruction_intercept_tests[i]); +} + +static void test_hardware_npf(struct svm_test_data *svm, gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_read_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + assert_decode_assist_insn_bytes(vmcb); +} + +/* + * The IOIO intercept causes L0 to emulate OUTSB before accessing its sour= ce + * operand. The emulated read then faults on L1's NPT, resulting in a + * KVM-synthesized #NPF. + */ +static void test_synthesized_npf(struct svm_test_data *svm, gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_outsb_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + assert_full_decode_assist_insn_bytes(vmcb); +} + +/* + * MOVSB first reads from MMIO, causing a hardware #NPF that L0 emulates. + * After userspace completes the read, the emulated destination write faul= ts + * on L1's NPT. The new #NPF must not reuse the original hardware exit's = GPA. + * Userspace replaces MOVSB with NOP while the read is pending. DecodeAss= ist + * must retain the cached MOVSB bytes instead of re-reading the opcode. + */ +static void test_synthesized_npf_after_hardware_npf(struct svm_test_data *= svm, + gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + u8 insn_bytes[sizeof(vmcb->control.insn_bytes)]; + + memcpy(insn_bytes, l2_movsb_insn, sizeof(insn_bytes)); + GUEST_ASSERT_EQ(insn_bytes[0], MOVSB_OPCODE); + prepare_l2_for_vmrun(svm, (u64)l2_movsb_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + GUEST_ASSERT_EQ(vmcb->save.rip, (u64)l2_movsb_insn); + GUEST_ASSERT_EQ(l2_movsb_insn[0], NOP_OPCODE); + GUEST_ASSERT_EQ(vmcb->control.insn_len, sizeof(insn_bytes)); + GUEST_ASSERT(!memcmp(vmcb->control.insn_bytes, insn_bytes, + sizeof(insn_bytes))); +} + +/* + * OUTSB is the final byte of a mapped code page, and the following page is + * not present in L2's page tables. DecodeAssist byte fetching must stop = at + * the page boundary and report only the OUTSB opcode. + */ +static void test_synthesized_npf_truncated(struct svm_test_data *svm, + gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, + (u64)&boundary_outsb_code[PAGE_SIZE - + BOUNDARY_OUTSB_CODE_SIZE]); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + GUEST_ASSERT_EQ(vmcb->save.rip, + (u64)&boundary_outsb_code[PAGE_SIZE - 1]); + GUEST_ASSERT_EQ(vmcb->control.insn_len, 1); + GUEST_ASSERT_EQ(vmcb->control.insn_bytes[0], OUTSB_OPCODE); +} + +static void test_hardware_intercepted_pf(struct svm_test_data *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_pf_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_TEST_GVA); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_PRESENT_MASK)); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_FETCH_MASK)); + assert_decode_assist_insn_bytes(vmcb); +} + +static void test_hardware_intercepted_fetch_pf(struct svm_test_data *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, PF_FETCH_TEST_GVA); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_FETCH_TEST_GVA); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_PRESENT_MASK)); + GUEST_ASSERT(vmcb->control.exit_info_1 & PFERR_FETCH_MASK); + GUEST_ASSERT_EQ(vmcb->control.insn_len, 0); +} + +static void test_synthesized_pf(struct svm_test_data *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + if (!is_forced_emulation_enabled) + return; + + prepare_l2_for_vmrun(svm, (u64)l2_fep_pf_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_TEST_GVA); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_PRESENT_MASK)); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_FETCH_MASK)); + assert_full_decode_assist_insn_bytes(vmcb); +} + +/* The pending MMIO instruction must complete before reflecting userspace = #PF. */ +static void test_userspace_injected_pf_during_emulation(struct svm_test_da= ta *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_userspace_pf_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_1, 0); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_TEST_GVA); + GUEST_ASSERT_EQ(vmcb->save.rip, (u64)l2_userspace_pf_insn); + GUEST_ASSERT_EQ(vmcb->save.rax, 0x5a); + assert_full_decode_assist_insn_bytes(vmcb); + GUEST_ASSERT_EQ(vmcb->control.insn_bytes[0], NOP_OPCODE); +} + +static void l1_guest_code(struct svm_test_data *svm, gpa_t npf_gpa, + gpa_t iopm_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + GUEST_ASSERT(this_cpu_has(X86_FEATURE_DECODEASSISTS)); + + generic_svm_setup(svm, l2_read_code); + vmcb->control.iopm_base_pa =3D iopm_gpa; + + vmcb->control.intercept |=3D BIT_ULL(INTERCEPT_IOIO_PROT); + vmcb->control.intercept_exceptions |=3D 1U << PF_VECTOR; + + test_hardware_npf(svm, npf_gpa); + test_synthesized_npf(svm, npf_gpa); + test_synthesized_npf_after_hardware_npf(svm, npf_gpa); + test_synthesized_npf_truncated(svm, npf_gpa); + test_hardware_intercepted_pf(svm); + test_hardware_intercepted_fetch_pf(svm); + test_synthesized_pf(svm); + test_userspace_injected_pf_during_emulation(svm); + test_instruction_intercepts(svm); + + GUEST_DONE(); +} + +static void build_boundary_outsb_code(u8 *code) +{ + u64 source =3D (u64)&npf_target; + + /* movabs $npf_target, %rsi */ + code[0] =3D 0x48; + code[1] =3D 0xbe; + memcpy(&code[2], &source, sizeof(source)); + + /* mov $0x80, %dx; outsb */ + code[10] =3D 0x66; + code[11] =3D 0xba; + code[12] =3D 0x80; + code[13] =3D 0x00; + code[14] =3D OUTSB_OPCODE; +} + +static void prepare_boundary_outsb_code(struct kvm_vm *vm) +{ + gva_t code_gva =3D (gva_t)&boundary_outsb_code[PAGE_SIZE - + BOUNDARY_OUTSB_CODE_SIZE]; + + build_boundary_outsb_code(addr_gva2hva(vm, code_gva)); +} + +static void queue_userspace_pf(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_events events; + + vcpu_events_get(vcpu, &events); + TEST_ASSERT(!events.exception.pending && !events.exception.injected, + "Unexpected exception before userspace #PF injection"); + TEST_ASSERT(events.flags & KVM_VCPUEVENT_VALID_PAYLOAD, + "KVM_CAP_EXCEPTION_PAYLOAD was not enabled"); + + events.exception.pending =3D true; + events.exception.nr =3D PF_VECTOR; + events.exception.has_error_code =3D true; + events.exception.error_code =3D 0; + events.exception_has_payload =3D true; + events.exception_payload =3D PF_TEST_GVA; + vcpu_events_set(vcpu, &events); +} + +static void complete_mmio_read(struct kvm_vcpu *vcpu, gpa_t expected_gpa, + u8 value) +{ + if (vcpu->run->exit_reason =3D=3D KVM_EXIT_IO) { + struct ucall uc; + + if (get_ucall(vcpu, &uc) =3D=3D UCALL_ABORT) + REPORT_GUEST_ASSERT(uc); + } + + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_MMIO); + TEST_ASSERT(!vcpu->run->mmio.is_write, + "Expected an MMIO read, got a write"); + TEST_ASSERT_EQ(vcpu->run->mmio.phys_addr, expected_gpa); + TEST_ASSERT_EQ(vcpu->run->mmio.len, 1); + vcpu->run->mmio.data[0] =3D value; +} + +static void assert_ucall_done(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + u64 actual; + + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); + actual =3D get_ucall(vcpu, &uc); + if (actual =3D=3D UCALL_ABORT) + REPORT_GUEST_ASSERT(uc); + + TEST_ASSERT_EQ(actual, UCALL_DONE); +} + +int main(int argc, char *argv[]) +{ + gva_t svm_gva, npf_gva, boundary_page_gva, iopm_gva; + gpa_t npf_gpa, mmio_source_gpa, mmio_gpa, iopm_gpa; + struct userspace_mem_region *region; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + u8 *movsb_insn; + u64 *pte; + + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM)); + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_NPT)); + TEST_REQUIRE(this_cpu_has(X86_FEATURE_DECODEASSISTS)); + TEST_ASSERT(kvm_cpu_has(X86_FEATURE_DECODEASSISTS), + "KVM failed to expose DecodeAssists"); + TEST_REQUIRE(kvm_has_cap(KVM_CAP_EXCEPTION_PAYLOAD)); + + vm =3D vm_create_with_one_vcpu(&vcpu, l1_guest_code); + vm_enable_cap(vm, KVM_CAP_EXCEPTION_PAYLOAD, 1); + prepare_boundary_outsb_code(vm); + vm_enable_npt(vm); + vcpu_alloc_svm(vm, &svm_gva); + iopm_gva =3D vm_alloc_pages(vm, TEST_IOPM_SIZE / PAGE_SIZE); + iopm_gpa =3D addr_gva2gpa(vm, iopm_gva); + memset(addr_gva2hva(vm, iopm_gva), 0, TEST_IOPM_SIZE); + npf_gva =3D (gva_t)&npf_target; + npf_gpa =3D addr_gva2gpa(vm, npf_gva); + + tdp_identity_map_default_memslots(vm); + pte =3D tdp_get_pte(vm, npf_gpa); + *pte &=3D ~PTE_PRESENT_MASK(&vm->stage2_mmu); + region =3D memslot2region(vm, 0); + mmio_gpa =3D region->region.guest_phys_addr + + region->region.memory_size + PAGE_SIZE; + mmio_source_gpa =3D addr_gva2gpa(vm, (gva_t)&mmio_source); + pte =3D tdp_get_pte(vm, mmio_source_gpa); + *pte =3D (*pte & ~PHYSICAL_PAGE_MASK) | mmio_gpa; + + boundary_page_gva =3D (gva_t)&boundary_outsb_code[PAGE_SIZE]; + pte =3D vm_get_pte(vm, boundary_page_gva); + *pte &=3D ~PTE_PRESENT_MASK(&vm->mmu); + + vcpu_args_set(vcpu, 3, svm_gva, npf_gpa, iopm_gpa); + + /* Complete the MOVSB source read. */ + vcpu_run(vcpu); + complete_mmio_read(vcpu, mmio_gpa, 0xa5); + movsb_insn =3D addr_gva2hva(vm, (gva_t)l2_movsb_insn); + TEST_ASSERT_EQ(movsb_insn[0], MOVSB_OPCODE); + movsb_insn[0] =3D NOP_OPCODE; + vcpu_run(vcpu); + complete_mmio_read(vcpu, mmio_gpa, 0x5a); + queue_userspace_pf(vcpu); + vcpu_run(vcpu); + assert_ucall_done(vcpu); + + kvm_vm_free(vm); + return 0; +} --=20 2.43.7