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charset="utf-8" From: Adrian Ng Ho Yin After commit 9119ceb76e98 ("firmware: stratix10-svc: fix memory leaks and list corruption bugs") removed the erroneous list_del(&svc_data_mem) that corrupted the list head on failed lookups, an unmatched free still silently returned. Report the spurious address with dev_warn(). While here, refactor the loop to use an inverted condition with continue to reduce nesting. Add braces in svc_pa_to_va() for consistency, and fix a stale "physical address" comment to "address" since paddr is not strictly a physical address. Signed-off-by: Adrian Ng Ho Yin --- drivers/firmware/stratix10-svc.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index 34c591d7fd58..643cc008808e 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -338,11 +338,12 @@ static void *svc_pa_to_va(unsigned long addr) =20 pr_debug("claim back P-addr=3D0x%016x\n", (unsigned int)addr); guard(mutex)(&svc_mem_lock); - list_for_each_entry(pmem, &svc_data_mem, node) + list_for_each_entry(pmem, &svc_data_mem, node) { if (pmem->paddr =3D=3D addr) return pmem->vaddr; + } =20 - /* physical address is not found */ + /* address is not found */ return NULL; } =20 @@ -1997,19 +1998,23 @@ EXPORT_SYMBOL_GPL(stratix10_svc_allocate_memory); */ void stratix10_svc_free_memory(struct stratix10_svc_chan *chan, void *kadd= r) { + struct stratix10_svc_controller *ctrl =3D chan->ctrl; struct stratix10_svc_data_mem *pmem; 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charset="utf-8" From: Adrian Ng Ho Yin On Agilex5, DDR starts at 0x8000_0000 which is outside the SDM's addressable range. When SMMU is active, the driver must allocate DMA-coherent buffers and pass IOVAs (not physical addresses) to ATF. Add SVC_SDM_DMA_ADDR_BITS (29) and SVC_SDM_DMA_ADDR_OFFSET (0x8000_0000) to constrain IOVAs to the 0-512 MB window the SDM can reach and to satisfy ATF's address range check respectively. Extend struct stratix10_svc_data_mem with dma_addr, and struct stratix10_svc_controller with use_dma_mem and dma_addr_offset. Update allocate/free and svc_thread_cmd_data_claim() for the DMA path. Wire the Agilex5 path in probe: require an IOMMU domain for intel,agilex5-svc, bypass the SDM address remapper via INTEL_SIP_SMC_SDM_REMAPPER_CONFIG, call svc_setup_dma_memory() to set the 29-bit DMA mask, select the DMA path through stratix10_svc_pdata, register a devm cleanup for leaked buffers, and guard err_destroy_pool against a NULL genpool. Signed-off-by: Adrian Ng Ho Yin --- drivers/firmware/stratix10-svc.c | 229 ++++++++++++++++--- include/linux/firmware/intel/stratix10-smc.h | 23 ++ 2 files changed, 215 insertions(+), 37 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index 643cc008808e..fa2335378536 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -7,10 +7,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -48,6 +50,23 @@ #define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30 #define BYTE_TO_WORD_SIZE 4 =20 +/* + * SVC_SDM_DMA_ADDR_BITS - constrains the IOVA allocated by + * dma_alloc_coherent() to 29 bits (0x0000_0000 - 0x1FFF_FFFF) + * when SMMU is active on Agilex5. The SDM accesses these buffers + * via the SMMU using IOVAs, so the 29-bit limit keeps IOVAs within + * the SDM's addressable window. + * + * SVC_SDM_DMA_ADDR_OFFSET - ATF on Agilex5 distinguishes + * SMMU-mapped buffers from direct physical addresses by the + * presence of this offset. The driver adds it to the IOVA before + * passing the address to ATF via SMC; ATF strips it, translates + * the remaining IOVA through the SMMU, and the SDM accesses the + * underlying physical memory. + */ +#define SVC_SDM_DMA_ADDR_BITS 29 +#define SVC_SDM_DMA_ADDR_OFFSET 0x80000000UL + /* stratix10 service layer clients */ #define STRATIX10_RSU "stratix10-rsu" #define SOCFPGA_HWMON "socfpga-hwmon" @@ -103,12 +122,17 @@ =20 struct stratix10_svc_pdata { bool needs_psci_cpu_off; + bool use_dma_mem; }; =20 static const struct stratix10_svc_pdata psci_cpu_off_pdata =3D { .needs_psci_cpu_off =3D true, }; =20 +static const struct stratix10_svc_pdata agilex5_pdata =3D { + .use_dma_mem =3D true, +}; + typedef void (svc_invoke_fn)(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, @@ -149,18 +173,25 @@ struct stratix10_svc_sh_memory { /** * struct stratix10_svc_data_mem - service memory structure * @vaddr: virtual address - * @paddr: physical address + * @paddr: address passed to ATF via SMC and echoed back in completion + * notifications; used as the lookup key in svc_pa_to_va(). + * On the SMMU path this is (IOVA + %SVC_SDM_DMA_ADDR_OFFSET); + * on the gen_pool path this equals the raw physical address. * @size: size of memory + * @dma_addr: IOVA returned by dma_alloc_coherent(); used to free the + * mapping via dma_free_coherent() on the SMMU path. * @node: link list head node * * This struct is used in a list that keeps track of buffers which have * been allocated or freed from the memory pool. Service layer driver also - * uses this struct to transfer physical address to virtual address. + * uses this struct to map the address returned by ATF back to a virtual + * address. */ struct stratix10_svc_data_mem { void *vaddr; phys_addr_t paddr; size_t size; + dma_addr_t dma_addr; struct list_head node; }; =20 @@ -296,6 +327,15 @@ struct stratix10_svc_chan { * @sdm_lock: only allows a single command single response to SDM * @actrl: async control structure * @psci_reboot_nb: reboot notifier for PSCI secondary CPU offlining + * @use_dma_mem: when true, buffers are allocated via dma_alloc_coherent() + * instead of the ATF reserved-memory gen_pool. + * @dma_addr_offset: value added to the DMA address (IOVA) before passing = it + * to ATF via SMC. ATF uses this offset to distinguish + * SMMU-mapped buffers from direct physical addresses; it + * strips the offset, translates the remaining IOVA thro= ugh + * the SMMU, and the SDM accesses the underlying memory. + * Set to %SVC_SDM_DMA_ADDR_OFFSET on Agilex5 when SMMU = is + * active; zero otherwise. * @chans: array of service channels * * This struct is used to create communication channels for service client= s, to @@ -313,6 +353,8 @@ struct stratix10_svc_controller { struct mutex sdm_lock; struct stratix10_async_ctrl actrl; struct notifier_block psci_reboot_nb; + bool use_dma_mem; + unsigned long dma_addr_offset; struct stratix10_svc_chan chans[] __counted_by(num_chans); }; =20 @@ -377,11 +419,17 @@ static void svc_thread_cmd_data_claim(struct stratix1= 0_svc_controller *ctrl, break; } cb_data->status =3D BIT(SVC_STATUS_BUFFER_DONE); - cb_data->kaddr1 =3D svc_pa_to_va(res.a1); + /* + * The firmware COMPLETED_WRITE response returns the + * raw IOVA (without dma_addr_offset). Add it back to + * match the key stored in pmem->paddr at allocation + * time. dma_addr_offset is zero on non-SMMU paths. + */ + cb_data->kaddr1 =3D svc_pa_to_va(res.a1 + ctrl->dma_addr_offset); cb_data->kaddr2 =3D (res.a2) ? - svc_pa_to_va(res.a2) : NULL; + svc_pa_to_va(res.a2 + ctrl->dma_addr_offset) : NULL; cb_data->kaddr3 =3D (res.a3) ? - svc_pa_to_va(res.a3) : NULL; + svc_pa_to_va(res.a3 + ctrl->dma_addr_offset) : NULL; p_data->chan->scl->receive_cb(p_data->chan->scl, cb_data); } else { @@ -1052,6 +1100,38 @@ svc_create_memory_pool(struct platform_device *pdev, return genpool; } =20 +/** + * svc_setup_dma_memory() - configure the device for dynamic DMA allocation + * @pdev: pointer to service layer device + * + * Called instead of svc_get_sh_memory() + svc_create_memory_pool() when + * the device is behind an SMMU. Sets a 29-bit coherent DMA mask so that + * every subsequent dma_alloc_coherent() call yields an IOVA within the + * first 512MB (0x0000_0000 - 0x1FFF_FFFF). The driver then adds + * %SVC_SDM_DMA_ADDR_OFFSET to the IOVA before passing it to ATF; ATF + * strips the offset and uses the SMMU to translate the IOVA to the + * underlying physical memory for SDM access. + * + * Return: 0 on success, or a negative error code on failure. + */ +static int svc_setup_dma_memory(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(SVC_SDM_DMA_ADDR_BITS= )); + if (ret) { + dev_err(dev, + "failed to set %u-bit DMA mask: %d\n", + SVC_SDM_DMA_ADDR_BITS, ret); + return ret; + } + + dev_info(dev, + "SMMU enabled: using dynamic DMA allocation (IOVA range 0-512MB)\n"); + return 0; +} + /** * svc_smccc_smc() - secure monitor call between normal and secure world * @a0: argument passed in registers 0 @@ -1958,34 +2038,50 @@ EXPORT_SYMBOL_GPL(stratix10_svc_done); void *stratix10_svc_allocate_memory(struct stratix10_svc_chan *chan, size_t size) { + struct stratix10_svc_controller *ctrl =3D chan->ctrl; struct stratix10_svc_data_mem *pmem; - unsigned long va; - phys_addr_t pa; - struct gen_pool *genpool =3D chan->ctrl->genpool; - size_t s =3D roundup(size, 1 << genpool->min_alloc_order); + struct gen_pool *genpool; + dma_addr_t dma_addr; + size_t s; + void *va; =20 pmem =3D kzalloc_obj(*pmem); if (!pmem) return ERR_PTR(-ENOMEM); =20 - guard(mutex)(&svc_mem_lock); - va =3D gen_pool_alloc(genpool, s); - if (!va) { - kfree(pmem); - return ERR_PTR(-ENOMEM); - } + if (ctrl->use_dma_mem) { + va =3D dma_alloc_coherent(ctrl->dev, size, &dma_addr, GFP_KERNEL); + if (!va) { + kfree(pmem); + return ERR_PTR(-ENOMEM); + } + + pmem->vaddr =3D va; + pmem->paddr =3D dma_addr + ctrl->dma_addr_offset; + pmem->dma_addr =3D dma_addr; + pmem->size =3D size; + } else { + genpool =3D ctrl->genpool; + s =3D roundup(size, 1 << genpool->min_alloc_order); =20 - memset((void *)va, 0, s); - pa =3D gen_pool_virt_to_phys(genpool, va); + va =3D (void *)gen_pool_alloc(genpool, s); + if (!va) { + kfree(pmem); + return ERR_PTR(-ENOMEM); + } + + memset(va, 0, s); + pmem->vaddr =3D va; + pmem->paddr =3D gen_pool_virt_to_phys(genpool, (unsigned long)va); + pmem->size =3D s; + } =20 - pmem->vaddr =3D (void *)va; - pmem->paddr =3D pa; - pmem->size =3D s; + guard(mutex)(&svc_mem_lock); list_add_tail(&pmem->node, &svc_data_mem); - pr_debug("%s: %s: va=3D%p, pa=3D0x%016x\n", __func__, - chan->name, pmem->vaddr, (unsigned int)pmem->paddr); + pr_debug("%s: %s: va=3D%p, addr=3D0x%016llx\n", __func__, + chan->name, pmem->vaddr, (unsigned long long)pmem->paddr); =20 - return (void *)va; + return va; } EXPORT_SYMBOL_GPL(stratix10_svc_allocate_memory); =20 @@ -2007,8 +2103,13 @@ void stratix10_svc_free_memory(struct stratix10_svc_= chan *chan, void *kaddr) if (pmem->vaddr !=3D kaddr) continue; =20 - gen_pool_free(ctrl->genpool, (unsigned long)kaddr, pmem->size); - pmem->vaddr =3D NULL; + if (ctrl->use_dma_mem) { + dma_free_coherent(ctrl->dev, pmem->size, + pmem->vaddr, pmem->dma_addr); + } else { + gen_pool_free(ctrl->genpool, + (unsigned long)kaddr, pmem->size); + } list_del(&pmem->node); kfree(pmem); return; @@ -2073,6 +2174,7 @@ static void psci_cpu_off_teardown(struct stratix10_sv= c_controller *ctrl) static const struct of_device_id stratix10_svc_drv_match[] =3D { { .compatible =3D "intel,stratix10-svc", .data =3D &psci_cpu_off_pdata }, { .compatible =3D "intel,agilex-svc", .data =3D &psci_cpu_off_pdata }, + { .compatible =3D "intel,agilex5-svc", .data =3D &agilex5_pdata }, {}, }; =20 @@ -2083,14 +2185,38 @@ static const char * const chan_names[SVC_NUM_CHANNE= L] =3D { SVC_CLIENT_HWMON }; =20 +static void svc_data_mem_cleanup(void *data) +{ + struct stratix10_svc_controller *ctrl =3D data; + struct stratix10_svc_data_mem *pmem, *tmp; + + guard(mutex)(&svc_mem_lock); + + list_for_each_entry_safe(pmem, tmp, &svc_data_mem, node) { + dev_warn(ctrl->dev, "leaked svc buffer %p, freeing on unbind\n", + pmem->vaddr); + if (ctrl->use_dma_mem) { + dma_free_coherent(ctrl->dev, pmem->size, + pmem->vaddr, pmem->dma_addr); + } else { + gen_pool_free(ctrl->genpool, + (unsigned long)pmem->vaddr, pmem->size); + } + list_del(&pmem->node); + kfree(pmem); + } +} + static int stratix10_svc_drv_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct stratix10_svc_controller *controller; - struct gen_pool *genpool; + struct gen_pool *genpool =3D NULL; struct stratix10_svc_sh_memory *sh_memory; struct stratix10_svc *svc =3D NULL; const struct stratix10_svc_pdata *pdata =3D of_device_get_match_data(dev); + struct arm_smccc_res res; + bool use_dma_mem =3D false; =20 svc_invoke_fn *invoke_fn; size_t fifo_size; @@ -2101,18 +2227,38 @@ static int stratix10_svc_drv_probe(struct platform_= device *pdev) if (IS_ERR(invoke_fn)) return -EINVAL; =20 - sh_memory =3D devm_kzalloc(dev, sizeof(*sh_memory), GFP_KERNEL); - if (!sh_memory) - return -ENOMEM; + use_dma_mem =3D pdata && pdata->use_dma_mem; =20 - sh_memory->invoke_fn =3D invoke_fn; - ret =3D svc_get_sh_memory(pdev, sh_memory); - if (ret) - return ret; + if (use_dma_mem) { + if (!iommu_get_domain_for_dev(dev)) { + dev_err(dev, + "SMMU is required for agilex5-svc but no IOMMU domain found\n"); + dev_err(dev, + "Ensure the SMMU node is enabled in the device tree and 'iommus' is se= t for this node\n"); + return -ENODEV; + } =20 - genpool =3D svc_create_memory_pool(pdev, sh_memory); - if (IS_ERR(genpool)) - return PTR_ERR(genpool); + invoke_fn(INTEL_SIP_SMC_SDM_REMAPPER_CONFIG, + INTEL_SIP_SMC_SDM_REMAPPER_BYPASS, + 0, 0, 0, 0, 0, 0, &res); + + ret =3D svc_setup_dma_memory(pdev); + if (ret) + return ret; + } else { + sh_memory =3D devm_kzalloc(dev, sizeof(*sh_memory), GFP_KERNEL); + if (!sh_memory) + return -ENOMEM; + + sh_memory->invoke_fn =3D invoke_fn; + ret =3D svc_get_sh_memory(pdev, sh_memory); + if (ret) + return ret; + + genpool =3D svc_create_memory_pool(pdev, sh_memory); + if (IS_ERR(genpool)) + return PTR_ERR(genpool); + } =20 /* allocate service controller and supporting channel */ controller =3D devm_kzalloc(dev, struct_size(controller, chans, SVC_NUM_C= HANNEL), @@ -2127,9 +2273,17 @@ static int stratix10_svc_drv_probe(struct platform_d= evice *pdev) controller->num_active_client =3D 0; controller->genpool =3D genpool; controller->invoke_fn =3D invoke_fn; + controller->use_dma_mem =3D use_dma_mem; + controller->dma_addr_offset =3D use_dma_mem ? SVC_SDM_DMA_ADDR_OFFSET : 0; INIT_LIST_HEAD(&controller->node); init_completion(&controller->complete_status); =20 + if (use_dma_mem) { + ret =3D devm_add_action_or_reset(dev, svc_data_mem_cleanup, controller); + if (ret) + goto err_destroy_pool; + } + if (pdata && pdata->needs_psci_cpu_off) { controller->psci_reboot_nb.notifier_call =3D psci_cpu_off_reboot_notifier; @@ -2237,7 +2391,8 @@ static int stratix10_svc_drv_probe(struct platform_de= vice *pdev) err_free_notifier: psci_cpu_off_teardown(controller); err_destroy_pool: - gen_pool_destroy(genpool); + if (genpool) + gen_pool_destroy(genpool); =20 return ret; } diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/f= irmware/intel/stratix10-smc.h index 366309260121..b0d42d585a75 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -813,4 +813,27 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_= CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_NOTIFY (0xEC) #define INTEL_SIP_SMC_ASYNC_RSU_NOTIFY \ INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_NOTIFY) + +/** + * Request INTEL_SIP_SMC_SDM_REMAPPER_CONFIG + * + * Sync call to configure the SDM address remapper. On Agilex5, the remapp= er + * must be bypassed when the SMMU is active to avoid conflicts with IOMMU + * address translation. + * + * Call register usage: + * a0: INTEL_SIP_SMC_SDM_REMAPPER_CONFIG + * a1: INTEL_SIP_SMC_SDM_REMAPPER_ENABLE or INTEL_SIP_SMC_SDM_REMAPPER_BYP= ASS + * a2-7: not used + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK + * a1-3: not used + */ +#define INTEL_SIP_SMC_FUNCID_SDM_REMAPPER_CONFIG 513 +#define INTEL_SIP_SMC_SDM_REMAPPER_CONFIG \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_SDM_REMAPPER_CONFIG) +#define INTEL_SIP_SMC_SDM_REMAPPER_ENABLE 0 +#define INTEL_SIP_SMC_SDM_REMAPPER_BYPASS 1 + #endif --=20 2.49.GIT