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Thu, 10 Sep 2026 16:17:22 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v4 01/15] iommu/arm-smmu-v3: Disable the impl before disabling the SMMU on shutdown Date: Thu, 10 Sep 2026 16:16:53 -0700 Message-ID: <61536b87c45164b1f581ee4358574ee7822e212d.1789081084.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|SA3PR12MB8047:EE_ X-MS-Office365-Filtering-Correlation-Id: aadb92ee-9d15-4a1a-3b6b-08df0f91b750 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|7416014|82310400026|23010399003|1800799024|10067099003|22082099003|18002099003|11063799006|56012099006; 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charset="utf-8" arm_smmu_device_shutdown() only calls arm_smmu_device_disable(), and never the impl_ops->device_disable() hook. On tegra241-cmdqv, that hook quiesces every VINTF through tegra241_vintf_hw_deinit(), which issues a CMD_SYNC on the shared CMDQ while it is still enabled. arm_smmu_disable_action() already runs this hook before disabling the SMMU, to cover an unbind or a probe failure, and no devres release ever follows a reboot or a kexec to run it again. Have arm_smmu_device_shutdown() call it directly, instead of reimplementing part of what it already does. Fixes: 9ff145a25c5c ("iommu/tegra241-cmdqv: Fix CMD_SYNC use-after-free on = teardown") Cc: stable@vger.kernel.org Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5732f3ba0122d..81baafaffc410 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5633,7 +5633,7 @@ static void arm_smmu_device_shutdown(struct platform_= device *pdev) { struct arm_smmu_device *smmu =3D platform_get_drvdata(pdev); =20 - arm_smmu_device_disable(smmu); + arm_smmu_disable_action(smmu); } =20 static const struct of_device_id arm_smmu_of_match[] =3D { --=20 2.43.0 From nobody Fri Sep 25 15:13:22 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013012.outbound.protection.outlook.com [40.93.201.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AFC939A4CF; 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charset="utf-8" The IOPF teardown is done in arm_smmu_remove_master_domain() when releasing the master_domain on detach, under the global arm_smmu_asid_lock mutex. A later change will add an IOPF workqueue flush to that teardown, which can block on a user-faulting page-fault handler. Holding the arm_smmu_asid_lock across it would stall every unrelated attachment in the system. Split the teardown out of arm_smmu_remove_master_domain(), to a new helper arm_smmu_attach_release() that runs after arm_smmu_asid_lock is released. No functional change: the old master_domain belongs to no other device, so freeing it outside the lock stays safe, still under iommu_group->mutex. Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 44 ++++++++++++++----- 3 files changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 50f8321e979ce..5b89bad71c102 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1204,12 +1204,14 @@ struct arm_smmu_attach_state { struct arm_smmu_vmaster *vmaster; struct arm_smmu_inv_state old_domain_invst; struct arm_smmu_inv_state new_domain_invst; + struct arm_smmu_master_domain *old_master_domain; bool ats_enabled; }; =20 int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, struct iommu_domain *new_domain); void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); +void arm_smmu_attach_release(struct arm_smmu_attach_state *state); void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, const struct arm_smmu_ste *target); =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 25982bdbcbd9a..fce026efa44f1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -194,6 +194,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_doma= in *domain, arm_smmu_install_ste_for_dev(master, &ste); arm_smmu_attach_commit(&state); mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_attach_release(&state); return 0; } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 81baafaffc410..759d0e1126b30 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3285,9 +3285,9 @@ arm_smmu_master_build_invs(struct arm_smmu_master *ma= ster, bool ats_enabled, return master->build_invs; } =20 -static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, - struct iommu_domain *domain, - ioasid_t ssid) +static struct arm_smmu_master_domain * +arm_smmu_remove_master_domain(struct arm_smmu_master *master, + struct iommu_domain *domain, ioasid_t ssid) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain_devices(domain); struct arm_smmu_master_domain *master_domain; @@ -3295,7 +3295,7 @@ static void arm_smmu_remove_master_domain(struct arm_= smmu_master *master, unsigned long flags; =20 if (!smmu_domain) - return; + return NULL; =20 if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) nested_ats_flush =3D to_smmu_nested_domain(domain)->enable_ats; @@ -3310,8 +3310,24 @@ static void arm_smmu_remove_master_domain(struct arm= _smmu_master *master, } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 + /* arm_smmu_attach_release() will free it */ + return master_domain; +} + +/* Release the old master_domain detached by arm_smmu_remove_master_domain= () */ +void arm_smmu_attach_release(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_master_domain *master_domain =3D state->old_master_domain; + struct arm_smmu_master *master =3D state->master; + + iommu_group_mutex_assert(master->dev); + + if (!master_domain) + return; + arm_smmu_disable_iopf(master, master_domain); kfree(master_domain); + state->old_master_domain =3D NULL; } =20 /* @@ -3609,7 +3625,8 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_st= ate *state) arm_smmu_atc_inv_master(master, IOMMU_NO_PASID); } =20 - arm_smmu_remove_master_domain(master, state->old_domain, state->ssid); + state->old_master_domain =3D arm_smmu_remove_master_domain( + master, state->old_domain, state->ssid); arm_smmu_install_old_domain_invs(state); master->ats_enabled =3D state->ats_enabled; } @@ -3684,6 +3701,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, =20 arm_smmu_attach_commit(&state); mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_attach_release(&state); return 0; } =20 @@ -3766,8 +3784,10 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, =20 mutex_lock(&arm_smmu_asid_lock); ret =3D arm_smmu_attach_prepare(&state, &smmu_domain->domain); - if (ret) - goto out_unlock; + if (ret) { + mutex_unlock(&arm_smmu_asid_lock); + return ret; + } =20 /* * We don't want to obtain to the asid_lock too early, so fix up the @@ -3781,10 +3801,9 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, arm_smmu_update_ste(master, sid_domain, state.ats_enabled); =20 arm_smmu_attach_commit(&state); - -out_unlock: mutex_unlock(&arm_smmu_asid_lock); - return ret; + arm_smmu_attach_release(&state); + return 0; } =20 static int arm_smmu_blocking_set_dev_pasid(struct iommu_domain *new_domain, @@ -3804,9 +3823,11 @@ static int arm_smmu_blocking_set_dev_pasid(struct io= mmu_domain *new_domain, arm_smmu_clear_cd(master, pasid); if (master->ats_enabled) arm_smmu_atc_inv_master(master, pasid); - arm_smmu_remove_master_domain(master, &smmu_domain->domain, pasid); + state.old_master_domain =3D arm_smmu_remove_master_domain( + master, &smmu_domain->domain, pasid); arm_smmu_install_old_domain_invs(&state); mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_attach_release(&state); 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charset="utf-8" A queue position, the wrap bit combined with the index, is Q_WRP | Q_IDX. It is a (max_n_shift + 1)-bit value that wraps at twice the queue capacity. queue_inc_cons(), queue_sync_cons_ovf(), and queue_inc_prod_n() currently compute such positions by open-coding the two macros at each call site. Add a Q_POS() macro and switch the open-coded sites to it. A subsequent change will build a Q_DIFF() on it, to count the entries that a queue pointer moved past. No functional change intended. Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5b89bad71c102..de7e4284658a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -187,6 +187,8 @@ struct arm_vsmmu; =20 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) +/* A position is Q_WRP | Q_IDX, wrapping at twice the queue capacity */ +#define Q_POS(llq, p) (Q_WRP(llq, p) | Q_IDX(llq, p)) #define Q_OVERFLOW_FLAG (1U << 31) #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) #define Q_ENT(q, p) ((q)->base + \ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 759d0e1126b30..b908a8af31442 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -181,8 +181,8 @@ static void queue_sync_cons_out(struct arm_smmu_queue *= q) =20 static void queue_inc_cons(struct arm_smmu_ll_queue *q) { - u32 cons =3D (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; 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charset="utf-8" When a device leaves a domain, fault events for the old domain may remain in the SMMU event queue or the IOPF workqueue. If the IOMMU core frees that domain before those events are handled, the work may use freed memory. Start with the hardware queue by using arm_smmu_wait_for_queue_drained() to count entries consumed by the threaded IRQ handler, and poll the EVTQ when an IOPF-enabled attachment ends. This prevents a pending IRQ from queuing old-domain work after the drain. Its until_empty mode can drain the CMDQ as well during suspend and runtime PM. queue_poll() cannot be used because it is an atomic busy-wait that expects hardware to consume entries. The EVTQ and PRIQ are drained by threaded IRQ handlers, so a busy-wait could starve a handler sharing the same CPU on a non-preemptible kernel. The new helper sleeps, and might_sleep() catches an atomic-context caller even when the queue is already empty. Note that a drained event is dequeued, but not necessarily handled, since queue_remove_raw() moves the MMIO CONS before the threaded IRQ handler gets to push the event onto the IOPF workqueue. A subsequent change will invoke synchronize_irq() and iopf_queue_flush_dev() to close that gap, and it will act on the errno of a timed-out drain too. Fixes: cfea71aea921 ("iommu/arm-smmu-v3: Put iopf enablement in the domain = attach path") Cc: stable@vger.kernel.org # v6.16 Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 93 +++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index de7e4284658a1..21b00b9296b31 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -189,6 +189,8 @@ struct arm_vsmmu; #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) /* A position is Q_WRP | Q_IDX, wrapping at twice the queue capacity */ #define Q_POS(llq, p) (Q_WRP(llq, p) | Q_IDX(llq, p)) +/* Entries between two positions, i.e. how far @b leads @a */ +#define Q_DIFF(llq, a, b) Q_POS(llq, (b) - (a)) #define Q_OVERFLOW_FLAG (1U << 31) #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) #define Q_ENT(q, p) ((q)->base + \ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index b908a8af31442..ef1fddad7868e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -948,6 +948,89 @@ static int arm_smmu_cmdq_batch_submit(struct arm_smmu_= device *smmu, cmds->num, true); } =20 +/** + * arm_smmu_wait_for_queue_drained - Wait for an SMMU queue to be drained + * @smmu: the SMMU device + * @q: the queue to be drained + * @until_empty: target selection + * + * With @until_empty =3D=3D true (for CMDQ), exit once the queue is observ= ed empty: + * + * cons0 cons prod + * | | | + * ---+###################+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+---> + * |<--------- undrained=3D=3D0? --------->| + * + * With @until_empty =3D=3D false (for EVTQ/PRIQ), exit once "drained" rea= ches its + * target: "pending" (i.e. prod0 - cons0, frozen at the entry time): + * + * cons0 cons prod0 (prod) + * |<---- drained ---->| | | + * ---+###################+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+---> + * |<--------------- pending --------------->| + * + * Note that a drained entry is dequeued, but not necessarily handled: the + * EVTQ/PRIQ callers must follow up with a synchronize_irq() to wait for t= he + * threaded IRQ handler to finish handling the dequeued entries. + * + * Context: Process context; may sleep. + * Return: 0 on success or a negative errno on timeout. + */ +static int arm_smmu_wait_for_queue_drained(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, + bool until_empty) +{ + ktime_t timeout =3D ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); + u32 cons, prod, pending; + u32 drained =3D 0; + + might_sleep(); + + cons =3D readl_relaxed(q->cons_reg); + prod =3D readl_relaxed(q->prod_reg); + /* The exit target: the number of entries in the queue at entry */ + pending =3D Q_DIFF(&q->llq, cons, prod); + + while (true) { + u32 prev, undrained; + + /* Accumulate the entries consumed since the last poll */ + prev =3D cons; + cons =3D readl_relaxed(q->cons_reg); + drained +=3D Q_DIFF(&q->llq, prev, cons); + + prod =3D readl_relaxed(q->prod_reg); + undrained =3D Q_DIFF(&q->llq, cons, prod); + + /* Exit on an empty queue, regardless of until_empty */ + if (!undrained) + return 0; + + /* Snapshot mode: exit once the pending entries are drained */ + if (!until_empty && drained >=3D pending) + return 0; + + /* + * A timeout means the consumer might be stuck. In theory, if it + * moves 2 * qsize entries or more within a single poll interval + * Q_DIFF() will wrap and undercount drained: that could trigger + * a spurious warning too, if the queue was never once observed + * empty. Yet, that much consumption in such a short interval is + * unrealistic. + */ + if (ktime_compare(ktime_get(), timeout) > 0) + break; + + /* The consumer might be a threaded IRQ handler. Yield to it */ + fsleep(100); + } + + dev_warn_ratelimited(smmu->dev, + "queue drain timed out at prod=3D0x%x cons=3D0x%x\n", + prod, cons); + return -ETIMEDOUT; +} + static void arm_smmu_page_response(struct device *dev, struct iopf_fault *= unused, struct iommu_page_response *resp) { @@ -3318,12 +3401,22 @@ void arm_smmu_attach_release(struct arm_smmu_attach= _state *state) { struct arm_smmu_master_domain *master_domain =3D state->old_master_domain; struct arm_smmu_master *master =3D state->master; + struct arm_smmu_device *smmu =3D master->smmu; =20 + lockdep_assert_not_held(&arm_smmu_asid_lock); iommu_group_mutex_assert(master->dev); =20 if (!master_domain) return; =20 + /* + * In-flight fault work references the old domain via its attach handle, + * which the IOMMU core might free once this returns. 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charset="utf-8" After the hardware queue is drained, an event may still be moving from the IRQ thread to the IOPF workqueue, while earlier IOPF work is still running. Synchronize the EVTQ and combined IRQs, then call iopf_queue_flush_dev(). This finishes all old-domain work before the IOMMU core frees the domain. Skip synchronize_irq() after a drain timeout because a stuck consumer can otherwise leave it waiting forever. If arm_smmu_wait_for_queue_drained() times out, fault work may still be in flight, and iopf_queue_remove_device() would free iopf groups that the work also references. Skip the iopf teardown and leak the master_domain, rather than risk a use-after-free. The skip also leaks the iopf refcount, keeping the device enrolled on the IOPF queue, which would strand its fault parameter on the queue list once the device teardown frees dev->iommu, crashing a later iopf_queue_free(). Reclaim the enrollment in arm_smmu_release_device(), where all the attach handles are gone so a straggler report cannot queue a new fault group. Note that a residual race window remains between an iopf_queue_flush_dev() and iopf_queue_remove_device(): a fault arriving in between still resolves to the old attach handle, as the IOMMU core publishes a handle change only after the driver ops return. This window predates the drain narrowing it, and is only closable by an ordering fix in the IOMMU core. Furthermore, a timed-out drain shares exactly the same window, given that it must keep the device enrolled on the IOPF queue, where iopf_queue_remove_device() would free the iopf groups that any in-flight fault work still references. Fixes: cfea71aea921 ("iommu/arm-smmu-v3: Put iopf enablement in the domain = attach path") Cc: stable@vger.kernel.org # v6.16 Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 46 +++++++++++++++++++-- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ef1fddad7868e..a915d8b0baf69 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3402,6 +3402,7 @@ void arm_smmu_attach_release(struct arm_smmu_attach_s= tate *state) struct arm_smmu_master_domain *master_domain =3D state->old_master_domain; struct arm_smmu_master *master =3D state->master; struct arm_smmu_device *smmu =3D master->smmu; + bool timed_out =3D false; =20 lockdep_assert_not_held(&arm_smmu_asid_lock); iommu_group_mutex_assert(master->dev); @@ -3414,8 +3415,38 @@ void arm_smmu_attach_release(struct arm_smmu_attach_= state *state) * which the IOMMU core might free once this returns. Drain the hardware * eventq, so that a pending event cannot turn into new fault work. */ - if (master_domain->using_iopf && master->stall_enabled) - arm_smmu_wait_for_queue_drained(smmu, &smmu->evtq.q, false); + if (master_domain->using_iopf && master->stall_enabled) { + timed_out =3D arm_smmu_wait_for_queue_drained(smmu, &smmu->evtq.q, + false); + /* + * Ensure pending events have reached the IOPF queue, unless + * the drain timed out: a stuck consumer would also block an + * unbounded wait_event() inside the synchronize_irq(). + */ + if (!timed_out) { + if (smmu->evtq.q.irq) + synchronize_irq(smmu->evtq.q.irq); + /* Pending events might be in the combined_irq handler */ + if (smmu->combined_irq) + synchronize_irq(smmu->combined_irq); + } + } + + /* Lastly, flush the fault work that the drained events queued */ + if (master_domain->using_iopf) { + iopf_queue_flush_dev(master->dev); + + /* + * A timed-out drain may leave fault work in flight, and + * iopf_queue_remove_device() would free iopf groups that + * such work still references. Skip the iopf teardown and + * leak master_domain, rather than risk a UAF. + */ + if (WARN_ON(timed_out)) { + state->old_master_domain =3D NULL; + return; + } + } =20 arm_smmu_disable_iopf(master, master_domain); kfree(master_domain); @@ -4399,7 +4430,16 @@ static void arm_smmu_release_device(struct device *d= ev) { struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); =20 - WARN_ON(master->iopf_refcount); + /* + * A timed-out drain in arm_smmu_attach_release() leaks the refcount, + * keeping the device on the IOPF queue. Reclaim it here, since every + * attach handle is gone: a straggler fault can no longer queue a new + * fault group, so the queue turns stable once flushed. + */ + if (WARN_ON(master->iopf_refcount)) { + iopf_queue_flush_dev(dev); + iopf_queue_remove_device(master->smmu->evtq.iopf, dev); + } =20 arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); --=20 2.43.0 From nobody Fri Sep 25 15:13:22 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013062.outbound.protection.outlook.com [40.93.201.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 675273AA1A9; Thu, 10 Sep 2026 23:17:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789082278; cv=fail; b=m4w+pwF+YgEIxAhTQiXPaFem3c6UuzCHYRudjMSTKL1YPKo9OK9G5l8bkG15EIIEHSiuIzL5WaIFCchQGbYgzFNcZofJraTRMbzh/0kINjL6t4XHNDc5m0RVVCx94wJ0zPHd80NYhRxugLWfYp4GZgJ10LncUYmDfdQTxkKUxAo= ARC-Message-Signature: i=2; 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charset="utf-8" arm_smmu_init_queues() allocates the IOPF queue only for FEAT_SVA together with FEAT_STALLS. This queue has no SVA dependency, and FEAT_STALLS alone can produce events that need IOPF. On HW with FEAT_STALLS but no FEAT_SVA, a master with the "dma-can-stall" device-tree property has master->stall_enabled set at probe. Then also with CONFIG_ARM_SMMU_V3_SVA=3Dy, arm_smmu_enable_iopf() sees stall_enabled, calls iopf_queue_add_device(NULL, ...) at fault-handling domain attach, which can oops on mutex_lock(&queue->lock). Allocate the queue whenever FEAT_STALLS is present. Also select IOMMU_IOPF so iopf_queue_alloc() is always available without CONFIG_ARM_SMMU_V3_SVA. Since IOPF does not depend on SVA, drop the SVA guards from its enable and disable paths. Fixes: 395ad89d11fd9 ("iommu/arm-smmu-v3: Add stall support for platform de= vices") Cc: stable@vger.kernel.org # v5.14 Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Jonathan Cameron Signed-off-by: Nicolin Chen --- drivers/iommu/arm/Kconfig | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +-------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index 5fac08b89deea..b848a4253677d 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -78,6 +78,7 @@ config ARM_SMMU_V3 depends on ARM64 select IOMMU_API select IOMMU_IO_PGTABLE_LPAE + select IOMMU_IOPF select GENERIC_MSI_IRQ select IOMMUFD_DRIVER if IOMMUFD help diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a915d8b0baf69..8b7d88d469198 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3207,9 +3207,6 @@ static int arm_smmu_enable_iopf(struct arm_smmu_maste= r *master, =20 iommu_group_mutex_assert(master->dev); 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charset="utf-8" From: Malak Marrid To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() must issue a CMDQ_OP_PRI_RESP back to the SMMU. Both EVTQ stall events and PRIQ requests reach the IOPF layer with the same IOMMU_FAULT_PAGE_REQ, but these two fault models are mutually exclusive. A stalling master holds a transaction until CMDQ_OP_RESUME and has no reason to send a page request. A later patch rejects PRI for such a master, so the response command can be selected from stall_enabled or pri_enabled. Note that a CMD_PRI_RESP.Resp encodes 0b00 as ResponseFailure (a permanent non-paging error), 0b01 as InvalidRequest (page-in unsuccessful), and 0b10 as Success. So IOMMU_PAGE_RESP_FAILURE maps to PRI_RESP_DENY (0b00) while IOMMU_PAGE_RESP_INVALID maps to PRI_RESP_FAIL (0b01), following the codes rather than the similarity of the enum names. Extend arm_smmu_enable_iopf() to also proceed for a PRI-enabled master, so that attaching a fault-capable domain would set up IOPF for it. Note that a later change will set master->pri_enabled, once all PRI paths are ready. Note: streams[0].id remains the RID because arm_smmu_enable_iopf() rejects num_streams !=3D 1. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Reviewed-by: Jonathan Cameron Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++++++++------ 2 files changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 21b00b9296b31..558ba40f2f456 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1017,6 +1017,7 @@ struct arm_smmu_master { /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; + bool pri_enabled : 1; bool ats_enabled : 1; bool ste_ats_enabled : 1; bool stall_enabled; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8b7d88d469198..815847c2d7b43 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1031,32 +1031,68 @@ static int arm_smmu_wait_for_queue_drained(struct a= rm_smmu_device *smmu, return -ETIMEDOUT; } =20 -static void arm_smmu_page_response(struct device *dev, struct iopf_fault *= unused, +static void arm_smmu_page_response(struct device *dev, struct iopf_fault *= evt, struct iommu_page_response *resp) { struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); - u8 resume_resp; + struct arm_smmu_cmd cmd; + int sid; =20 - if (WARN_ON(!master->stall_enabled)) + if (WARN_ON_ONCE(evt->fault.type !=3D IOMMU_FAULT_PAGE_REQ)) return; =20 - switch (resp->code) { - case IOMMU_PAGE_RESP_INVALID: - case IOMMU_PAGE_RESP_FAILURE: - resume_resp =3D CMDQ_RESUME_0_RESP_ABORT; - break; - case IOMMU_PAGE_RESP_SUCCESS: - resume_resp =3D CMDQ_RESUME_0_RESP_RETRY; - break; - default: - resume_resp =3D CMDQ_RESUME_0_RESP_TERM; - break; + /* IOPF is gated to num_streams =3D=3D 1 in arm_smmu_enable_iopf() */ + sid =3D master->streams[0].id; + + if (master->stall_enabled) { + u8 resume_resp; + + switch (resp->code) { + case IOMMU_PAGE_RESP_INVALID: + case IOMMU_PAGE_RESP_FAILURE: + resume_resp =3D CMDQ_RESUME_0_RESP_ABORT; + break; + case IOMMU_PAGE_RESP_SUCCESS: + resume_resp =3D CMDQ_RESUME_0_RESP_RETRY; + break; + default: + resume_resp =3D CMDQ_RESUME_0_RESP_TERM; + break; + } + cmd =3D arm_smmu_make_cmd_resume(sid, resp->grpid, resume_resp); + } else if (master->pri_enabled) { + struct iommu_fault_page_request *prm =3D &evt->fault.prm; + enum pri_resp pri_resp; + bool ssv; + + /* PCIe allows only one PRG Response per group */ + if (!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) + return; + switch (resp->code) { + case IOMMU_PAGE_RESP_SUCCESS: + pri_resp =3D PRI_RESP_SUCC; + break; + case IOMMU_PAGE_RESP_FAILURE: + /* 0b00 ResponseFailure: a permanent non-paging error */ + pri_resp =3D PRI_RESP_DENY; + break; + case IOMMU_PAGE_RESP_INVALID: + /* 0b01 InvalidRequest: page-in unsuccessful */ + pri_resp =3D PRI_RESP_FAIL; + break; + default: + WARN_ON(true); + return; + } + ssv =3D !!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID); + cmd =3D arm_smmu_make_cmd_pri_resp(sid, resp->pasid, ssv, + resp->grpid, pri_resp); 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charset="utf-8" The EVTQ, PRIQ and combined IRQ handlers are threaded and issue commands of their own, e.g. a CMDQ_OP_PRI_RESP for a page request. Disabling the SMMU while one is in flight hands that command to a queue consuming nothing, so its poll waits out a full timeout. Two paths disable the SMMU while those IRQs are still requested: a failing arm_smmu_device_reset() returns to a probe that disables the device itself, and arm_smmu_disable_action() covers an unbind or any later probe failure. Both can run after arm_smmu_setup_irqs() requested the IRQs. Disable those IRQs first in both paths, so that no handler is left running once the SMMU goes down. arm_smmu_device_shutdown() needs no change of its own here, since it already just calls arm_smmu_disable_action(). Also clear an IRQ number when its request fails or is skipped for a missing ARM_SMMU_FEAT_PRI, keeping disable_irq() to the IRQs that this driver truly owns. Note that the IOPF queue needs no such care of its own, as devres frees the IRQs before running the release action of that queue, which came earlier in arm_smmu_init_queues(). Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++++++++++++--- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 815847c2d7b43..bd7615ce69581 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4906,8 +4906,10 @@ static void arm_smmu_setup_unique_irqs(struct arm_sm= mu_device *smmu) arm_smmu_evtq_thread, IRQF_ONESHOT, "arm-smmu-v3-evtq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable evtq irq\n"); + smmu->evtq.q.irq =3D 0; + } } else { dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); } @@ -4930,12 +4932,17 @@ static void arm_smmu_setup_unique_irqs(struct arm_s= mmu_device *smmu) IRQF_ONESHOT, "arm-smmu-v3-priq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable priq irq\n"); + smmu->priq.q.irq =3D 0; + } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); } + } else { + /* An unrequested IRQ (e.g. set by DT) must not be disabled */ + smmu->priq.q.irq =3D 0; } } =20 @@ -4963,8 +4970,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_devic= e *smmu) arm_smmu_combined_irq_thread, IRQF_ONESHOT, "arm-smmu-v3-combined-irq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); + smmu->combined_irq =3D 0; + } } else arm_smmu_setup_unique_irqs(smmu); =20 @@ -4991,10 +5000,22 @@ static int arm_smmu_device_disable(struct arm_smmu_= device *smmu) return ret; } =20 +/* Quiesce the queue IRQ threads, e.g. before disabling the SMMU */ +static void arm_smmu_disable_irqs(struct arm_smmu_device *smmu) +{ + if (smmu->combined_irq) + disable_irq(smmu->combined_irq); + if (smmu->evtq.q.irq) + disable_irq(smmu->evtq.q.irq); + if (smmu->priq.q.irq) + disable_irq(smmu->priq.q.irq); +} + static void arm_smmu_disable_action(void *data) { struct arm_smmu_device *smmu =3D data; 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charset="utf-8" arm_smmu_setup_irqs() can leave the PRIQ without any registered handler if its IRQ is missing, its request fails, or the combined IRQ request fails. These paths warn but leave ARM_SMMU_FEAT_PRI set. This function itself would then go on to enable IRQ_CTRL_PRIQ_IRQEN, even though no handler will drain the queue. A later patch also enables PRI on such endpoints. The caller already enabled CR0_PRIQEN before this function even runs. Clear ARM_SMMU_FEAT_PRI in all three failure paths, so that subsequent code treats PRI as unavailable. And disable CR0_PRIQEN after the setup function returns. A kdump kernel doesn't service page requests: strip FEAT_PRI when detecting features, so downstream PRI setup is skipped. Reviewed-by: Jonathan Cameron Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index bd7615ce69581..43a6029cef430 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4936,9 +4936,11 @@ static void arm_smmu_setup_unique_irqs(struct arm_sm= mu_device *smmu) dev_warn(smmu->dev, "failed to enable priq irq\n"); smmu->priq.q.irq =3D 0; + smmu->features &=3D ~ARM_SMMU_FEAT_PRI; } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); + smmu->features &=3D ~ARM_SMMU_FEAT_PRI; } } else { /* An unrequested IRQ (e.g. set by DT) must not be disabled */ @@ -4973,6 +4975,7 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device= *smmu) if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); smmu->combined_irq =3D 0; + smmu->features &=3D ~ARM_SMMU_FEAT_PRI; } } else arm_smmu_setup_unique_irqs(smmu); @@ -5153,6 +5156,10 @@ static int arm_smmu_device_reset(struct arm_smmu_dev= ice *smmu) return ret; } =20 + /* arm_smmu_setup_irqs() might have unset the ARM_SMMU_FEAT_PRI */ + if (!(smmu->features & ARM_SMMU_FEAT_PRI)) + enables &=3D ~CR0_PRIQEN; + if (is_kdump_kernel()) enables &=3D ~(CR0_EVTQEN | CR0_PRIQEN); =20 @@ -5294,7 +5301,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_d= evice *smmu) } =20 /* Boolean feature flags */ - if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) + if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI && !is_kdump_kernel()) smmu->features |=3D ARM_SMMU_FEAT_PRI; =20 if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) --=20 2.43.0 From nobody Fri Sep 25 15:13:22 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013031.outbound.protection.outlook.com [40.107.201.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF82E39CCE3; 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charset="utf-8" For a PRI-enabled master, convert every PRIQ entry into an iopf_fault and report it through iommu_report_device_fault(). For an unknown StreamID or a master without PRI enabled, keep the existing LAST-page DENY path. Merge its two messages into one ratelimited line so a faulty device cannot flood the kernel log. Discard any PASID Stop Marker (LRW =3D 0b100) prior to the fault report and the DENY fallback both, because a Stop Marker does not expect a response. The IOPF infrastructure requires the driver to discard it, as per the doc at iommu_report_device_fault(). This also matches the intel-iommu code. Note that master->pri_enabled will only be set by a later change, once all the PRI paths are ready. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 43a6029cef430..c631c6344685d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2370,6 +2370,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void= *dev) =20 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) { + struct arm_smmu_master *master; u32 sid, ssid; u16 grpid; bool ssv, last; @@ -2380,9 +2381,47 @@ static void arm_smmu_handle_ppr(struct arm_smmu_devi= ce *smmu, u64 *evt) last =3D FIELD_GET(PRIQ_0_PRG_LAST, evt[0]); grpid =3D FIELD_GET(PRIQ_1_PRG_IDX, evt[1]); =20 - dev_info(smmu->dev, "unexpected PRI request received:\n"); - dev_info(smmu->dev, - "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016l= lx\n", + /* + * A PASID Stop Marker (LRW =3D 0b100) does not expect a response and + * must be discarded before fault reporting: see the documentation + * at iommu_report_device_fault(). + */ + if (last && !(evt[0] & (PRIQ_0_PERM_READ | PRIQ_0_PERM_WRITE))) + return; + + mutex_lock(&smmu->streams_mutex); + master =3D arm_smmu_find_master(smmu, sid); + if (master && master->pri_enabled) { + struct iopf_fault iopf_fault =3D {}; + struct iommu_fault *fault =3D &iopf_fault.fault; + + fault->type =3D IOMMU_FAULT_PAGE_REQ; + if (last) + fault->prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + if (ssv) { + fault->prm.flags |=3D + IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + fault->prm.pasid =3D ssid; + } + fault->prm.grpid =3D grpid; + if (evt[0] & PRIQ_0_PERM_READ) + fault->prm.perm |=3D IOMMU_FAULT_PERM_READ; + if (evt[0] & PRIQ_0_PERM_WRITE) + fault->prm.perm |=3D IOMMU_FAULT_PERM_WRITE; + if (evt[0] & PRIQ_0_PERM_EXEC) + fault->prm.perm |=3D IOMMU_FAULT_PERM_EXEC; + if (evt[0] & PRIQ_0_PERM_PRIV) + fault->prm.perm |=3D IOMMU_FAULT_PERM_PRIV; + fault->prm.addr =3D FIELD_GET(PRIQ_1_ADDR_MASK, evt[1]) << 12; + + iommu_report_device_fault(master->dev, &iopf_fault); + mutex_unlock(&smmu->streams_mutex); + return; + } + mutex_unlock(&smmu->streams_mutex); + + dev_info_ratelimited(smmu->dev, + "unexpected PRI request: sid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s = access at iova 0x%016llx\n", sid, ssid, grpid, last ? "L" : "", evt[0] & PRIQ_0_PERM_PRIV ? "" : "un", evt[0] & PRIQ_0_PERM_READ ? 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charset="utf-8" On PRIQ overflow, partial requests stored via report_partial_fault() whose LAST-page entry was lost stay in iopf_param->partial. Drop them by calling iopf_queue_discard_partial(), matching intel-iommu's handling. Do it only after the queue is fully drained, since the visible entries all precede the loss point: a group whose LAST-page entry is still in the queue gets assembled before the discard, rather than losing its stored partials to it. Nothing can arrive in between, as an active overflow inhibits new entries from being written to the PRI queue until a final CONS write acknowledges it (IHI0070 8.1). Suggested-by: Harsha Vardhan V Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c631c6344685d..0a15556c9a558 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2441,15 +2441,27 @@ static irqreturn_t arm_smmu_priq_thread(int irq, vo= id *dev) struct arm_smmu_queue *q =3D &smmu->priq.q; struct arm_smmu_ll_queue *llq =3D &q->llq; u64 evt[PRIQ_ENT_DWORDS]; + bool overflow =3D false; =20 do { while (!queue_remove_raw(q, evt)) arm_smmu_handle_ppr(smmu, evt); =20 - if (queue_sync_prod_in(q) =3D=3D -EOVERFLOW) + if (queue_sync_prod_in(q) =3D=3D -EOVERFLOW) { dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); + overflow =3D true; + } } while (!queue_empty(llq)); =20 + /* + * Discard the partial faults after the drain, so any group with its + * LAST-page entry visible in the queue gets assembled beforehand. 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charset="utf-8" After the previous change drops the FEAT_SVA gate, arm_smmu_init_queues() allocates smmu->evtq.iopf when the SMMU advertises FEAT_STALLS. PRI support is being added on top of the IOPF infrastructure, so extend the allocation condition to cover SMMUs that advertise FEAT_PRI without FEAT_STALLS. Reviewed-by: Jonathan Cameron Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 0a15556c9a558..3cc2d365d2d66 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4740,7 +4740,7 @@ static int arm_smmu_init_queues(struct arm_smmu_devic= e *smmu) if (ret) return ret; =20 - if (smmu->features & ARM_SMMU_FEAT_STALLS) { + if (smmu->features & (ARM_SMMU_FEAT_STALLS | ARM_SMMU_FEAT_PRI)) { smmu->evtq.iopf =3D iopf_queue_alloc(dev_name(smmu->dev)); if (!smmu->evtq.iopf) return -ENOMEM; --=20 2.43.0 From nobody Fri Sep 25 15:13:22 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010008.outbound.protection.outlook.com [52.101.193.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D60CD2DCF74; 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charset="utf-8" From: Jean-Philippe Brucker The SMMUv3 driver, which may be built without CONFIG_PCI, will shortly gain PRI support. Partially revert commit c6e9aefbf9db ("PCI/ATS: Remove unused PRI and PASID stubs") to re-introduce the PRI stubs, avoiding more #ifdefs in the SMMU driver. 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charset="utf-8" From: Jean-Philippe Brucker Export pci_enable_pri() and pci_reset_pri() so the SMMUv3 driver, which is tristate, can use them from its probe path when built as a module. Link: https://lore.kernel.org/iommu/20201112125519.3987595-9-jean-philippe@= linaro.org/ Acked-by: Bjorn Helgaas Reviewed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Jean-Philippe Brucker [nicolinc: drop stale or already-exported APIs] Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/pci/ats.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 9cb23780093dd..b6de3c858d390 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -320,6 +320,7 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs) =20 return 0; } +EXPORT_SYMBOL_GPL(pci_enable_pri); =20 /** * pci_disable_pri - Disable PRI capability @@ -399,6 +400,7 @@ int pci_reset_pri(struct pci_dev *pdev) =20 return 0; } +EXPORT_SYMBOL_GPL(pci_reset_pri); =20 /** * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit --=20 2.43.0 From nobody Fri Sep 25 15:13:22 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011012.outbound.protection.outlook.com [52.101.62.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 970CB3A7F45; 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charset="utf-8" PRI handling is now ready. Enable PRI when probing a PCI device, and drain the PRIQ with the EVTQ when an IOPF-enabled attachment ends. Queued fault work may still refer to the old domain when the detach call returns. Note that PRI is enabled at the probe time, while ATS gets toggled by the attach/detach routines, so a master could have PRI enabled when its ATS is disabled. PCIe (Base 6.3, Table 10-14) sets no ATS precondition on the PRI Enable bit. Its only ordering rule is that the interface must have gotten successfully Stopped prior to an enabling, which pci_enable_pri() already checks using PCI_PRI_STATUS_STOPPED. Also, a PRI-enabled device would not issue a page request until it starts to use ATS. Set the per-device outstanding request budget to the full priq depth, same as intel-iommu's per-device PRQ_DEPTH choice. A fixed per-device cap won't prevent multiple PRI-capable devices from potentially exceeding the priq's capacity; priq overflow is recoverable per the SMMUv3 spec, and it is rare in practice. Select PCI_PRI in Kconfig like other IOMMUs, gated on PCI so the build can stay clean for non-PCI ARM SMMUv3 configurations. A stalling master resolves its faults synchronously, so it has no reason at all to issue a page request. Refuse to enable PRI on such a master, so that page_response() can keep dispatching on the master state unambiguously. Refuse to enable PRI as well on any master reporting num_streams !=3D 1, as arm_smmu_enable_iopf() rejects multi-stream masters, so IOPF cannot be set up for them; keeping PRI enabled would let a PRI request arrive on an alias StreamID and get a PRI_RESP_DENY issued against streams[0] by the driver's error-response path. Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron --- drivers/iommu/arm/Kconfig | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 52 +++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index b848a4253677d..a31d04f5b031a 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -80,6 +80,7 @@ config ARM_SMMU_V3 select IOMMU_IO_PGTABLE_LPAE select IOMMU_IOPF select GENERIC_MSI_IRQ + select PCI_PRI if PCI select IOMMUFD_DRIVER if IOMMUFD help Support for implementations of the ARM System MMU architecture diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 3cc2d365d2d66..104b0e008eb7f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3513,6 +3513,20 @@ void arm_smmu_attach_release(struct arm_smmu_attach_= state *state) } } =20 + /* Same as the eventq drain above, for the hardware priq */ + if (master_domain->using_iopf && master->pri_enabled) { + timed_out |=3D arm_smmu_wait_for_queue_drained( + smmu, &smmu->priq.q, false); + /* Ensure pending requests have reached the IOPF queue */ + if (!timed_out) { + if (smmu->priq.q.irq) + synchronize_irq(smmu->priq.q.irq); + /* Pending requests might be in the combined_irq handler */ + if (smmu->combined_irq) + synchronize_irq(smmu->combined_irq); + } + } + /* Lastly, flush the fault work that the drained events queued */ if (master_domain->using_iopf) { iopf_queue_flush_dev(master->dev); @@ -4445,6 +4459,40 @@ static int arm_smmu_master_prepare_ats(struct arm_sm= mu_master *master) return arm_smmu_alloc_cd_tables(master); } =20 +static void arm_smmu_master_enable_pri(struct arm_smmu_master *master) +{ + struct arm_smmu_device *smmu =3D master->smmu; + struct pci_dev *pdev; + unsigned int reqs; + + if (!(smmu->features & ARM_SMMU_FEAT_PRI) || !smmu->evtq.iopf) + return; + if (!dev_is_pci(master->dev)) + return; + pdev =3D to_pci_dev(master->dev); + + if (!pci_pri_supported(pdev)) + return; + + /* A stalling master resolves its faults without any page request */ + if (master->stall_enabled) { + pci_warn(pdev, "stall enabled, skip PRI\n"); + return; + } + + if (master->num_streams !=3D 1) { + pci_warn(pdev, "multi-SID master, skip PRI\n"); + return; + } + + reqs =3D 1 << smmu->priq.q.llq.max_n_shift; + + if (!pci_reset_pri(pdev) && !pci_enable_pri(pdev, reqs)) + master->pri_enabled =3D true; + else + pci_warn(pdev, "failed to enable PRI\n"); +} + static struct iommu_device *arm_smmu_probe_device(struct device *dev) { int ret; @@ -4497,6 +4545,8 @@ static struct iommu_device *arm_smmu_probe_device(str= uct device *dev) if (ret) goto err_disable_pasid; =20 + arm_smmu_master_enable_pri(master); + return &smmu->iommu; =20 err_disable_pasid: @@ -4522,6 +4572,8 @@ static void arm_smmu_release_device(struct device *de= v) iopf_queue_remove_device(master->smmu->evtq.iopf, dev); } =20 + if (master->pri_enabled) + pci_disable_pri(to_pci_dev(master->dev)); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); if (arm_smmu_cdtab_allocated(&master->cd_table)) --=20 2.43.0