From nobody Fri Sep 25 17:42:21 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012026.outbound.protection.outlook.com [40.107.200.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F9D63769E9 for ; Thu, 10 Sep 2026 03:34:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.26 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011263; cv=fail; b=W0LodF0ph5qunag+e0pkXSdYGtmlunXphvkuI2XxD2v9UVdiB6Yp7ZoD7OWUrvLbgVIJkouLNT9auhvQRdJJNtL5j8YMI2LNnQrdyvgZCS4sG/QfEC/0rzFFi7CwYHGMDX2ESmenQj+leCK98zMrgzBD0i7Rwfcda/t+kSzEUKg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011263; c=relaxed/simple; bh=qRZGKKkpkQO5wpSTuJTkY33V4jgkGspvyUpfOO7QugY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qYoqNNq0bVInPZzY9ra12BLBN2asuvSZL1DDATkCdzQ9ztx+DrOUr0pw8j48K5qc6XBHKS0JKGQnXDIVEy+VcZ4Nw3jjOEXnM0CqNGKVG/zUpKhhBa7YZBimpmRdWUa0h9v6DAYxejOYGDpVysKPJdCA7jPBJjwcqMWLAeW3TuM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=k43BJ9TG; arc=fail smtp.client-ip=40.107.200.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="k43BJ9TG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wAfn8euJemwK5JsuPJ6MF3bo9Cy5/gcou9XE1dRF2/G/8R8g6Mk4nEyGWRjvtwD3tB87oGsTn2DR5uttpbI5fYLtx4Vti0JjQ4pLjyeJJBXEPM7prmsrErBB6TDQYT+32v02vl46msZR0hL7Jg4F0cKy+Qf17nD+W1pan+vZLMSW38j/2N8cH3ny9GFcbY9mTy+OpJe/aNwBl4t9hEqfgFN/QJ9AoulmMtHqehV0t6QbmQKLL0xgverwYWatdAsbwspIaXU4JRbLvA7+Xh8HSF2J3dHOmgdiDYiBxrju2z22HVpiCYjC4gYIGun97K/Py0AeVeybsnI16SlOXoNChQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/RT5MEi13NhbvUpXcVj6ZnkJ1EuOtEu5fTTf6U9AFwY=; b=HjE4beabFno87b60PZs2f2/qmI69O6i/Fh4lf6D2b3OgS7ERVpgUoc+Z3FTBlPzhLY7Vh91F9WMUTWQyZTuOSR5jGPH5GMaDGetHMzwKwOx64cugPrkFdzZMaCBTMpPHIgNBF0jj77DGmFGBg6Me6bnXaz/JdKLzXWQJn8DCHDoLRmrLlI+zvHBi/OTRDt6aARjJ6aHae7AmXKh1W5ZlCSoiniKX3XUDp/Etx+UaxtHOdMdDTlNhnaW2btw29J+UUBiTG34YOUsaoIV3zfz7s/SdDE4iHq+lzRy7oGUOfOgJedlTBO291fvH4psHyB8nJPEfdpfwGPABZ1E4bz0yvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/RT5MEi13NhbvUpXcVj6ZnkJ1EuOtEu5fTTf6U9AFwY=; b=k43BJ9TGviEdVfc0/Er+lkPT/AhcmHh+3qmh+i7ZGaxbB5eMZjBMtFbzNWalRC5orOXrmcxNYSXybQYTCGRUH+A8dOJTZijLyWhRIIFWCMcIkXNGuQbTN9vyrew0cKWkU7Bd+cyHC44VRkmDAkbbPtggIXJxNaR5fw/p2yNYKqn10uAEKOtPLtZgoavrvrAM0WPPqEcEzTcKEGxVy/+awhtoKE5XMoxjI06m/k7YfLrzqSF0mlb+b8lyddpN0as00Scjgq+MEffikKGh6BW0K3yH52w7Gl8I7QXHbzLVwCShSrvB6RHH/P6UMXF3yDjsA1k5zG/euyli0Yo7fGtAeg== Received: from SJ0PR05CA0183.namprd05.prod.outlook.com (2603:10b6:a03:330::8) by SN7PR12MB8025.namprd12.prod.outlook.com (2603:10b6:806:340::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.7; Thu, 10 Sep 2026 03:34:07 +0000 Received: from SJ1PEPF00002315.namprd03.prod.outlook.com (2603:10b6:a03:330:cafe::8) by SJ0PR05CA0183.outlook.office365.com (2603:10b6:a03:330::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.406.7 via Frontend Transport; Thu, 10 Sep 2026 03:34:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00002315.mail.protection.outlook.com (10.167.242.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:07 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:33:59 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:33:59 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:33:57 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 1/8] firmware: arm_rmm: Move RSI support out of arch/arm64 Date: Wed, 9 Sep 2026 20:32:44 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002315:EE_|SN7PR12MB8025:EE_ X-MS-Office365-Filtering-Correlation-Id: ae6d58e8-d2b7-49f4-404d-08df0eec5ebf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|30052699003|7416014|1800799024|376014|82310400026|5023799004|11063799006|56012099006|10067099003|13003099007|6133799003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: r/fa+oFUbSNZZs8cyVrrkiL84Je+RJf94CrUveU773Ljs43RzkuNZUTCXKANfi2lzFpKelpN5i7R/16ZagZ5N/Gn5rMEblh7THWGOVtOYNrqj8z9zDYr+iAgF7pab+KpM5UrDK8e67Vor+VkO49wikoRfdWDnEYFg6ck0n+5owrqhYj7G1OyFqFZfe2fejB84RdmUhwedsbLrsyaki6a8IKsnb0khLTWpv/opX3DMv6yljlJwgv1mdl1iIRRC4cEElyF7P24KYnC2NPVOr4DWo3QKVRhTkQ0eV7cPmvGGj4KxQLTf50/6Kgy8PVGf4qZiZiGopOdmAFTkA/92oYFzUgsEiZhZQaisqGOq4+WGWSlsmoOuWH8MRCMGB8Tx1IGQZoPQ8NyKuZvvVXOM+thM+eFxa/6zIX2RlOgmI/gvNeFOVMeDNFwkIad3Y7URiBYfR8eY+n3huCyNuVromIvFeOgFWDxOp0TIGuj5WB6QZR8uNhFVgX3pJQ3+e8MOGaktX8XIgsoCrg+Ny48IitjvfUrDAPCKOfRu76cNfxX+ln54xv8gxAfZnT6HSBDx23Rns6PmvynkYRF2TED568IsJ2XkyYj0z7T/6mg4HYB2RGFaSOUlwjq7G4+KOFcFcLqn03cN5VcC4RSsPKcmcCgOwAS5SzoTqzNiXetya1YwSeec6QN2IUi4ZvgWyRrWnE6Y4kr49RR0aUDLhg5NP5hiw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(30052699003)(7416014)(1800799024)(376014)(82310400026)(5023799004)(11063799006)(56012099006)(10067099003)(13003099007)(6133799003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vCRWX9k8bbnSWTqlZNZIHMyy5v80RqAEb8oYm4+OEq7A/5SlWWgJW6P3VpoVIGjqHsNXXskC97ll+WN1ZJ7njmZUIJ9AC9KVmZhIIANOEHesosmzn1ATo8Kep23VSeW1IdgDwVgqKvuJcxbGAVNxuiqybLx9DByrcYTVDyITKTLg1ZNp9Te61/FAdgD5QwcGzagzV2byZs9EkI799Rwr/5nSpZgiEygZVQCZGwLwRhPQasKbCdb7qCaZatkeh0lgQdsk4nYF/Exv2vGc0NsXt6RqrLsY0j3i5MQccpOGFiv6q8HMFLaPYcmfi6yIs1BW82Su6pbDI8QpVkIPaMr3kLdHRVAc5FHJCxJL0bASLvfeyLzKvGvUKanZgPvvoLosumlfhHiJjpn8eeBqN/3CW5KZaQbvu2TXkMYRY/wMo0d2dpT2XWMB9otUN2kI94C8 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:07.4253 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae6d58e8-d2b7-49f4-404d-08df0eec5ebf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002315.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8025 Content-Type: text/plain; charset="utf-8" From: "Aneesh Kumar K.V (Arm)" The RSI SMCCC function IDs describe a firmware ABI and are not arm64 architecture specific definitions. Follow-up changes need to use them from non-arch code, including drivers/firmware/smccc and the Arm CCA guest driver. Move the complete Realm Service Interface (RSI) implementation from arch/arm64 to drivers/firmware/arm_rmm. The RSI SMCCC definitions and command helpers are also moved to include/linux so they can be shared by architecture code and firmware or driver code. This also keeps the firmware interface outside architecture code, as requested [1]. [1] https://lore.kernel.org/all/agsNO9cc7H-b0H8L@willie-the-truck Signed-off-by: Aneesh Kumar K.V (Arm) Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- arch/arm64/Kconfig | 1 + drivers/firmware/Kconfig | 1 + drivers/firmware/arm_rmm/Kconfig | 18 +++++ drivers/virt/coco/arm-cca-guest/Kconfig | 2 +- arch/arm64/kernel/Makefile | 2 +- drivers/firmware/Makefile | 1 + drivers/firmware/arm_rmm/Makefile | 2 + arch/arm64/include/asm/io.h | 2 +- arch/arm64/include/asm/mem_encrypt.h | 2 +- arch/arm64/include/asm/pgtable-prot.h | 2 +- arch/arm64/include/asm/rsi.h | 70 ----------------- .../linux/arm-rsi-cmds.h | 77 +++++++++++++++++-- .../linux/arm-smccc-rsi.h | 6 +- arch/arm64/kernel/setup.c | 2 +- arch/arm64/mm/init.c | 3 +- .../kernel =3D> drivers/firmware/arm_rmm}/rsi.c | 2 +- .../virt/coco/arm-cca-guest/arm-cca-guest.c | 5 +- 17 files changed, 109 insertions(+), 89 deletions(-) create mode 100644 drivers/firmware/arm_rmm/Kconfig create mode 100644 drivers/firmware/arm_rmm/Makefile delete mode 100644 arch/arm64/include/asm/rsi.h rename arch/arm64/include/asm/rsi_cmds.h =3D> include/linux/arm-rsi-cmds.h= (69%) rename arch/arm64/include/asm/rsi_smc.h =3D> include/linux/arm-smccc-rsi.h= (98%) rename {arch/arm64/kernel =3D> drivers/firmware/arm_rmm}/rsi.c (99%) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b5a51b0ef9440..ff9565d3ffa59 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -38,6 +38,7 @@ config ARM64 select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_MEM_ENCRYPT select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS + select ARCH_SUPPORTS_RMM select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index b7cc11e4fbfa6..62660bf520a8d 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -310,5 +310,6 @@ source "drivers/firmware/samsung/Kconfig" source "drivers/firmware/smccc/Kconfig" source "drivers/firmware/tegra/Kconfig" source "drivers/firmware/xilinx/Kconfig" +source "drivers/firmware/arm_rmm/Kconfig" =20 endmenu diff --git a/drivers/firmware/arm_rmm/Kconfig b/drivers/firmware/arm_rmm/Kc= onfig new file mode 100644 index 0000000000000..1322a1447b560 --- /dev/null +++ b/drivers/firmware/arm_rmm/Kconfig @@ -0,0 +1,18 @@ + +config ARCH_SUPPORTS_RMM + bool + +config ARM_RMM + bool "Realm Management Monitor (RMM) Support" + depends on ARCH_SUPPORTS_RMM + default y + help + Support the Realm Management Monitor (RMM) on Arm systems that + implement the Realm Management Extension (RME), as defined by the + Arm Confidential Compute Architecture. + + The RMM provides the Realm Management Interface (RMI) for use by + the Normal World host and the Realm Service Interface (RSI) for + use by Realm guests. The RSI is used to negotiate the RSI version + and Realm configuration with the RMM and manage the protected + state of memory. diff --git a/drivers/virt/coco/arm-cca-guest/Kconfig b/drivers/virt/coco/ar= m-cca-guest/Kconfig index 3f0f013f03f15..b2c225fd445cf 100644 --- a/drivers/virt/coco/arm-cca-guest/Kconfig +++ b/drivers/virt/coco/arm-cca-guest/Kconfig @@ -1,6 +1,6 @@ config ARM_CCA_GUEST tristate "Arm CCA Guest driver" - depends on ARM64 + depends on ARM_RMM select TSM_REPORTS help The driver provides userspace interface to request and diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index d2690c3ec5288..21fc3a3d25c91 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -34,7 +34,7 @@ obj-y :=3D debug-monitors.o entry.o irq.o fpsimd.o \ cpufeature.o alternative.o cacheinfo.o \ smp.o smp_spin_table.o topology.o smccc-call.o \ syscall.o proton-pack.o idle.o patching.o pi/ \ - rsi.o jump_label.o + jump_label.o =20 obj-$(CONFIG_COMPAT) +=3D sys32.o signal32.o \ sys_compat.o diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index be46f1e1dc77f..196a650ccf025 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -39,3 +39,4 @@ obj-y +=3D samsung/ obj-y +=3D smccc/ obj-y +=3D tegra/ obj-y +=3D xilinx/ +obj-y +=3D arm_rmm/ diff --git a/drivers/firmware/arm_rmm/Makefile b/drivers/firmware/arm_rmm/M= akefile new file mode 100644 index 0000000000000..3d8181ae94a7b --- /dev/null +++ b/drivers/firmware/arm_rmm/Makefile @@ -0,0 +1,2 @@ + +obj-$(CONFIG_ARM_RMM) =3D rsi.o diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 49a7002661a92..1620537f0332d 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -8,6 +8,7 @@ #ifndef __ASM_IO_H #define __ASM_IO_H =20 +#include #include #include =20 @@ -17,7 +18,6 @@ #include #include #include -#include =20 /* * Generic IO read/write. These perform native-endian accesses. diff --git a/arch/arm64/include/asm/mem_encrypt.h b/arch/arm64/include/asm/= mem_encrypt.h index 636f45b4d8afc..f03b9d7b83b43 100644 --- a/arch/arm64/include/asm/mem_encrypt.h +++ b/arch/arm64/include/asm/mem_encrypt.h @@ -2,8 +2,8 @@ #ifndef __ASM_MEM_ENCRYPT_H #define __ASM_MEM_ENCRYPT_H =20 +#include #include -#include =20 struct device; =20 diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm= /pgtable-prot.h index 09d7c00cf4054..58e71e592175e 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -66,9 +66,9 @@ =20 #ifndef __ASSEMBLER__ =20 +#include #include #include -#include =20 extern bool arm64_use_ng_mappings; extern unsigned long prot_ns_shared; diff --git a/arch/arm64/include/asm/rsi.h b/arch/arm64/include/asm/rsi.h deleted file mode 100644 index 88b50d660e85a..0000000000000 --- a/arch/arm64/include/asm/rsi.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2024 ARM Ltd. - */ - -#ifndef __ASM_RSI_H_ -#define __ASM_RSI_H_ - -#include -#include -#include - -#define RSI_PDEV_NAME "arm-cca-dev" - -DECLARE_STATIC_KEY_FALSE(rsi_present); - -void __init arm64_rsi_init(void); - -bool arm64_rsi_is_protected(phys_addr_t base, size_t size); - -static inline bool is_realm_world(void) -{ - return static_branch_unlikely(&rsi_present); -} - -static inline int rsi_set_memory_range(phys_addr_t start, phys_addr_t end, - enum ripas state, unsigned long flags) -{ - unsigned long ret; - phys_addr_t top; - - while (start !=3D end) { - ret =3D rsi_set_addr_range_state(start, end, state, flags, &top); - if (ret || top < start || top > end) - return -EINVAL; - start =3D top; - } - - return 0; -} - -/* - * Convert the specified range to RAM. Do not use this if you rely on the - * contents of a page that may already be in RAM state. - */ -static inline int rsi_set_memory_range_protected(phys_addr_t start, - phys_addr_t end) -{ - return rsi_set_memory_range(start, end, RSI_RIPAS_RAM, - RSI_CHANGE_DESTROYED); -} - -/* - * Convert the specified range to RAM. Do not convert any pages that may h= ave - * been DESTROYED, without our permission. - */ -static inline int rsi_set_memory_range_protected_safe(phys_addr_t start, - phys_addr_t end) -{ - return rsi_set_memory_range(start, end, RSI_RIPAS_RAM, - RSI_NO_CHANGE_DESTROYED); -} - -static inline int rsi_set_memory_range_shared(phys_addr_t start, - phys_addr_t end) -{ - return rsi_set_memory_range(start, end, RSI_RIPAS_EMPTY, - RSI_CHANGE_DESTROYED); -} -#endif /* __ASM_RSI_H_ */ diff --git a/arch/arm64/include/asm/rsi_cmds.h b/include/linux/arm-rsi-cmds= .h similarity index 69% rename from arch/arm64/include/asm/rsi_cmds.h rename to include/linux/arm-rsi-cmds.h index c1fab41f671ec..13478e14c4296 100644 --- a/arch/arm64/include/asm/rsi_cmds.h +++ b/include/linux/arm-rsi-cmds.h @@ -3,14 +3,36 @@ * Copyright (C) 2023 ARM Ltd. */ =20 -#ifndef __ASM_RSI_CMDS_H -#define __ASM_RSI_CMDS_H +#ifndef __LINUX_ARM_RSI_CMDS_H_ +#define __LINUX_ARM_RSI_CMDS_H_ =20 -#include +#include +#include #include #include =20 -#include +#define RSI_PDEV_NAME "arm-cca-dev" +#ifdef CONFIG_ARM_RMM +DECLARE_STATIC_KEY_FALSE(rsi_present); + +void __init arm64_rsi_init(void); + +bool arm64_rsi_is_protected(phys_addr_t base, size_t size); + +static inline bool is_realm_world(void) +{ + return static_branch_unlikely(&rsi_present); +} +#else +static inline void arm64_rsi_init(void) { } + +static inline bool arm64_rsi_is_protected(phys_addr_t base, size_t size) +{ + return false; +} + +static inline bool is_realm_world(void) { return false; } +#endif =20 #define RSI_GRANULE_SHIFT 12 #define RSI_GRANULE_SIZE (_AC(1, UL) << RSI_GRANULE_SHIFT) @@ -88,6 +110,51 @@ static inline long rsi_set_addr_range_state(phys_addr_t= start, return res.a0; } =20 +static inline int rsi_set_memory_range(phys_addr_t start, phys_addr_t end, + enum ripas state, unsigned long flags) +{ + unsigned long ret; + phys_addr_t top; + + while (start !=3D end) { + ret =3D rsi_set_addr_range_state(start, end, state, flags, &top); + if (ret || top < start || top > end) + return -EINVAL; + start =3D top; + } + + return 0; +} + +/* + * Convert the specified range to RAM. Do not use this if you rely on the + * contents of a page that may already be in RAM state. + */ +static inline int rsi_set_memory_range_protected(phys_addr_t start, + phys_addr_t end) +{ + return rsi_set_memory_range(start, end, RSI_RIPAS_RAM, + RSI_CHANGE_DESTROYED); +} + +/* + * Convert the specified range to RAM. Do not convert any pages that may h= ave + * been DESTROYED, without our permission. + */ +static inline int rsi_set_memory_range_protected_safe(phys_addr_t start, + phys_addr_t end) +{ + return rsi_set_memory_range(start, end, RSI_RIPAS_RAM, + RSI_NO_CHANGE_DESTROYED); +} + +static inline int rsi_set_memory_range_shared(phys_addr_t start, + phys_addr_t end) +{ + return rsi_set_memory_range(start, end, RSI_RIPAS_EMPTY, + RSI_CHANGE_DESTROYED); +} + #define RSI_ATTEST_CHALLENGE_MIN_SIZE 32 #define RSI_ATTEST_CHALLENGE_MAX_SIZE 64 =20 @@ -170,4 +237,4 @@ static inline unsigned long rsi_attestation_token_conti= nue(phys_addr_t granule, return res.a0; } =20 -#endif /* __ASM_RSI_CMDS_H */ +#endif /* __LINUX_ARM_RSI_CMDS_H_ */ diff --git a/arch/arm64/include/asm/rsi_smc.h b/include/linux/arm-smccc-rsi= .h similarity index 98% rename from arch/arm64/include/asm/rsi_smc.h rename to include/linux/arm-smccc-rsi.h index e19253f96c940..fddb77986f706 100644 --- a/arch/arm64/include/asm/rsi_smc.h +++ b/include/linux/arm-smccc-rsi.h @@ -3,8 +3,8 @@ * Copyright (C) 2023 ARM Ltd. */ =20 -#ifndef __ASM_RSI_SMC_H_ -#define __ASM_RSI_SMC_H_ +#ifndef __LINUX_ARM_SMCCC_RSI_H_ +#define __LINUX_ARM_SMCCC_RSI_H_ =20 #include =20 @@ -190,4 +190,4 @@ struct realm_config { */ #define SMC_RSI_HOST_CALL SMC_RSI_FID(0x199) =20 -#endif /* __ASM_RSI_SMC_H_ */ +#endif /* __LINUX_ARM_SMCCC_RSI_H_ */ diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 29c6100f0c50b..a707deba6ae70 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -43,7 +44,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index fbf215ecc7d06..2a8de20d2b447 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -34,6 +34,8 @@ #include #include #include +#include + =20 #include #include @@ -43,7 +45,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm64/kernel/rsi.c b/drivers/firmware/arm_rmm/rsi.c similarity index 99% rename from arch/arm64/kernel/rsi.c rename to drivers/firmware/arm_rmm/rsi.c index 25ca75ce1a4df..8e716f1c1e319 100644 --- a/arch/arm64/kernel/rsi.c +++ b/drivers/firmware/arm_rmm/rsi.c @@ -8,11 +8,11 @@ #include #include #include +#include =20 #include #include #include -#include =20 static struct realm_config config; =20 diff --git a/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c b/drivers/virt= /coco/arm-cca-guest/arm-cca-guest.c index 0eeddd1ff05b5..b741643d13647 100644 --- a/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c +++ b/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c @@ -3,7 +3,8 @@ * Copyright (C) 2023 ARM Ltd. */ =20 -#include +#include +#include #include #include #include @@ -12,8 +13,6 @@ #include #include =20 -#include - /** * struct arm_cca_token_info - a descriptor for the token buffer. * @granule: PA of the granule to which the token will be written --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010031.outbound.protection.outlook.com [52.101.85.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D129D39E178 for ; Thu, 10 Sep 2026 03:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.31 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011263; cv=fail; b=hcwnrw5TL8kx67rqAdQCyETP4OezPzHTh2xNFTqvVh2BH0rCCuMO2JC0o2wLUtrKUlEX95hj+iya/fb9WV/eJPpERXayZ4YlU6oX9LhkFH2rApwPy92XNjBhjfgwU0PA9Tz4tONLZcUHGuwn4fBp9U1loWaXa6vVWTV9vp0gEjo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011263; c=relaxed/simple; bh=Cbf0G2CKzPWjXKsyASrMZy+ImW79Fe+8bMQT2dGZDKE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tvqAuMuGhAwpWjXth7bZjEtHj9kZvF3Ui4BUl5rzkNdlknsmJ9hODNAgQKx5QCVddw20xALnKfbG6fuLa2ibSGqxLSflM7vUkOEdPHcV50T5X34XzXq0uPbnXSeqt/pA3WGvrhf+aaW1XBEULcFTv3KRm6gnhctoGqcGs0iC48A= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=W6S6ZZhv; arc=fail smtp.client-ip=52.101.85.31 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="W6S6ZZhv" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rdHiSE1S1NxhdV+NevHfrhYefOHHer1M09F4VJWhkgTPnyYlF+CGQlcpqFSUEY2s8USu6v2WjC/opZo7aZyMsuiRe6QC1V75t2Z11QvzIu17ZFBUEbi6mDO5PeSebH8Mv489eoEP1NRinkCTE7HzY6cHEai7n1sEtD/dCRfktaHVPv0oegot+Cov+vKIGsjP4V0KyYIFOx9C5kayMhMAwEh800u1z9615cZRbQ9H3csWaOQTF5jsTiUnThKU8hcHs8UfPcTbNjfvkrXC8ihfy+8pv4/Y0ARj54DyX2wuq4Dkcl37YLZ348nLnbZ60AQrp0adJ6dPXyEFqf9hoc/Yow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=t+SKy7WQuPqhO0auNrXCQs91OozJyuHZDXrsfTl0CPI=; b=Ytwn42lY8PpjyRuhimcRYyh94815eyQZ362GC03fceSriVTOWr7PLsnljrnl7SjlQH5SUkGBgaOjdjtlsWfdG5OHR9lE2y3aKQIA/vt67/ZZ+zYfqQnVSmGqmuRbJ16Tatg4mA2krfVykbde37opnDQ1mZ0AepadnV55CYqYL5QKj0dPOHyPNbifkXeyZb8depMKoiXg9+kRzU/DXINhfJme1sg5s44jFVyBdKjH6KJ7mCimRI+sFA3j3gCcfD0E8QmrN/gjpLUCYR/r23Sihx8RHLylonV4X4WStfVqZb8ht+HJeqZjZpG7jqlyG9ZiFzX3kpeflpodaaSHexJzLw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t+SKy7WQuPqhO0auNrXCQs91OozJyuHZDXrsfTl0CPI=; b=W6S6ZZhv1qaXAXOi5bq0MdJrV0WAT85BIU1SttmG1hd8memYyx31yiPmzZtz3FcTIA8O5gIFs8ePkO1xyBgn0L1D/0E7ETu71CcaCRjQ5yKV1Mw/KriTMAvrsjGBllhdCpCvQZz5lfHopr9LVAbpF34REDnqVE/y7mD2yqU7oD0O5mqwJ4D6nsGBRbfN8xQgbLok+6PUajHlOdPaZ+hSkGST0I57ufsIunYdM2WFwhMEAMpyUiRpThjDGxS8ML99hiAK84mJgvkLLDKklxbghP2CnrtVI/fh1WQVtAoCUuAp4rk2xy7jomjTDSHJVUp5Iw5QmI5Xqem5J2LxDeHsFQ== Received: from DS2PEPF00004567.namprd21.prod.outlook.com (2603:10b6:f:fc00::509) by BL1PR12MB5827.namprd12.prod.outlook.com (2603:10b6:208:396::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.9; Thu, 10 Sep 2026 03:34:11 +0000 Received: from CY4PEPF0000FCC5.namprd03.prod.outlook.com (2603:10b6:92f::1006:0:b) by DS2PEPF00004567.outlook.office365.com (2603:10b6:f:fc00::509) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.9 via Frontend Transport; Thu, 10 Sep 2026 03:34:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CY4PEPF0000FCC5.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:11 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:01 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:01 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:33:59 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 2/8] firmware: arm_rmm: Add VSMMU commands and fields Date: Wed, 9 Sep 2026 20:32:45 -0700 Message-ID: <0623345baaf550da1339e040b59f1fda902e3390.1789010941.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|BL1PR12MB5827:EE_ X-MS-Office365-Filtering-Correlation-Id: ea30de88-fdb2-4e17-b343-08df0eec612f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700016|82310400026|23010399003|6133799003|3023799007|10067099003|5023799004|11063799006|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 43iqHOiBy55PMinPvDiJxNMBZ/m+CyahmNtwsmJWCOow3MfzkdDVhioJq89/zgID47SWvJpe+n2+BDzm7PyWQphZZbSlhiRGRiw7dCNuwfX7fuBtw5sa70WhbALNhSglGXgJKCaAc/4IfhhPPWCFrByNMnIsBj5S0vz0WoEWoGY4PIRBCZbT8ZWpX3mtTMdMLQY20zdMKeaIwN+rAHV7Y1WF4tZaVg2hlx8sIhn6MQO4L1uRSmCry1AH91yxIl65PJlIuFtjCn3ABghJNq95HbFrK1ZzWKNKg7EwNs/uwGdtIY6s0uWI8i/fssetNNCXs43+8jFKZGU8VOQwLt99g3H336Zz/1cR2Y7XfQ5rMODp45cBXaN19riF24hCN1yswdPBrYLevSLmVdckczyh0c6CUPGSgn3xHoqtSholVrPWUq0S0ZIAYYAi+KGv4r23kOtUXgso6fW1zLgasOkj+VjweytUERS7/nqqy/pwmyNkkQCAKKSodGjxcZW1JT17Lm8YPYqg9RYPJWr8oUvbc71rgfrwwknRue+o/G9f1ezFN+Y2NC1x5BOc4DrDKW7F3Pinm8e6dpiIS1rBfVvZSZOOLCJhKZQSrAsvLpRcEs/ZA7iO3iwP92htNp1kjOsvybVuuXvvSShUT1WRnDUjNupK0sEXFq9D59Qfjll+V7uVX4b325Bpg1bU9ZVfmCPTQpW+Dar4KHRERcjERDKD+w== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700016)(82310400026)(23010399003)(6133799003)(3023799007)(10067099003)(5023799004)(11063799006)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MIsdXZm7Ath9JsQ+XO1SJdp4BdnLLda2AyXgD0tV+HFoAq73bLafIGFe3+K8FU4uR5Xl85OqNKNduPXfQkY0/wlPNUb3RwebbticTEHn4BCZhBD98O0n7BCbWamtRe/AeV9lobYbXgsyhahtJmZ9aeW0rUrpEdBlZiC34kalZaueXwV9fPS6pFfLCwcoKNXc4pGnRkguWYqgQWY3GiJJVFkoZ4D6CrpP7SG8rUluKltnSxd3HABObuEnAgjUGXMReHH+t2niT3RgLpHLoX7AWWGfym5+ukFg2zjJmnIksVTJgYaDL0mFYWQVU0lPEHU5G+2bPisat0eyyxuHhMheleb44/dXTR9hlDqZvvT/orn8S0hGgRdr5i+1ePoAVt4iPz13HsTkbODT+v1m5DGCjjMECx7wMMkAar8wqIXz+8pgxZGkglIV2ousrwwwO/qY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:11.4558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea30de88-fdb2-4e17-b343-08df0eec612f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5827 Content-Type: text/plain; charset="utf-8" DEN0137 2.0-bet3 adds the RSI_VSMMU_GET_INFO command and replaces the old RSI_VSMMU_ACTIVATE command with RSI_ARCH_DEV_ACTIVATE. Add the command IDs, return codes, SMMUv3 device type, and helpers for both commands. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Nicolin Chen --- include/linux/arm-rsi-cmds.h | 22 ++++++++++++++++++++++ include/linux/arm-smccc-rsi.h | 20 ++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/include/linux/arm-rsi-cmds.h b/include/linux/arm-rsi-cmds.h index 13478e14c4296..548ab0bcac722 100644 --- a/include/linux/arm-rsi-cmds.h +++ b/include/linux/arm-rsi-cmds.h @@ -237,4 +237,26 @@ static inline unsigned long rsi_attestation_token_cont= inue(phys_addr_t granule, return res.a0; } =20 +static inline unsigned long rsi_vsmmu_get_info(phys_addr_t addr, + phys_addr_t *top) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC_RSI_VSMMU_GET_INFO, addr, &res); + if (res.a0 =3D=3D RSI_SUCCESS && top) + *top =3D res.a1; + + return res.a0; +} + +static inline unsigned long rsi_arch_dev_activate(phys_addr_t base, + unsigned long dev_type) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC_RSI_ARCH_DEV_ACTIVATE, base, dev_type, &res); + + return res.a0; +} + #endif /* __LINUX_ARM_RSI_CMDS_H_ */ diff --git a/include/linux/arm-smccc-rsi.h b/include/linux/arm-smccc-rsi.h index fddb77986f706..2c16c23611891 100644 --- a/include/linux/arm-smccc-rsi.h +++ b/include/linux/arm-smccc-rsi.h @@ -37,6 +37,7 @@ #define RSI_ERROR_STATE UL(2) #define RSI_INCOMPLETE UL(3) #define RSI_ERROR_UNKNOWN UL(4) +#define RSI_ERROR_DEVICE UL(5) =20 #define SMC_RSI_FID(n) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ARM_SMCCC_SMC_64, \ @@ -190,4 +191,23 @@ struct realm_config { */ #define SMC_RSI_HOST_CALL SMC_RSI_FID(0x199) =20 +/* + * Get information about a VSMMU. + * + * arg1 =3D=3D Base IPA of the VSMMU + * ret0 =3D=3D Status / error + * ret1 =3D=3D Top IPA of the VSMMU + */ +#define SMC_RSI_VSMMU_GET_INFO SMC_RSI_FID(0x19A) + +#define RSI_ARCH_DEV_SMMUV3 UL(0) + +/* + * Activate an architectural device. + * + * arg1 =3D=3D Base IPA of the architectural device + * arg2 =3D=3D Architectural device type + * ret0 =3D=3D Status / error + */ +#define SMC_RSI_ARCH_DEV_ACTIVATE SMC_RSI_FID(0x19B) #endif /* __LINUX_ARM_SMCCC_RSI_H_ */ --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013037.outbound.protection.outlook.com [40.93.201.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D211D39FCC4 for ; Thu, 10 Sep 2026 03:34:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.37 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011270; cv=fail; b=iggzN/1GuJkDL7Un8yVTcCFeJAbmmpkqY0slyyzCKjczIYa6Ne8ZrqC55IQWXeZep20SHXoJa3BkfWvKgQ/ekrlCEquH00JY0TWr5r3+38FZ52SuSQXmXOOqJPFxJkVX8oU1gwwJxsfDH1o7j4ECrnN4DllboOrS0DwXizG/HrQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011270; c=relaxed/simple; bh=nmpPLepvqfyD3x/9yBa7S1QHwUb5IveWlo7/GVfuLuE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dNCaJSG03XvpXiDP4a1DpRcRL8grJYMdJ8y2ScNQzBsCeURUeMuy0Mpd2FXAeHycpncTSDsn9DoFb5hL12PrkYrD8DWsQi3D3vQ169x3Tlvc4Pax0Na5FE3hl6pf7fdR+jHlOtPyLL+td0oy8KmgIMbOc+qcNYBSQN6tMW0mzUo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Ids9shPa; arc=fail smtp.client-ip=40.93.201.37 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Ids9shPa" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=j1jR7LE0CTApO7N28tTpr7+3tr761XamVDgqHylmPo5qFDOxJBCxVPDgDXkiCZGufQhsPRgayUSCeky99addD8h1g0gQ2ZivCkL8EbSpB+7ykCTCkGVk4E71aaqEljNrG/2vUqzcTdggolVXloCesulaIq6t70AJZ0r2PrWeVh0ig3hmcnEjpG7bDqWkRukC/sqVW8+OHItyOL6/kMllOzravC0revcXU3CoWEcht0s+k1qBkl22PO1d0emoEbJ1CQjsBTuz8t57xT+G/CELVcDsv455PAXoJ4jROAurNh0W5IPW5BcWko3HMFczebJ6f2PAmYCBqWmkRV1YWc4PPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mP3wOfzqpEf8iRTqZ3mT+eF2s4gZ475jaPm0o9mXzg8=; b=thhh4WPk/whdebf3hCBuzunPJTWBBsIP3dnS47IpGxm7DFOV56rBnBDcU3cknFhyE5zSLuLDEHMEuV1P9LN45X1rxEk7gPoIWkV/eRRejKHvdGJ0USPFHDcADzUn5EbzdUnMRdGaKgt29YfCWEhPqCiPcRzOFY3DnUzdrV93W7P0vvOSnKBRFF+wYK92kiDp6fjZlDNulv5bKvC2A4b2qrN1UhCyr9YJfQ+ZYyyOJ4Acbw4rDQUTEI2m37C2u2XV2CJ8XuVDE6zqjsramFj0Dx5mqM3m1vEwNIdCdj1bQXKtnvH2dMdBtqhshSWsLv/tTLziq+liTOujZ5y50poEyw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mP3wOfzqpEf8iRTqZ3mT+eF2s4gZ475jaPm0o9mXzg8=; b=Ids9shPayTvg3qu/a5Mnh/YNnTjCenFqTe88/igLjS3eb09jAB7jz7gHZHYkn/BM1tBmzMsgSb663mcZoTR8XSn1AZVDVxckTJfxWI70FTciTTBAJiv9fpzxCYlgzsJCkcFcQq2qrO7CkzzMyPYk9WR6NuW9F15FBG3K/IiCisTvdvxcx+pfDryXFDxLNNgciYKfIfZLuyc/squbiqRGCr5h01Gw7Yq8oj3oxSB0lXsjC6oJy9AfEZUpfr7griy852qJ7ZifdH2G3nt6xDw+VUYubkn+eY/zPKPZ+J22yXPB70BcxDX6sD0/F+kzAUmPvh2/5Ayzw3v8wkdpWhUQ/Q== Received: from DS2PEPF0000455D.namprd21.prod.outlook.com (2603:10b6:f:fc00::515) by CH3PR12MB9194.namprd12.prod.outlook.com (2603:10b6:610:19f::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.8; Thu, 10 Sep 2026 03:34:15 +0000 Received: from CY4PEPF0000FCC5.namprd03.prod.outlook.com (2603:10b6:92f::1006:0:b) by DS2PEPF0000455D.outlook.office365.com (2603:10b6:f:fc00::515) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.10 via Frontend Transport; Thu, 10 Sep 2026 03:34:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CY4PEPF0000FCC5.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:15 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:04 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:03 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:34:01 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 3/8] dma-mapping: Let a device declare that it reaches private memory Date: Wed, 9 Sep 2026 20:32:46 -0700 Message-ID: <2190d81f2451668fa09d5f83e43e25540907daf1.1789010941.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|CH3PR12MB9194:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d2511aa-7a82-425b-703f-08df0eec6385 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|23010399003|36860700016|376014|7416014|10067099003|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: A191XTttZT1/w9yKIV6bkxBpFr98Z2fyfcd/gsU1RcU8a3nF7Dv6sH0EF7QASFhW1hSRf1vY/3RuX1FmUeH1bRuKaL+7UZV3Jpc9zCBZAPvtkzsXoagCOAu5JGzhg2xst+N3idiZ1jtxvBqQjtjLQ209M4Jm0tpTHJKWCXtImzVZbHMDObKcTsbCKLL5vpl+K9eEWXwCMuKSZojR4vyIz3yUmysRETR8snP6r5BKV1afQQhk4La9n3j62AMG7B4xnsr32RQPUdMWjTenWDvIL//YgV+jKqlRzFiocPVkPeq6nU2xXnp4A3vON1N5rRdZFeqzLj1SXSEQ+UBWzfINQplpQCbGapTW6eDtsoVKuFZS3eAOiiJbB2k7bxoBoemSFK3shrsNExgNmYYELCNXqR4kZhHKt++L3SpBf7RE7kc7UnT+pV/4itDg7vqborj/pgkjmbzzGYVuXLc/zWnB3Cvl7WggXcERoqRMpsPoI8LSPE0UcAa/R+jhg0SFDfaa2xk0W6kaGr2pW8OvL5xastE0bNx11/YS+TmB3drAoT3j/dIaRcKz0fy27i2lB4RCNuSTgsURFJ9iDwrks+0pNXa3K2pOWWl0WhZru1DgRjzpxhdCI8lHTAIkK4s4VHKYGFRdK+TB7EgMXNBugocZuMGsaIRULsE9sczyDR6yLHNyyKK+1mJe84Vkr3eOamwhayDt/yY6a09mNVHtrpxgYw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(23010399003)(36860700016)(376014)(7416014)(10067099003)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LPqY1Lp9f1TZ2DSveYPEV2mWGaxY0aI++Pr0TpMVq0vfRIrfJxWREcnjm8QutmXgi5pgyWxBxl7+Nr6xp62EJo6iCTI78lavUZltRKoAT3TwYw7ONav1OInPUSeazunh/yTpV7cXT1i3zlV8JnnfKHZK7YnkTXI+rTwpmLQF05eBlxqNfdkB91mGpUVSukpHpQxkvMv2PxCIdoxqpPz/bM+n7yrLbba6vNoQSOUgwBkXpGh71kZfO/OSq/VQVJW9ag+Aqyaf0ww1VnL5NDqjAkfd+j/HZSwfFaEm8ADHRCtb1v777yQCJrLjke+02vwClcunphm5MfK+8k3makKhwaYphzRqC7ypcpVSZmy3E8u17NSlTBbJ+nSF/KDbyd9Swjrsr0IBsa6FsVNJWcFuYUuLsZ4vj9+RiNz2SUnprLXWVFafSdVUk4PRJl4a9aMN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:15.3802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d2511aa-7a82-425b-703f-08df0eec6385 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9194 Content-Type: text/plain; charset="utf-8" DMA devices in a confidential guest can access only shared memory, or both private and shared memory. Some method outside the DMA API will confirm the device is able to access private memory through DMA. Add DEV_FLAG_DMA_CC_PRIVATE and dma_set_cc_private(dev, bool). The flag must be stable while any DMA mapping exists. Suggested-by: Jason Gunthorpe Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen --- include/linux/device.h | 4 ++++ include/linux/dma-mapping.h | 4 ++++ kernel/dma/mapping.c | 21 +++++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/include/linux/device.h b/include/linux/device.h index aee79fd6b32b4..54ac6cb7f3762 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -599,6 +599,8 @@ struct device_physical_location { * ancestor device. * @DEV_FLAG_OFFLINE_DISABLED: If set, the device is permanently online. * @DEV_FLAG_OFFLINE: Set after successful invocation of bus type's .offli= ne(). + * @DEV_FLAG_DMA_CC_PRIVATE: The device is able to access private (encrypt= ed) + * memory, no shared memory bouncing is required from the DMA API. * @DEV_FLAG_COUNT: Number of defined struct_device_flags. */ enum struct_device_flags { @@ -612,6 +614,7 @@ enum struct_device_flags { DEV_FLAG_OF_NODE_REUSED =3D 7, DEV_FLAG_OFFLINE_DISABLED =3D 8, DEV_FLAG_OFFLINE =3D 9, + DEV_FLAG_DMA_CC_PRIVATE =3D 10, =20 DEV_FLAG_COUNT }; @@ -829,6 +832,7 @@ __create_dev_flag_accessors(dma_coherent, DEV_FLAG_DMA_= COHERENT); __create_dev_flag_accessors(of_node_reused, DEV_FLAG_OF_NODE_REUSED); __create_dev_flag_accessors(offline_disabled, DEV_FLAG_OFFLINE_DISABLED); __create_dev_flag_accessors(offline, DEV_FLAG_OFFLINE); +__create_dev_flag_accessors(dma_cc_private, DEV_FLAG_DMA_CC_PRIVATE); =20 #undef __create_dev_flag_accessors =20 diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index a3e880649fa41..8d23b983092e8 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -218,6 +218,7 @@ void *dma_vmap_noncontiguous(struct device *dev, size_t= size, void dma_vunmap_noncontiguous(struct device *dev, void *vaddr); int dma_mmap_noncontiguous(struct device *dev, struct vm_area_struct *vma, size_t size, struct sg_table *sgt); +void dma_set_cc_private(struct device *dev, bool private); #else /* CONFIG_HAS_DMA */ static inline dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, size_t offset, size_t size, @@ -357,6 +358,9 @@ static inline int dma_mmap_noncontiguous(struct device = *dev, { return -EINVAL; } +static inline void dma_set_cc_private(struct device *dev, bool private) +{ +} #endif /* CONFIG_HAS_DMA */ =20 #ifdef CONFIG_IOMMU_DMA diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index bf2651a70b7c2..11c127ad45370 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -501,6 +501,27 @@ static void dma_setup_need_sync(struct device *dev) static inline void dma_setup_need_sync(struct device *dev) { } #endif /* !CONFIG_DMA_NEED_SYNC */ =20 +/** + * dma_set_cc_private - Set whether @dev can DMA to private memory + * @dev: device whose confidential-computing DMA access is being updated + * @private: whether the device can DMA to private memory + * + * Called when a device is known to be able to DMA to private memory. + * For architected CPU integrated devices their kernel drivers will + * self-accept using a driver specific validation. Other devices will + * have a userspace managed process. + * + * DMA mapping must not be active when this flag is changed. For CPU + * integrated devices the driver should self accept early during probe + * after validation. Other devices have this flag set automatically + * before probing. + */ +void dma_set_cc_private(struct device *dev, bool private) +{ + dev_assign_dma_cc_private(dev, private); +} +EXPORT_SYMBOL_GPL(dma_set_cc_private); + /* * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems * that the intention is to allow exporting memory allocated via the --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010057.outbound.protection.outlook.com [52.101.61.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2227139DBE5 for ; Thu, 10 Sep 2026 03:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011278; cv=fail; b=rgu4jINAoyvR/x3AX9LhKH2OdgymyTnKL0BTJ3auivxWFJ8Lmoh1b31A+/mA7IkY7HajfkSMxIGomhT7nRgXb40dVs5dXpmjT18QpHFmY7m2+pJJLdt5b7p2vYUQFTw3yQywKXUf0/8Ru25P6aIJtuChOYb3m/z811UfWqeyKsE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011278; c=relaxed/simple; bh=rzbitRnpJAFSTXusz+GATdcHEZwdYGgyF+iJjOY6Gi4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lU97gQcTypCosMjaDVh/ji7qrfbM9pKEg4ag4jkbSZBTLyjmN3VHGYpJavQ+N4oLGMNUSZiEEqeSkSiODUFMRZJ+wNmO0TxP5wi6/t7xF4tmqCdKBRbEpcGphGByCxtMe3vimTYw2MwO+F/og19LLJRLngw9H1PTaFcP/jcmQbE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=TVhVpuwp; arc=fail smtp.client-ip=52.101.61.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="TVhVpuwp" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dlSMxEE583HmzEa5kcsLxShoWxTTNXy0aG59Buat4DJbOEqK9MwFzRM0vA0PzkpKTB9Zhs33wbq87HLL4hJWToAjUIUO/a68HFmqEPQ6k3proVGYi1lJ5Q0LgsnQUTnGKp4oZqy3OAZsDWV04/K4LTHDmkZBjq0y2b3GkLt2FDBOFXDxEfj19wmbRlh6xS0SYfftuEAOU78qdpI2HWwdGLQKZgYbO3slN3ceV/90fNLB9VLnpEKwypGavtgNeJ1NRHclZ9EFPeEiBhGR8/P/ga7Ay5IdxzvblDaRVCdLVrNV8MXq+AOcesNqil/M52m34aPpZr+SWMbcWiQkIfYCTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZPsnVwapVkwHCRbG/3G5otIOKnbDmZl98XDmt9LMWU4=; b=OcqhquJbQGMGUl2ViKSuIgIeg5ALFkdZJBMX0PFvk1zodBcSv75EsveJPXzQioi6UIhEMdFVIIUEQ6blDk41wcEK8M/8ECQTxVxx5z2Gfe+lYyQ+YLuxULsOmCiVsC8iyukf5a25UGAtk1imIj2Jwn+siUFzCNF3ZU2aC2CikxHKZ5KlOLqnC8j9ZWK7A3S8TAUWjLp5jctGJ4VTFEz3IC/ZHY7b9oTSmNjvnknG4V0lrUyS6xbMbM7yWG9HcJYzoGUSHpn0+TByS95gmIn9wZZh2pRl977fJ/Zk/cTRU/fJUUcMvk0sjKsNT6Hx+280lcUkRefnJnZBJdUJmdvxgw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZPsnVwapVkwHCRbG/3G5otIOKnbDmZl98XDmt9LMWU4=; b=TVhVpuwpB8C7ycmi330+M57T5uZjP35nvp6ca/a/5ukKXdT9SYNRZTtjQtBWyhIgQCI1jXUvX4KHs6gDCm14vTHeAkkUwfMeciTBRE1xb5sV2P7jkngg9EWaF3G7WCHP1UMwe+NX3G+5bIhxCOsmWfa1GzAUYxzp6ot0MRB2nMISCuhpnzEjYVejHfafcEWtk6abkYQGwkzosiAs+f9gznh2ag45MjTplnD92Jv/GeOSEv9GZNjg4V3Y4Mq3X7oNjaxrjtHGvV9lQGIxTPcVZYzzCNtWUV/1eGRvZfJQgtHZtHo3JdkJzVuAFS5DYTD7VuZUlRTveXlTo27a1e0vjA== Received: from SJ0PR05CA0202.namprd05.prod.outlook.com (2603:10b6:a03:330::27) by CH0PR12MB8487.namprd12.prod.outlook.com (2603:10b6:610:18c::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.8; Thu, 10 Sep 2026 03:34:17 +0000 Received: from SJ1PEPF00002315.namprd03.prod.outlook.com (2603:10b6:a03:330:cafe::7) by SJ0PR05CA0202.outlook.office365.com (2603:10b6:a03:330::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.406.7 via Frontend Transport; Thu, 10 Sep 2026 03:34:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00002315.mail.protection.outlook.com (10.167.242.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:16 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:06 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:05 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:34:03 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 4/8] dma-mapping: Keep DMA memory private for capable devices Date: Wed, 9 Sep 2026 20:32:47 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002315:EE_|CH0PR12MB8487:EE_ X-MS-Office365-Filtering-Correlation-Id: 022bb3dc-e09c-4dcc-5a39-08df0eec643b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700016|23010399003|82310400026|10067099003|11063799006|5023799004|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: ei9nHSUwrZ7wotiRfXlSGwXlAOrFjQ7V1Dc4nnJ5LeNLOZvixqlKzsRqVAn5LgC9bdwKG/hteuuhdW/Bbx3pOLXMt57wrs73MkDJVIeYua+npM0fuWoJqiqmLwy8mYynTg+q5WoX4hJ84mY0EGfQkp71ZOs6I/P/kpoWj8rvp6SWa1fqlzNiaMmsSKIob4RC5RFt7AhF7QoqYuqrcoxcaJfjgZryYvhhap+1hFfI3KoS7gNpih5nkDcuKQrRw24BxgqESOUbb9+WUIJZtZ//BH61BggcKhxEYux0yTz30uutt6who3J6Jp13jDS/u/I9yzJ18YohPp+l8HJ1sh2IifwQxXSvHfmKltZWLCdZFRLopNMctKgmAksavVy99j0KUPmCGEschdwVTJgzN2gFXiRWaInMFBME8H8FXmqJTWQeRZ4/87KNR3oN4Ya0Wnn/fE/x5rDPQqIJTHl9IpLpXYENUqP3nrl0jQh4uUSM4j7Qr5kxrdg5NSkeImP8IhUxMhhChPAW/gHIgsieN3aiE9/YCprNng+QeqJUSpr8C8LHkim6zmQ+rJrDP0rotIinJ3lE5vUYLIHQFzTNeJc0O2tBFg+3I0T0KcyplT+ogptGT6DzpQaVuKhSUI0IzAQy2SlJZ0l4AdzAGaSN4+JrBFrEfWy3caFEJhJUbDF8+PpF+ZbEjTD+pj5BiI7nVhyc0t90zeIQ+nAvLrArx4sjEA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700016)(23010399003)(82310400026)(10067099003)(11063799006)(5023799004)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kEdK22RZERh211hZ3xj6GMS3vM0XQz6gSWzST4irWBXaHUC5oqLYR7NyrZYSd8rFizig1k81NHhDrjp6x16VwBtmS6vZy6WxGifkb9U5t4NR6yl/k0+CHFi+DD87+EOwWLGP4KFQU9gXOLxnfTj1YjcYvt5t3sKsjwr+jZzutvg0Hgvk05bzhCTr8rYzohyuDzr0TKJuHWkbbpiomu+12EeXSwAml2dVpz6f5ob4CsIQEudmkvPIxqNSV0iJNengrHwKNvTQfVNTekyt8o4ea2b5Dgml/AGENcWxmIYyWcpEgSATNeeDiNKFdqfOiqsFfx+Hd9JNgpfDYX9veaDtufyYYHasMXp1aq0k8arnvnxW7Q7Tmo524gUYANHnjGS1tI96+9AFGm3VsH7bmUrQKA3HZ5VLY95o0qn4Fw/Hr+IAQmDodMtTfa3gqM8cwhI/ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:16.6401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 022bb3dc-e09c-4dcc-5a39-08df0eec643b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002315.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8487 Content-Type: text/plain; charset="utf-8" Architecture code can require devices to use unencrypted memory. This makes the DMA API use shared memory for coherent allocations and bounce streaming mappings through SWIOTLB. A device marked with DEV_FLAG_DMA_CC_PRIVATE can reach private memory directly. Add dma_require_decrypted() to combine force_dma_unencrypted() with the new device flag, and use it throughout the generic DMA code. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Nicolin Chen --- include/linux/dma-direct.h | 7 ++++++- kernel/dma/direct.c | 16 ++++++++-------- kernel/dma/mapping.c | 2 +- kernel/dma/swiotlb.c | 2 +- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h index daa31a1adf7b0..fb35ca27941cc 100644 --- a/include/linux/dma-direct.h +++ b/include/linux/dma-direct.h @@ -134,6 +134,11 @@ static inline bool force_dma_unencrypted(struct device= *dev) } #endif /* CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED */ =20 +static inline bool dma_require_decrypted(struct device *dev) +{ + return !dev_dma_cc_private(dev) && force_dma_unencrypted(dev); +} + static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t= size, bool is_ram, unsigned long attrs) { @@ -146,7 +151,7 @@ static inline bool dma_capable(struct device *dev, dma_= addr_t addr, size_t size, * requires unencrypted DMA addresses. Treat it as not DMA-capable * so the caller can fall back to a suitable SWIOTLB pool. */ - if (!(attrs & DMA_ATTR_CC_SHARED) && force_dma_unencrypted(dev)) + if (!(attrs & DMA_ATTR_CC_SHARED) && dma_require_decrypted(dev)) return false; =20 if (is_ram && !IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index da665ca22d5c0..fbddab9740162 100644 --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -41,7 +41,7 @@ static inline struct page *dma_direct_to_page(struct devi= ce *dev, =20 u64 dma_direct_get_required_mask(struct device *dev) { - bool require_decrypted =3D force_dma_unencrypted(dev); + bool require_decrypted =3D dma_require_decrypted(dev); phys_addr_t phys =3D ((phys_addr_t)max_pfn << PAGE_SHIFT) - 1; u64 max_dma =3D phys_to_dma_direct(dev, phys, require_decrypted); =20 @@ -72,7 +72,7 @@ static gfp_t dma_direct_optimal_gfp_mask(struct device *d= ev, u64 *phys_limit) =20 bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size) { - bool require_decrypted =3D force_dma_unencrypted(dev); + bool require_decrypted =3D dma_require_decrypted(dev); dma_addr_t dma_addr =3D phys_to_dma_direct(dev, phys, require_decrypted); =20 if (dma_addr =3D=3D DMA_MAPPING_ERROR) @@ -208,7 +208,7 @@ void *dma_direct_alloc(struct device *dev, size_t size, struct page *page; void *cpu_addr; =20 - if (force_dma_unencrypted(dev)) + if (dma_require_decrypted(dev)) attrs |=3D __DMA_ATTR_ALLOC_CC_SHARED; =20 if (attrs & __DMA_ATTR_ALLOC_CC_SHARED) { @@ -368,7 +368,7 @@ void dma_direct_free(struct device *dev, size_t size, * If the allocation used decrypted/shared backing pages, restore * the encryption state on free. */ - if (force_dma_unencrypted(dev)) + if (dma_require_decrypted(dev)) attrs |=3D __DMA_ATTR_ALLOC_CC_SHARED; =20 if (attrs & __DMA_ATTR_ALLOC_CC_SHARED) @@ -436,7 +436,7 @@ struct page *dma_direct_alloc_pages(struct device *dev,= size_t size, struct page *page; void *cpu_addr; =20 - if (force_dma_unencrypted(dev)) + if (dma_require_decrypted(dev)) attrs |=3D __DMA_ATTR_ALLOC_CC_SHARED; =20 if ((attrs & __DMA_ATTR_ALLOC_CC_SHARED) && dma_direct_use_pool(dev, gfp)) @@ -480,7 +480,7 @@ void dma_direct_free_pages(struct device *dev, size_t s= ize, * if the device had requested for an unencrypted buffer, * convert it to encrypted on free */ - bool mark_mem_encrypted =3D force_dma_unencrypted(dev); + bool mark_mem_encrypted =3D dma_require_decrypted(dev); =20 /* If page is not from an atomic pool, dma_free_from_pool_page() fails */ if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) && @@ -649,7 +649,7 @@ int dma_direct_mmap(struct device *dev, struct vm_area_= struct *vma, const pgoff_t pgoff_end =3D vma_end_pgoff(vma); int ret =3D -ENXIO; =20 - if (force_dma_unencrypted(dev)) + if (dma_require_decrypted(dev)) attrs |=3D DMA_ATTR_CC_SHARED; =20 vma->vm_page_prot =3D dma_pgprot(dev, vma->vm_page_prot, attrs); @@ -798,7 +798,7 @@ size_t dma_direct_max_mapping_size(struct device *dev) /* If SWIOTLB is active, use its maximum mapping size */ if (is_swiotlb_active(dev) && (dma_addressing_limited(dev) || is_swiotlb_force_bounce(dev) || - force_dma_unencrypted(dev))) + dma_require_decrypted(dev))) return swiotlb_max_mapping_size(dev); =20 return SIZE_MAX; diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 11c127ad45370..e7c48a925b7ac 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -673,7 +673,7 @@ void *dma_alloc_attrs(struct device *dev, size_t size, = dma_addr_t *dma_handle, return NULL; } =20 - if (force_dma_unencrypted(dev)) + if (dma_require_decrypted(dev)) attrs |=3D __DMA_ATTR_ALLOC_CC_SHARED; =20 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) { diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c index ded7016a46a71..d08a3643ded14 100644 --- a/kernel/dma/swiotlb.c +++ b/kernel/dma/swiotlb.c @@ -1552,7 +1552,7 @@ phys_addr_t swiotlb_tbl_map_single(struct device *dev= , phys_addr_t orig_addr, if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) { =20 /* swiotlb pool is incorrect for this device */ - if (unlikely(mem->cc_shared !=3D force_dma_unencrypted(dev))) + if (unlikely(mem->cc_shared !=3D dma_require_decrypted(dev))) return (phys_addr_t)DMA_MAPPING_ERROR; =20 } else if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011058.outbound.protection.outlook.com [40.93.194.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E3E3379ED4 for ; Thu, 10 Sep 2026 03:34:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011271; cv=fail; b=O0SW3Jq7CFDqFk6pN+JE+VrPGcy2qMsE2H6WZQKZCKW3/+5VeiU3mVJthQEzOBxo/AoYjcJvWaVJTvEVZZbMNtqPin+42ishP7GOg1E73eOl98aJM2vFDLCyIiWoWgTI6oSF8S8jM//aj+G8lGAVE3T4NzoY4slAi2ZfpT01MrI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011271; c=relaxed/simple; bh=4736cWY4vqqohisgRKlLBlR3jvOBw3lhn1McAZHG8XQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VHOAcRsIALdJzoNJ9Q2rFuVwbrvAdvS3WzbxC/+nsTBGvmIJ+MslKTjtlDjDQswi2Yo5anh5QVkxsuUjncV2AvqtjdqrWHfui8s7F+BZt8dV2UONYpJgO3JYptRQ4aRNrnKR0hMeaWzrBYPbVePgtkcM2Xpwu/cRviqn2SJLrnA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=H+yiEFcj; arc=fail smtp.client-ip=40.93.194.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="H+yiEFcj" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jTVzQrX6MymaMqxQLLWSLwRVdtjByhCaAVUjuGrinRb1+cSxzj/0F94KCMM5myeV8m0CiDwChuexYijz2YIWKiQRlMticL5aJNRkiEHX773F+3RxH78yanzjQdL5Q5dsN3PxAnBOnaJoInb6iktXJh7+W0do6b/ZFZwAxSdVox4rYpdBNF/7+CLR8Azqncra80Px3ji0Z0l6i8UdnqrZZhtRMWqMs6afgqX+A7Wvf1/xzYIOsRv7tQb1YQxj3e9524+Njvsl2mwf34GLzrMxnI51/3guxDu7zsZszmCiNlwg1dZVUFVyHczQtqHB7eC5bAq3hN7WbgZb1Uj+JSp32w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1aSvNQ5GYhLgwH3JSuWxrnC/T0tSa6usxfg4eftxz2k=; b=gvurqFKmEcpSst9VWUf35ibCwQlfiwoyHaS2sofTu+T+O960Cxvo7anZxJyJ7LPoZSMcvJIAoNQvQGpNJX9CcLn2a+Hi0exABujbiu1YlMVZCsLvfHXUk6SPqEN4itQdnpBKYc3EWdmgjyfAqLrYnWecQjaRCCdxotJXB5fFDHEsMyx1vX9L374WyJxANmRLGdoBwHrij+exiQmWDa2p68P0LppslLnPu9twRc+G6YNAqiU0vWeqoiF5rkBXNg8d90yGRA67r5gekrzejVR14mkh2kXOGF3WVIZJzQX1gnSJCuLj3RL+4fT6I8QBI7VwVJ0Xf6cuvQ3ExBeIcWtGDQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1aSvNQ5GYhLgwH3JSuWxrnC/T0tSa6usxfg4eftxz2k=; b=H+yiEFcj9G5g5Nk4qH5D64Wdfxo2SrgqjKpacx9Oq6gbeg6rDZSBzFC6z7VvdBT8dsZqON5aXx3lCoqN2K3hjSD3ALP6CSPtrlFNxR6A8tME9nrcs7rDlmNgwMp8Aerj7UMAdwB23OYhtJHH9Y7ZTbNioVYyjwL4clU9KeFCMIDa//0p0rx5fVsg1wfvheCzxUKOsF3MJGiiYrk4w0iDB5F3coTVm7CSHVgEANcnGBeoE7fosYomurwjRiaQYsfYtG9qHT3Glw19VxOMUtT+zndbvO8GYvvOLCW+Fr0ITMIxgBtP3TWdY10otLd+jIblb8mxkpqzDpceihkXghLcBw== Received: from DS2PEPF0000455D.namprd21.prod.outlook.com (2603:10b6:f:fc00::515) by SJ2PR12MB9190.namprd12.prod.outlook.com (2603:10b6:a03:554::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.7; Thu, 10 Sep 2026 03:34:19 +0000 Received: from CY4PEPF0000FCC5.namprd03.prod.outlook.com (2603:10b6:92f::1006:0:b) by DS2PEPF0000455D.outlook.office365.com (2603:10b6:f:fc00::515) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.10 via Frontend Transport; Thu, 10 Sep 2026 03:34:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CY4PEPF0000FCC5.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:18 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:08 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:07 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:34:06 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 5/8] iommu: Let a driver mark an IOMMU as confidential Date: Wed, 9 Sep 2026 20:32:48 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|SJ2PR12MB9190:EE_ X-MS-Office365-Filtering-Correlation-Id: 79587abc-5fd4-4e0e-e481-08df0eec658a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|23010399003|1800799024|36860700016|10067099003|11063799006|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 3jnSfWtOigBAFoxa59d2zTTmt4kb190qjD9z57wiUWLpK+B8vNrd6ylArLGp/E4L8VWEUCXTqcQ8MOqFrQQC1qyF+p6F772X553tCx4Ovt16jlXmfY/OsuFIzNhqU+aftQ7I1pxCK5jhZ85lyS0V+SjyP8QGAR0h9gQYZqIswfgexHe6+eFZH9gDedsXGNVrC0XWiaSZ/luh4LM1mc1+brioL22mVgK98kQQF8Gc/TTjKSzsCMq+NZ/n6Yq/3Yy87Ynz5E/Ztl+cmtAFVs7yF7r1EEMA2FzCRETr7nj1ngPfpmesoU8QqobpDRfAp22ItZwnkD26URRHXF2ZjFaX8rkM3k/LFjWM6fYNpIT/5XGtQZsSG6nMIxYBieriO2g/UMW5ChHmxOI4WTPPxFbsCXZcgkideab/Jr3yWUux5WfTSATaoLtLXFlGasM9kSV4BauRPwYWifnDWEgWyynUaoLU65/udVe/Dkre0bdSjXivREG4ZfDdKUI811yPTHi3gTJi6Kj1OnPU8C9HTkOXQC0G+8DYqFQCTTDQVKdIjR4HdO/G81KU1Xmdk4e/cHLu4cCzMJIHHNlXcE27JlnxnO9SctIxvbnoZFEgJBOLhbC/md8ZsrfHOODXNTPzgHO11Yqe6etrf4fKXO41C477f26x/R8MIcEVs06Hlra07qqxX0EPHv0eApH2PwosZPEj5fd8+APcJACp7HYHJsVdMQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(23010399003)(1800799024)(36860700016)(10067099003)(11063799006)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4orO/DBsS/BPMD8m1hewdDL7zmGdWGsucMdkl3DtTSnc8q5dB7VVPQQO3UN2QOa3KxUWybl4jP0ZtA9arDXAaU0a76GnPZuZCGRWhap5tgfb2jDVmjYyPFvpOOMj/a/q3S7txaknol9u2mlbSzPoBGVTTor8CV+crhpOgwdaFzfGWuF1LzK5MqYuP+8ePj21FxJdVjQ53YzOJQOO4/F2LcaZqqen/bTmf/JMxuQ7EG9nNsfZe6kezA0zfnA84g2k/RfiT1AQatxRoyGARqqp52z9rlMY0qG0joDOexK0jr7Ba0tiJLO49zjOQJhw2lqk3fwmql28fDAcBPEutMxMKS9qTgMMg7mvBAlWfZLGnrdBhyx3f/iFoxPMKfug234E7IUYKfo+dePp9u81eEfnqBH5wm6/pjU886a50FKniTHi7HAhIEJLGeUYHOlljMvu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:18.7644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79587abc-5fd4-4e0e-e481-08df0eec658a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9190 Content-Type: text/plain; charset="utf-8" An IOMMU inside a confidential VM needs private memory for its queues and tables. Later changes also need to identify it when handling TDISP devices. Add a confidential marker and a helper for IOMMU drivers. The helper also marks the IOMMU device as able to access private memory. Drivers must call it before iommu_device_register(). Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 10 ++++++++++ drivers/iommu/iommu.c | 20 ++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ac43b8b93f14a..bd68532e7f3be 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -822,6 +822,8 @@ struct iommu_domain_ops { * @singleton_group: Used internally for drivers that have only one group * @max_pasids: number of supported PASIDs * @ready: set once iommu_device_register() has completed successfully + * @confidential: this instance runs inside a confidential VM. Set by the = driver + * before any dma allocation. */ struct iommu_device { struct list_head list; @@ -831,6 +833,7 @@ struct iommu_device { struct iommu_group *singleton_group; u32 max_pasids; bool ready; + bool confidential; }; =20 /** @@ -890,6 +893,8 @@ struct dev_iommu { int iommu_device_register(struct iommu_device *iommu, const struct iommu_ops *ops, struct device *hwdev); +void iommu_device_set_confidential(struct iommu_device *iommu, + struct device *hwdev); void iommu_device_unregister(struct iommu_device *iommu); int iommu_device_sysfs_add(struct iommu_device *iommu, struct device *parent, @@ -1423,6 +1428,11 @@ static inline int iommu_device_register(struct iommu= _device *iommu, return -ENODEV; } =20 +static inline void iommu_device_set_confidential(struct iommu_device *iomm= u, + struct device *hwdev) +{ +} + static inline struct iommu_device *dev_to_iommu_device(struct device *dev) { return NULL; diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index cd1bca7ede9af..feff390727d13 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -313,6 +314,25 @@ int iommu_device_register(struct iommu_device *iommu, } EXPORT_SYMBOL_GPL(iommu_device_register); =20 +/** + * iommu_device_set_confidential - Mark an IOMMU instance as confidential + * @iommu: the IOMMU instance + * @hwdev: the struct device of @iommu, whose own DMA reaches private memo= ry + * + * Declare that @iommu runs inside a confidential VM + * + * Call this before @iommu makes any DMA allocation of its own, and not me= rely + * before iommu_device_register(). Queues and tables allocated any earlier= land + * in shared memory that the hypervisor can read. + */ +void iommu_device_set_confidential(struct iommu_device *iommu, + struct device *hwdev) +{ + iommu->confidential =3D true; + dma_set_cc_private(hwdev, true); +} +EXPORT_SYMBOL_GPL(iommu_device_set_confidential); + void iommu_device_unregister(struct iommu_device *iommu) { for (int i =3D 0; i < ARRAY_SIZE(iommu_buses); i++) --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012066.outbound.protection.outlook.com [40.107.200.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 060013A4F23 for ; Thu, 10 Sep 2026 03:34:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011283; cv=fail; b=uRUzRF9uenf+Yo2ie8KAYB5B6M8+0GJXs2YzPYMcX4v5c5pWuZ/9k6VFfe6jpL7+TC+vNHVYxVYyGOxTHNFjgkZAEqtwDz5D13m4ShmSZE5u4+cvm8cauhdIQCID2whdIxPSj05QFJ8VX3XbZvX/ittPBpEngig/qoNOpPn6vOY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011283; c=relaxed/simple; bh=KHDVozucmfDd3Sh/0+v2fj6tdwSkpE5oK+qTr/12QIU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rAW+iMbXwPbAO4E/lIZjY0HW1TTsqqPY5TUAn14QdjKFZvopRfQlAZVWPv4m97o1mHjs4kNBRB2pCaw9Z/f5xCCpe8xTs7Q+h7Wq2vgQtdL6m74e4GmCNCjXAbB3m2wUcVMq4VGevwnilXtXOA/7dcpCFoXSSafpQ08sAyrLKLc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=E4urgNsm; arc=fail smtp.client-ip=40.107.200.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="E4urgNsm" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WqX6OsSzzfVpCsRQ5zXpKUd0YvFU2HjyFdgugNtgTGSgsI290407z/NAsMhD6a+6NrmreJ3pHyVpjTbYNu8i4KFmeedOXMemUmOKHoMmbmyrdr9RydGhObiBjPGAfGmbdKEI0NS6XY7XZ5iicOi9B5BwIjqqSZHiC6oPMNvOBFBrK++sT9DUsf4QipJtjb9AsYceRBLNZD5WUXyMhJo8P4C+ln9btEUHFt5saQd32ptSFmpdWClLl+EIsQOd0E3ayoGL3BziHznK1IMAPnN8j2kQqU16+G1Bm14zsI3Pr3WVW58U8gNmzhwxnJT8ySJrf8aEqJZojOBWRnKoO33YRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8DyR2tD/EpvmkH5l4JyfBoAKAadlLV7F1+oGCIOV//Y=; b=s2Sc6143GJZsbGQZrSsWHs2VEfYqt2t0zu2HHGPo/dKxqhi7PE0pGyiFJcH42LqHd50+D1wUkxVV05hKEn3zlnOLHzeKxkU+mnOh+WvF2fpovEg+PbAzG1M98tWslTg9Ee1SUXa074vrTPlgkV1XHCuJEE8MIIov2uQUdxT1dBq+1yhHJfn7T76JAzXi26EhEiup07olJK5SMDgYlSrRNjD4TOxMk9nwS3hQ/2It6vLobBEvOU2bzhA2VaGzjX0C3g3Lld8BKr4YxhTjMFtHeruzjTpAVM4mbOWd/Ywu7zHGStYq+koFmelr+OPxWAsfIPodO0cxhLEeIqCUjsRXQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8DyR2tD/EpvmkH5l4JyfBoAKAadlLV7F1+oGCIOV//Y=; b=E4urgNsms4xXxg5PQ6eG9tCdFKgBFa0QgI1DIuvQ+g1C7iSJTJEqT/mconbYajo1EmMS8+6f8HmOh2OZRMISo12FQdBJneboyqPpRn8bko52J+rvWmDIgg1KRa2aP+zLf+shOmheGAJ8MXi0onYdPfgCGFqOh2Vhes81ZoRzosJVWb9lhpRabeWzWHTqr2FeCgJz7xNO3819urJH7PS3obh4VjHR0zaHkwzNztGJJiLxRylvxrYhsIDTUbYNGqaOQDcUvRDUw+9LzA+satRV4P+4yMcKgVf6YAD5T8KZHbB8OgbeuAI7ou76bPd4vHoBvRGW0MmiUWyey+kMKw7lbg== Received: from SJ0PR03CA0002.namprd03.prod.outlook.com (2603:10b6:a03:33a::7) by IA0PR12MB8839.namprd12.prod.outlook.com (2603:10b6:208:493::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.7; Thu, 10 Sep 2026 03:34:26 +0000 Received: from SJ1PEPF00002312.namprd03.prod.outlook.com (2603:10b6:a03:33a:cafe::83) by SJ0PR03CA0002.outlook.office365.com (2603:10b6:a03:33a::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.406.7 via Frontend Transport; Thu, 10 Sep 2026 03:34:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00002312.mail.protection.outlook.com (10.167.242.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:25 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:10 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:09 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:34:08 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 6/8] iommu: Introduce TDISP T=0 state for confidential IOMMUs Date: Wed, 9 Sep 2026 20:32:49 -0700 Message-ID: <0421799346a09bf7f32727330ca1044de05f46ba.1789010941.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|IA0PR12MB8839:EE_ X-MS-Office365-Filtering-Correlation-Id: 13e35d5e-fd6e-4a79-f853-08df0eec6985 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700016|23010399003|6133799003|22082099003|20052099010|18002099003|5023799004|56012099006|11063799006|10067099003; X-Microsoft-Antispam-Message-Info: WeW1IMv1PS9S8kVpZBeD3PbmM1NeMIIHJgfQ0B+6GvwmnGSDlyUbtA/YiEC5wdr+fQH/cjO3Mf6BQLPBeJw/34xI0wwLi8rtwS+Dg3HewAb/dtLqqSouk7ebv4dzyo5FIl0gQfhZrlS1aaURPmbHBBgaXDBV2j16uUaGVa0LpodYxl9LC+NZFEyfZV9WdWR/qTCyjrrcLf77ceG1KONmQkAPNqrwtFO3iYeIbt8Sqxyf4hHs5vVyf6/OqWhOmIGYb57UjPRtcFSypo3fSTTeuFdBgyWG//7FnbMK3iJHHDsQJyx5OTXvrj8iPF9i73P53YnLZsiONmQ8xFsBRemnXK+Ke8k8/oAflisxEAgzrDc9Xy1Dm3guR5FSbclkxznkZnc0P6e9uNLGHB8CFMsFLdCL18hjNgMdFvdnWEt2d7/u3v78fy0c/6TzZKavR3GQIyKcY3SxNeDsRU0r4AwaikqdNc14vzMKfZWvwV2gSS/bXZYvsIYawSl+ht26ZDUvkQ2CatceN8MxDmRnXFiYpOFBSVQWTXymLMy8+ySrm9q3odKYBXnp/WUi6VXt3TM/FnOL0IETOMAFdEQluQ0+Z8qn/2kNZGrn+Fiz/Z7d7vL7X+vj9taHkRcAz6O3ddJW51meYD9OosTSB6Pgml7Lvkm89K12lpe0NI15gEP8z8lPpp/xo2Ukw6uyl/tsRMSj/BTaYlb+uPhduM7MKfhrKg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700016)(23010399003)(6133799003)(22082099003)(20052099010)(18002099003)(5023799004)(56012099006)(11063799006)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tjm7W6rZ7JoUZhUHKLs05wTqgqeN0uqSvMFuplbfbu/Ue2rhpvb4NPXuOSE9nSrbCGW8dHQYn83Odg9ABJTRKPly0zQFHJjFWIeVN/3a4nbmS1HeqM0LfpPKCo4wUOR4k3hqdXP7qWpqH9R4ddiNIo/9ce0o9AO8W6mHzxVIR7FM6bgkN1YJMLTh3V4qLZkTTRL5Tub/C/K7soWd3S+J0hqEOmPUiDy1ixg0RgbYGlPM2N9mwNMPy5wSGjFoZFrQgVZk0CNEDmrZ7Ms8gX2t7kW2m91j5t/zcdvIdgKTMnRnPFNw95x2iBmMwdD680Lpv28OEF52oVLYfoXqwthEscO9Kcz6CVTY9R/pgXf0V4sN23GQ5yNvg+WK9BXoy5g1rHTnu8QyRszmWQCjUfF0Ia9PzMQhnx37zekwnWpe2ARgPB6x6MZv41gR2TlFfjG1 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:25.5169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13e35d5e-fd6e-4a79-f853-08df0eec6985 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8839 Content-Type: text/plain; charset="utf-8" TDISP devices have two independent DMA streams, T=3D1 and T=3D0. In several platforms these streams terminate into different IOMMU environments with different translation tables. For such platforms the IOMMU driver in Linux handles exactly one of the streams. Typically we expect the T=3D1 stream to be linked to the vIOMMU and the T=3D0 stream to simply be left as a no-iommu identity configuration. As the HW has these two different DMA translation environments, the iommu subsystem must participate in switching between them. When the device uses T=3D0, its T=3D1 vIOMMU path should be left in BLOCKING to disable it, and a simplified "T=3D0 IDENTITY" mode is setup within the DMA API. [device: T=3D0] =3D=3D=3D> [hypervisor] =3D=3D=3D> [memory] | +-- (guest association) --> [confidential IOMMU: blocking DMA] Setting the vIOMMU to BLOCKING also gives up its control of ATS, which is now managed by the core code as part of simplified T=3D0 mode. Suggested-by: Jason Gunthorpe Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen --- drivers/iommu/Makefile | 3 ++ drivers/iommu/iommu-priv.h | 19 +++++++++++++ include/linux/iommu.h | 4 +++ drivers/iommu/iommu-cc.c | 57 ++++++++++++++++++++++++++++++++++++++ drivers/iommu/iommu.c | 17 ++++++++++-- 5 files changed, 98 insertions(+), 2 deletions(-) create mode 100644 drivers/iommu/iommu-cc.c diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 2f05725eaab18..dc91d4cf0ce11 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -6,6 +6,9 @@ obj-$(CONFIG_RISCV_IOMMU) +=3D riscv/ obj-$(CONFIG_GENERIC_PT) +=3D generic_pt/fmt/ obj-$(CONFIG_HYPERV) +=3D hyperv/ obj-$(CONFIG_IOMMU_API) +=3D iommu.o +ifdef CONFIG_ARCH_HAS_CC_PLATFORM +obj-$(CONFIG_IOMMU_API) +=3D iommu-cc.o +endif obj-$(CONFIG_IOMMU_SUPPORT) +=3D iommu-pages.o obj-$(CONFIG_IOMMU_API) +=3D iommu-traces.o obj-$(CONFIG_IOMMU_API) +=3D iommu-sysfs.o diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index aaffad5854fc9..06e233ac4662f 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -8,6 +8,25 @@ #include #include =20 +#ifdef CONFIG_ARCH_HAS_CC_PLATFORM +void iommu_tdisp_enter_t0(struct device *dev); +void iommu_tdisp_exit_t0(struct device *dev); +#else +static inline void iommu_tdisp_enter_t0(struct device *dev) +{ +} + +static inline void iommu_tdisp_exit_t0(struct device *dev) +{ +} +#endif + +static inline bool iommu_using_t0_stream(struct device *dev) +{ + return dev->iommu->iommu_dev->confidential && + !dev->iommu->tdisp_t1; +} + static inline const struct iommu_ops *dev_iommu_ops(struct device *dev) { /* diff --git a/include/linux/iommu.h b/include/linux/iommu.h index bd68532e7f3be..e3ed0dc538e0d 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -871,6 +871,9 @@ struct iommu_fault_param { * @max_pasids: number of PASIDs this device can consume * @attach_deferred: the dma domain attachment is deferred * @pci_32bit_workaround: Limit DMA allocations to 32-bit IOVAs + * @tdisp_t1: device uses its confidential IOMMU's T=3D1 stream. A zero va= lue + * means T=3D0, where the T=3D1 stream remains blocked while th= e core + * owns required DMA operations such as ATS. * @require_direct: device requires IOMMU_RESV_DIRECT regions * @shadow_on_flush: IOTLB flushes are used to sync shadow tables * @@ -886,6 +889,7 @@ struct dev_iommu { u32 max_pasids; u32 attach_deferred:1; u32 pci_32bit_workaround:1; + u32 tdisp_t1:1; u32 require_direct:1; u32 shadow_on_flush:1; }; diff --git a/drivers/iommu/iommu-cc.c b/drivers/iommu/iommu-cc.c new file mode 100644 index 0000000000000..d107b39696a08 --- /dev/null +++ b/drivers/iommu/iommu-cc.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TDISP devices can have separate T=3D0 and T=3D1 DMA streams that termin= ate in + * different IOMMU environments. The Linux IOMMU driver manages the T=3D1 = stream + * while the T=3D0 stream uses the physical path. + * + * [device: T=3D0] =3D=3D=3D> [hypervisor] =3D=3D=3D> [memory] + * | + * +-- (guest association) --> [confidential IOMMU: blocking DMA] + */ +#include +#include + +#include "iommu-priv.h" + +/** + * iommu_tdisp_enter_t0 - Prepare @dev while TDISP is T=3D0 + * @dev: device entering TDISP T=3D0 + * + * The IOMMU core invokes this helper for a device on a confidential IOMMU + * while TDISP is T=3D0. The device remains associated with its IOMMU whil= e the + * core owns DMA operations required in this state. Enable ATS here when t= he + * device requires it, since the IOMMU driver does not operate ATS while in + * BLOCKED. + */ +void iommu_tdisp_enter_t0(struct device *dev) +{ + struct pci_dev *pdev; + int ret; + + if (!dev_is_pci(dev)) + return; + + pdev =3D to_pci_dev(dev); + if (!pci_ats_required(pdev)) + return; + + ret =3D pci_enable_ats(pdev, PCI_ATS_MIN_STU); + if (ret) + dev_warn(dev, "cannot enable ATS while TDISP is T=3D0\n"); +} + +/** + * iommu_tdisp_exit_t0 - Undo iommu_tdisp_enter_t0() + * @dev: device leaving TDISP T=3D0 + */ +void iommu_tdisp_exit_t0(struct device *dev) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(dev)) + return; + + pdev =3D to_pci_dev(dev); + if (pci_ats_required(pdev) && pdev->ats_enabled) + pci_disable_ats(pdev); +} diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index feff390727d13..7ac6569af6773 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -535,9 +535,17 @@ static int iommu_init_device(struct device *dev) } dev->iommu->iommu_dev =3D iommu_dev; =20 + if (iommu_using_t0_stream(dev)) { + /* + * After probe the iommu has to leave the T=3D1 stream in BLOCKING, + * while the T=3D0 stream will go through the physical path. + */ + iommu_tdisp_enter_t0(dev); + } + ret =3D iommu_device_link(iommu_dev, dev); if (ret) - goto err_release; + goto err_tdisp_t0; =20 group =3D ops->device_group(dev); if (WARN_ON_ONCE(group =3D=3D NULL)) @@ -555,7 +563,9 @@ static int iommu_init_device(struct device *dev) =20 err_unlink: iommu_device_unlink(iommu_dev, dev); -err_release: +err_tdisp_t0: + if (iommu_using_t0_stream(dev)) + iommu_tdisp_exit_t0(dev); if (ops->release_device) ops->release_device(dev); err_module_put: @@ -573,6 +583,9 @@ static void iommu_deinit_device(struct device *dev) =20 lockdep_assert_held(&group->mutex); =20 + if (iommu_using_t0_stream(dev)) + iommu_tdisp_exit_t0(dev); + iommu_device_unlink(dev->iommu->iommu_dev, dev); =20 /* --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013058.outbound.protection.outlook.com [40.93.201.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3E11379C39 for ; Thu, 10 Sep 2026 03:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011277; cv=fail; b=bUri68fY761ZwG+L0oM5DOaualjihhZjvv04ce4dONxd6nWt9seMdtVGaYtdRe6u/vHuE1UhL29DaWorYWcNeDsL+P17iw2MN4+yPfHYUKhs6A/T4Y3ScXsvgv+IwaMbfpQDeWc02zT5Cg1U0W1dIwkxnaMpNiqIwt5XwlvBBBI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011277; c=relaxed/simple; bh=ATDYHncYMCPkvW3NVLxWOUFcz+l6U+ageQjwK6RyPl8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LwHo/Bh5dQqhFISUSMpcVBnH6z6HpM4fXolnEaRFYoQLd5fDhAojkgfv7z1zzWPk+gkB+NDZhC66dmGkL6gsbsa6csruN6hD6pYXTpPX4Q9/Aj1Ksw0OVBn5G4SInAttqHXSczJb5BtHRs5iHIQqTmhYixV4jSGH2QWzd6udN0Y= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=AfvzQQPC; arc=fail smtp.client-ip=40.93.201.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="AfvzQQPC" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RdAR7igF/Qlm3QAqah/vA7PBhgFm1M8CA3czjYcBeNvL/ogjAe/9nfzLr47fx45Trp2mTnRyRejg+FWrOTxuod5bGc1hPDMRfapmBdw/JSNmjpqDYGHbLeRa/8RKR0VTlGcmoQu4Qn+X03cTmqfHLzwzDDkEl0YhMPGj6uDBMx+rrk6nFBvo1EVHFGOIYuT89OH/8sybeT2vlCDStaXwJ49xJ/agAnxF3ya49PwrClBSiFhlL9eeJHIyPYNAtvqBzTENE4bG4Jw599pC9NznIaIVLyq8RZdHZAAYb3unQYpwZIdNK/HNB8l2lUNX6j04JmQT8uQfc0TYd0EOiXUFRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pR7rMdEFTQNYMRzOAZb2SqWfOzcx0BhWw6w7SMZW5fk=; b=i5M40sFXCwAs36Tw7v7mQYiMF6hmTrJrc0UdVNzi42YimDsKszYiaBP0UNBteqV4ASPryEDRPbOhVQyMl/9ZpBPUvof2g6oPZMeA/gZSaTs0hmsFngRcp8xCZhVCNnkN87mhLylY+Sxtvm4k2+6k16Q2q+GvziPTD0IH/v68kaB/V5Q886AQs9O4dv/P0UzVBPey4nFM5lHS2R80V4788mne7PtfRLRxMZ31xAKuQk4yderTRNDMeZPZQWkTX+VEH1yhyqA9StpMMer2wS2bBPGZ4yDxNS71BH3lFZmuBgUN3WJ4GVIzGYhapRMsOf6UmwYZNLMROOi8lT8UhH/DyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pR7rMdEFTQNYMRzOAZb2SqWfOzcx0BhWw6w7SMZW5fk=; b=AfvzQQPCNwzAnInQIpFbE7j1cWSkbceaIAv04liT91/mWv1lKl/b14H+0AsPKuPsW6mAinoqNwonO5uMJ/PT2Q0rVYk7OekG+FjnxCiO3wNgiVgeayXmt1udT0DOm7iIu+Vqhq7NmV0pQj1tVwcNfm1qy1KpgljaLN/v2VncYE/8hLJveo0ZnDs9BSnozbqn2uaVLc4BRUrDg+AYKCRUH9WyuFDfIbWbT3gfsKIPXWR6U3p01jbp+drnZ0zf1bZUMajUsXyvQTBxE66kf0P+P2+L6gRYPOBQmhYGp2uVyw6fts5BVD2HINaL2FplbHVHQ2XvDY5YnhEocl7VNxBw1w== Received: from DS2PEPF00004561.namprd21.prod.outlook.com (2603:10b6:f:fc00::505) by SJ2PR12MB8690.namprd12.prod.outlook.com (2603:10b6:a03:540::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.8; Thu, 10 Sep 2026 03:34:25 +0000 Received: from CY4PEPF0000FCC5.namprd03.prod.outlook.com (2603:10b6:92f::1006:0:b) by DS2PEPF00004561.outlook.office365.com (2603:10b6:f:fc00::505) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.9 via Frontend Transport; Thu, 10 Sep 2026 03:34:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CY4PEPF0000FCC5.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:25 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:12 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:12 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:34:10 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 7/8] iommu: Park TDISP T=0 devices in the blocking domain Date: Wed, 9 Sep 2026 20:32:50 -0700 Message-ID: <0d57c59aa3cae891e9d3e07e939e13918a4e99a0.1789010941.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|SJ2PR12MB8690:EE_ X-MS-Office365-Filtering-Correlation-Id: 40b20b06-b649-4e0c-a446-08df0eec694c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|7416014|23010399003|18002099003|22082099003|56012099006|10067099003|11063799006; X-Microsoft-Antispam-Message-Info: YYwnoETDeB29vWKFMVvg7RO2Pd7rdeuRPp3YJFsEnq1UDBdFwKP/S7/tWsYWzzXkS3DFR6e5Xz+XorgPLHL4wTUaj7YWRr5xCGYG712xKkJ2TAfIHW8dL+DGQO9V7GrVI8N4X2nP1zEc6wpb/k4TlUmR4HTyidT1G5wm0K7ue0dqMjVse8d7WF3HyyotM/nE/yAoen9jt7nsojSamEs3cE9xX5WiEt8ro1FSClWDIZFru8dN8xniu46jAhkAGLe2Mq3exiImDz9KCU+t8Ebn9dwTQK3toC4jpbRGRaUmlNPs3GbO1YryaHDN+VMMezdUZ3qdMS5YUF4vTBSbl9byO63blls7p220YiCIOQFGc8rXOPjJvr7XRUF/ps7FvD2+j80nyLf7wRJyywPHAfEfzAuM7Z/rxF8aH2xuUyj1UvRlsTkK4gcdGdN0qY97GwNKEkI4BZ994vg6frkzlAoeQTw02DaEHyoiUzyWBXkz8yvgtOmArrAhdGYKKyA5OfJyz0jEluPWqqVcy04I7LQnfI6L/hZkA0Tx4INV8U6LxTw1tgBxfxsJnmmi3Jg9Uslyxn9rAHUP3/A2SMLArb0Zyjl+uee3LXW6NYmpLPWc3VH9TkBrk55mMhPQC+uoxX1anr84jAtWnsjwRbHfAjteLfc4xv6I66bd0x7Ow1eFMx7d1WeS9F/b464aNQmJhf4wS0gwvOczAJR61l+vMtfhJA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(7416014)(23010399003)(18002099003)(22082099003)(56012099006)(10067099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HG0HAuL0wF2B5+nr3w59B7NSXSt8RvQVq7qna2F5jF+SIefitmyUt5lkmAE8MAdjtEdqsbU6LqjIqydbjhuHJf1bpggihiTbJbpuwqlzvg/1jClO7GV/meITRqKkV+JFWZF4Zy6giIDPJ7C06IIh4UPbtrVgMwCvdKeCyqWcqxmikXf2aUmwsuPBWFVOh5ziJWdLa1hpACLTVAmEx9k2wurLc3go39DR/hYQS17FkQ6NSNO1oVIIzg8e1OcJhOuEPMJPd9+rygyQo0shoaDsjC/Uy/Vig83pDHzxCMdpJKSyLIo+d5orrIb4ipTELX9IWIbh+TYFlnY+zwoyMwtTg2nq3+oUPeTcuN7ViGwjCioiiZiOGsGqrN8U2EjH1h3yExMR3APO+ZEk11RsY759t0b30km33AcfglzHUnWVtGGwDE7DL5g6JiudkDnxFvfn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:25.0672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40b20b06-b649-4e0c-a446-08df0eec694c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8690 Content-Type: text/plain; charset="utf-8" A TDISP T=3D0 device stays associated with its guest T=3D1 vIOMMU, yet does= n't use that IOMMU for DMA translation. Instead, park its guest-visible stream in the driver's blocking domain. Linux's model requires a device to either use T=3D0 or T=3D1. Aside from MS= I, it cannot use T=3D0 for normal DMA once moved into T=3D1 mode, since the de= vice will have IOVA's that are not valid in T=3D0. Select the blocking domain before normal default-domain policy is applied. Direct-map reserved regions are still fine, because the T=3D0 stream always goes to an identity mapping. Skip them here, as recording the request would only refuse the device its blocking domain. Reject sysfs domain changes, driver-managed group attachment, and any PASID attachments that would install a translating domain. The state is uniform across each group because all devices on a confidential IOMMU start in T=3D= 0. Suggested-by: Jason Gunthorpe Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen --- drivers/iommu/iommu.c | 49 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 7ac6569af6773..d6b00e0373f5c 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1238,6 +1238,14 @@ static int iommu_create_device_direct_mappings(struc= t iommu_domain *domain, unsigned long pg_size; int ret =3D 0; =20 + /* + * The direct-map reserved regions are still fine because the T=3D0 stream + * always goes to an identity mapping. Skip them: recording the request + * would only refuse the device its blocking domain. + */ + if (iommu_using_t0_stream(dev)) + return 0; + pg_size =3D domain->pgsize_bitmap ? 1UL << __ffs(domain->pgsize_bitmap) := 0; =20 if (WARN_ON_ONCE(iommu_is_dma_domain(domain) && !pg_size)) @@ -1790,11 +1798,22 @@ __iommu_group_alloc_default_domain(struct iommu_gro= up *group, int req_type) static struct iommu_domain * iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) { - const struct iommu_ops *ops =3D dev_iommu_ops(iommu_group_first_dev(group= )); + struct device *first =3D iommu_group_first_dev(group); + const struct iommu_ops *ops =3D dev_iommu_ops(first); struct iommu_domain *dom; =20 lockdep_assert_held(&group->mutex); =20 + /* + * When in T=3D0 mode the T=3D1 vIOMMU must always be set to BLOCKED to + * release control of ATS. + */ + if (iommu_using_t0_stream(first)) { + if (!ops->blocked_domain) + return ERR_PTR(-EINVAL); + return ops->blocked_domain; + } + /* * Allow legacy drivers to specify the domain that will be the default * domain. This should always be either an IDENTITY/BLOCKED/PLATFORM @@ -2399,6 +2418,10 @@ static int __iommu_attach_group(struct iommu_domain = *domain, !domain_iommu_ops_compatible(dev_iommu_ops(dev), domain)) return -EINVAL; =20 + /* A domain cannot be attached while using the T=3D0 stream. */ + if (iommu_using_t0_stream(dev)) + return -EINVAL; + return __iommu_group_set_domain(group, domain); } =20 @@ -3325,6 +3348,12 @@ static ssize_t iommu_group_store_type(struct iommu_g= roup *group, goto out_unlock; } =20 + /* Default domain changes are not allowed while using the T=3D0 stream. */ + if (iommu_using_t0_stream(iommu_group_first_dev(group))) { + ret =3D -EINVAL; + goto out_unlock; + } + ret =3D iommu_setup_default_domain(group, req_type); if (ret) goto out_unlock; @@ -3690,6 +3719,12 @@ int iommu_attach_device_pasid(struct iommu_domain *d= omain, goto out_unlock; } =20 + /* PASID cannot be used on the T=3D0 stream. */ + if (iommu_using_t0_stream(dev)) { + ret =3D -EINVAL; + goto out_unlock; + } + for_each_group_device(group, device) { /* * Skip PASID validation for devices without PASID support @@ -3783,6 +3818,12 @@ int iommu_replace_device_pasid(struct iommu_domain *= domain, goto out_unlock; } =20 + /* PASID cannot be used on the T=3D0 stream. */ + if (iommu_using_t0_stream(dev)) { + ret =3D -EINVAL; + goto out_unlock; + } + entry =3D iommu_make_pasid_array_entry(domain, handle); curr =3D xa_cmpxchg(&group->pasid_array, pasid, NULL, XA_ZERO_ENTRY, GFP_KERNEL); @@ -4017,6 +4058,12 @@ int iommu_replace_group_handle(struct iommu_group *g= roup, return -EINVAL; =20 mutex_lock(&group->mutex); + /* Like attach, replacement is not allowed when using the T=3D0 stream. */ + if (iommu_using_t0_stream(iommu_group_first_dev(group))) { + ret =3D -EINVAL; + goto err_unlock; + } + entry =3D iommu_make_pasid_array_entry(new_domain, handle); ret =3D xa_reserve(&group->pasid_array, IOMMU_NO_PASID, GFP_KERNEL); if (ret) --=20 2.43.0 From nobody Fri Sep 25 17:42:21 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010061.outbound.protection.outlook.com [52.101.201.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1550E3A63E4 for ; Thu, 10 Sep 2026 03:34:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.201.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011281; cv=fail; b=tGfsBEG7+MPiE8VRy0la9JOlqJml1lxO8wzi7WRvZJqJvCRHxeDuxfP+W8WC+f6zCZ3ARoryCLDfz5pz1EJjsxO1SR87BzHLXSnpI367RAakXjfX62BiYJ2JIUpdFwL39d2VO7Z9JXz0jggC0LQCMMtBslh/2divfAPUTjXO5UE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789011281; c=relaxed/simple; bh=VSlpiOMejjdvUjggnEuZ+y9cCG1SsIHaN7TGkHcmN1g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RvRLoDxEsOhicTha1tHi03LzoMeCg89eijn05aEIDUfZy8ds70AIHxqt4lg4J/dSSBSDRTXFcRX+irLSihqUTcb7bHl8he6E7jnYK7rq5Rqq3zCO/8pC2SlbSfi7GT5HFAxLOsHGDbHPqjhnftGGggyVGqxYypZJfa0Z4jaxdss= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=CiNJiENt; arc=fail smtp.client-ip=52.101.201.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CiNJiENt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LBCX+Zr58bwO9BMcKYj3xS9d/AG5KhqwfRQJl7Rp56JuI9gYnOtnuug8fg79tfSqEJUmLQ5SF57+TvlngO2xytjkFahwaTUfQfqN/+Fg7jahyp/6Mv3mvcUiugMKccrYBW+dhms9K6K3clcuRiJZx6jMyPpQB+/yq2MD1MBP8SmPypX/iueaSfmyue1MdlzPBtCn47QNNF8/le0gkzLK/4svreBxWZsHZzUo2xQszRDTlMh9EQJrpnukfkJiQucUNmfr6UIbvYbk3UYEUwI0P92+GmnW8xLueNHpiyhJPBjcbzcx5A88fTVMku1hyVXIGjFfGIZejTmBxCWp0qcKSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KRgxd35oIwHiXkDjOaH6BgCMwgA2OzF2U7ApjvKEm8Y=; b=gXIBDKmSAPYrWispAEIDv2uQKyPREULVEI5eR4HcCRJmcPHuIgy/NuwfiEPPWzCl3BzCP0QSvZAx94VhEVv2MqR47OD6Dxt66I7O1cjtxvnWbGXI7AKX4JSHr9djfsq9BkvvQ9DbE3Obnr5b8OycXPxxHGqEx6u3YEgPcSWviiqgkBQ3q+ZCSTgjRfTWrFQ3FZI4ht2BviD2JSbWTOCBp2yAgdzW1ELlVrgvKPJrDjBrL80uhs35pDtTo5Qw+nF/KxHRPnkv+8o+BNQIF9kovDQO6Th8CIpSA+QxHPeCQzK0xzrJ/hpOdPz2+z0xjYFFcuw+oWw5DIARdxBLpM0QSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=arm.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KRgxd35oIwHiXkDjOaH6BgCMwgA2OzF2U7ApjvKEm8Y=; b=CiNJiENtkbwz/475ewsRq8NzHc0iu9MBEQNXJRaL6LzU4m6F5ra6JBy24JbfaoNw5M5KxY3t5puDb0xHeKLLRQt1ycHqyT+4Sa9as+17nGpo7i5ondmvfGYjTqkbLrya3zDDqG09skXI4wfDfmHez6lYVZANQD4NEmszFC+YCwd+9OtdwDyKsk4l6XxkGQm+PhdeIG59toFUX7E8Rz+Y8tpAzKtTt2TL5xA1+PymTKL5+Yy8XXWXQFFL9SsjmOWTXiAgwjHVgCDz0kaPrAfuwIMroRX3yyTOTPmokiDRlECkMSVVU5y9u4Fim/GFm/+CuBtzvFtHs1jkvjGWrTJ6Og== Received: from DS2PEPF00004563.namprd21.prod.outlook.com (2603:10b6:f:fc00::519) by BN7PPF9E4583E15.namprd12.prod.outlook.com (2603:10b6:40f:fc02::6dc) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.15; Thu, 10 Sep 2026 03:34:28 +0000 Received: from CY4PEPF0000FCC5.namprd03.prod.outlook.com (2603:10b6:92f::1006:0:b) by DS2PEPF00004563.outlook.office365.com (2603:10b6:f:fc00::519) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.382.9 via Frontend Transport; Thu, 10 Sep 2026 03:34:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CY4PEPF0000FCC5.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Thu, 10 Sep 2026 03:34:27 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:14 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 9 Sep 2026 20:34:14 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 20:34:12 -0700 From: Nicolin Chen To: Jason Gunthorpe , Catalin Marinas , Will Deacon , , Robin Murphy , , Danilo Krummrich , Marek Szyprowski , CC: Mark Rutland , Greg Kroah-Hartman , Suzuki K Poulose , Gavin Shan , Vikram Sethi , "Anshuman Khandual" , Shanker Donthineni , Mostafa Saleh , , Thomas Huth , Marc Zyngier , Ryan Roberts , , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , "Florian Fainelli" , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , Shameer Kolothum , , , , , Sonang Patel , Ankit Agrawal Subject: [PATCH v1 8/8] iommu/arm-smmu-v3: Probe a guest-level Realm VSMMU via RSI commands Date: Wed, 9 Sep 2026 20:32:51 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|BN7PPF9E4583E15:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b2db353-7b1c-431a-2440-08df0eec6ad3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|23010399003|1800799024|7416014|82310400026|56012099006|11063799006|10067099003|6133799003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: AZdwUii2V9mR1lEuv2Aj5/w49KLjDC4KPyV15MmoxlDculnceXlZ5rpFBN6pbha2wYss3BGK6r1d68AgACIm6AWlORIfM9ZjB9NAFjUmNo31SEsuTP3svcG+fIubrgtDCFcIwJ5L6QLWD8z3PhmuKFwl5t7LMnZsYb2iPH4Q08Yi3W69s8s9X0eIAVL6PVVIzAqkY0KW05Fk4tYBxIMcm0G9HVDB6wESN2P+ecI8ljBG083ePiVJCrLqkik4Gy/Vl3S76bTCRkeZCZQ63NoO8cPicK/FcozcZWhqu6UHRrITsn1qWSjDZrskzd5h5Pg1gWrKYrhVD7N+Bpgk+ft4W1OQPNXD4IJLZhyVS+CcW77bKpzgEmt5saNrceTZBoPpjS1gVV+vuaNGIQLCLAlHz5RE7MwDiajfD/+nSS/lLzIZL1a6tRID/MMV8wHRpLtnuor8+d8cUDzbxaMTm854P1PY3u7vVYxcjG+guyKPjlo1GfNZ3ZGk9xTdN+wOlRYYwU7f34cix9faWaDCDx85thCkLU/9+DoPpFkKzSfxGuuJQ+B6I3P4kkV81aSypfEPBmQuHMWQ+/t1Hl+jIKwO8hZX+TV4Nn097Ud7fOJcJYKEznd6CV2FI5lDqF5ZNzMCEtrLrIUrnEjqDH2iIMtmzYgnpLAH83yr5jNx081rlKFrzDa/JqYbX5JCHgJSiRZIEVZ1c4Pdtv5V1TAyVUYREw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(23010399003)(1800799024)(7416014)(82310400026)(56012099006)(11063799006)(10067099003)(6133799003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5tcXMWB5evienxZfpzwAByGBioR8es5/7wO0wmxHEZYpc1y8WIfYCUdGwMgRSBjVZcTFitFqqTwbEPRCSodmQoSpQCYOxfeAvCk09uUGGvhUSmcP7xFhJ/3unW7zKuPxrMnTCgm6FonZxyqnfMnGxSzEdn/jBhBWbQkR7G3vnV1VaZOypyylSgCLuo/x+8RPJnC5TEYPn9yhLDk1UMPwI1oi5ZelDggnbG8m9Hx5LO35uJBBjc/XhEarvSZ62xhTowCOeBzZWc73jf4cRU7pm9100hEj+0KxoAnVHtvJQJ0OqRLyqaOLV2q7zrOAa9GgmwBeZJGdjsR2yCUctu1hL03XlNx9zrYl63f4jRZz6wTkYMhXBGIkbenlBjl3F5G/Iq7758uVwEGAuLvtWqrbX/+e2yJZW3m6IHl0y7DNzZugT36WwH1bLiP1WMKjd6M2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 03:34:27.6257 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b2db353-7b1c-431a-2440-08df0eec6ad3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF9E4583E15 Content-Type: text/plain; charset="utf-8" In CCA, the ACPI/etc doesn't tell the OS whether the SMMU is a confidential T=3D1 instance or a normal T=3D0 one. Instead, it has to be learned by issu= ing a trusted RSI. Before the kernel can operate the trusted T=3D1 IOMMU, it al= so has to validate all the information that it gets from ACPI against the true information that it gets from the RSI call, to ensure the ACPI is correct and prevent substitution attacks. Use RSI_VSMMU_GET_INFO during probe and require the returned register range to match firmware. Then use RSI_ARCH_DEV_ACTIVATE before mapping registers. Currently the driver doesn't support a T=3D0 SMMU inside a realm. For examp= le it doesn't make the page table allocations into shared memory. If we are in a realm reject any SMMU that is not T=3D1. Once the SMMU is activated, its DMA will follow the DEV_FLAG_DMA_CC_PRIVATE rules. It must set that flag to ensure its coherent allocations for its own structures are allocated from private memory, not the SWIOTLB shared pool. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 55 +++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5732f3ba0122d..972815c54b11f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -11,9 +11,11 @@ =20 #include #include +#include #include #include #include +#include #include #include #include @@ -5507,6 +5509,53 @@ static struct arm_smmu_device *arm_smmu_impl_probe(s= truct arm_smmu_device *smmu) return ERR_PTR(ret); } =20 +static void arm_smmu_clear_realm_private(void *dev) +{ + dma_set_cc_private(dev, false); +} + +static int arm_smmu_probe_realm_vsmmu(struct arm_smmu_device *smmu, + const struct resource *res) +{ + struct device *dev =3D smmu->dev; + unsigned long rsi_ret; + phys_addr_t top; + + /* + * Currently the driver does not support a T=3D0 SMMU inside a realm. For + * instance it does not make the page table allocations into shared + * memory. If we are in a realm reject any SMMU that is not T=3D1. + */ + rsi_ret =3D rsi_vsmmu_get_info(res->start, &top); + if (rsi_ret !=3D RSI_SUCCESS) { + dev_err(dev, "RSI_VSMMU_GET_INFO failed for %pr: %lu\n", res, + rsi_ret); + return -ENODEV; + } + + if (top !=3D res->end + 1) { + dev_err(dev, "VSMMU range %pr ends at %pa\n", res, &top); + return -EINVAL; + } + + rsi_ret =3D rsi_arch_dev_activate(res->start, RSI_ARCH_DEV_SMMUV3); + if (rsi_ret !=3D RSI_SUCCESS) { + dev_err(dev, "RSI_ARCH_DEV_ACTIVATE failed for %pr: %lu\n", res, + rsi_ret); + return -EIO; + } + + /* + * Once activated, the SMMU DMA follows DEV_FLAG_DMA_CC_PRIVATE so its + * queues and tables are allocated from private memory, not the SWIOTLB + * shared pool. It only translates for a device we've requested the RMM + * to put into T=3D1. + */ + iommu_device_set_confidential(&smmu->iommu, dev); + + return devm_add_action_or_reset(dev, arm_smmu_clear_realm_private, dev); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -5542,6 +5591,12 @@ static int arm_smmu_device_probe(struct platform_dev= ice *pdev) } ioaddr =3D res->start; =20 + if (is_realm_world()) { + ret =3D arm_smmu_probe_realm_vsmmu(smmu, res); + if (ret) + return ret; + } + /* * Don't map the IMPLEMENTATION DEFINED regions, since they may contain * the PMCG registers which are reserved by the PMU driver. --=20 2.43.0