From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A42BC54CF7F; Tue, 8 Sep 2026 13:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872752; cv=none; b=qU7la0vjETfiAnF/4rUkYy4fGDsXGwMbX++SXRpxfiBDshVPMOEsUx5bo/56gszTF+DoZXa0FqIRGBH4UGMmzybH6EcTbFU3bk+LqMGI0psDsr7hMksy9WxAbFs0uplHxhOdJ4GRfcc44Dwe+HHJi+6+HfvlziNHlwVXC3g1hNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872752; c=relaxed/simple; bh=jWCyyfZ9I3VCtLkKmk044coxRXktwvjMCKi5KK2n5aI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ndjwC2o+47NRs+KDMSq0VqxhhCC20Zq3+GIbJXxKzzBOFTspLmjbQaQq5J83ZBmTgf2kqiuuDRv6dMAWAh/1gwVQIfmjxkXKZCMpE754LjjJEvpZMQTobshiMtSd5ASVlQa7EFx55lrP4QiIdQRjvrZAhx2lMx0KlaMshMF2Hsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hfPLr6sn0zKHN6G; Tue, 8 Sep 2026 21:05:40 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 4B2854058D; Tue, 8 Sep 2026 21:05:42 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S3; Tue, 08 Sep 2026 21:05:41 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 01/26] perf capstone: Symbolize address operands to match objdump on arm64 Date: Tue, 8 Sep 2026 13:05:04 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S3 X-Coremail-Antispam: 1UD129KBjvJXoWxtw15AF13JFWDKFW5Gr1rZwb_yoWfWFW7pa 1kC345Xrs5JF1fWws5Ja1kX343K393XF1Yk3y7C3ySkrnIgrn3JayxKFya9Fy5GrykGw47 tFs0yr45Wrs3Jr7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYx C7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C26cxK 6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_Wryl IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWx JVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa7sRm tCOUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Capstone currently outputs address-bearing instructions with a raw hex value prefixed by '#', without symbolic resolution. This differs from objdump output and leads to parse failures in jump__parse() and arm64_mov__parse() on arm64. Example of the mismatch: Current: b #0xffff8000800114c8 Objdump: b ffff8000800114c8 Current: adrp x18, #0xffff800081f5f000 Objdump: adrp x18, ffff800081f5f000 Fix this by extending symbol__disassemble_capstone() to: - Enable CS_OPT_DETAIL for arm64 to access instruction group info. - Detect instructions with address operands requiring symbolization (jump/call/branch/adr/adrp) via opcode or Capstone group ID. - Resolve target addresses to symbols via resolve_symbol_from_addr(). - Format output to match objdump's style (strip '#' prefix, add symbol and offset). Signed-off-by: Tengda Wu --- tools/perf/util/capstone.c | 185 +++++++++++++++++++++++++++++-------- tools/perf/util/disasm.c | 5 + tools/perf/util/disasm.h | 1 + 3 files changed, 153 insertions(+), 38 deletions(-) diff --git a/tools/perf/util/capstone.c b/tools/perf/util/capstone.c index 74213daf8786..7f82c33e3464 100644 --- a/tools/perf/util/capstone.c +++ b/tools/perf/util/capstone.c @@ -3,6 +3,7 @@ =20 #include #include +#include #include =20 #include @@ -31,6 +32,10 @@ #define CS_MODE_RISCVC 4 #endif =20 +#if CS_VERSION_MAJOR < 4 +#define ARM64_GRP_BRANCH_RELATIVE 7 /* =3D CS_GRP_BRANCH_RELATIVE */ +#endif + #ifdef LIBCAPSTONE_DLOPEN static void *perf_cs_dll_handle(void) { @@ -225,6 +230,12 @@ static int capstone_init(uint16_t e_machine, csh *cs_h= andle, bool is64, bool is_ * on x86 by investigating instruction details. */ perf_cs_option(*cs_handle, CS_OPT_DETAIL, CS_OPT_ON); + } else if (arch =3D=3D CS_ARCH_ARM64) { + /* + * Same as x86: arm64 needs instruction details to resolve + * symbolic addresses. + */ + perf_cs_option(*cs_handle, CS_OPT_DETAIL, CS_OPT_ON); } =20 return 0; @@ -292,16 +303,44 @@ ssize_t capstone__fprintf_insn_asm(struct machine *ma= chine, struct thread *threa return printed; } =20 +static int resolve_symbol_from_addr(struct map *map, u64 addr, + const char **sym_name, u64 *sym_offset) +{ + struct map *found_map =3D NULL; + struct symbol *sym; + u64 al_addr; + u64 ip =3D map__objdump_2mem(map, addr); + + if (dso__kernel(map__dso(map))) { + /* + * The kernel maps can be split into sections, let's + * find the map first and then search the symbol. + */ + found_map =3D maps__find(map__kmaps(map), ip); + if (found_map =3D=3D NULL) + return -1; + map =3D found_map; + } + + /* convert it to map-relative address for search */ + al_addr =3D map__map_ip(map, ip); + + sym =3D map__find_symbol(map, al_addr); + map__put(found_map); + + if (sym =3D=3D NULL) + return -1; + + *sym_name =3D sym->name; + *sym_offset =3D al_addr - sym->start; + return 0; +} + static void print_capstone_detail(struct cs_insn *insn, char *buf, size_t = len, struct annotate_args *args, u64 addr) { int i; struct map *map =3D args->ms->map; - struct symbol *sym; - - /* TODO: support more architectures */ - if (!arch__is_x86(args->arch)) - return; =20 if (insn->detail =3D=3D NULL) return; @@ -309,7 +348,8 @@ static void print_capstone_detail(struct cs_insn *insn,= char *buf, size_t len, for (i =3D 0; i < insn->detail->x86.op_count; i++) { struct cs_x86_op *op =3D &insn->detail->x86.operands[i]; u64 orig_addr; - struct map *found_map =3D NULL; + const char *sym_name =3D NULL; + u64 sym_offset; =20 if (op->type !=3D X86_OP_MEM) continue; @@ -320,40 +360,114 @@ static void print_capstone_detail(struct cs_insn *in= sn, char *buf, size_t len, =20 /* get the target address */ orig_addr =3D addr + insn->size + op->mem.disp; - addr =3D map__objdump_2mem(map, orig_addr); - - if (dso__kernel(map__dso(map))) { - /* - * The kernel maps can be split into sections, let's - * find the map first and then search the symbol. - */ - found_map =3D maps__find(map__kmaps(map), addr); - if (found_map =3D=3D NULL) - continue; - map =3D found_map; - } - - /* convert it to map-relative address for search */ - addr =3D map__map_ip(map, addr); - - sym =3D map__find_symbol(map, addr); - if (sym =3D=3D NULL) { - map__put(found_map); + if (resolve_symbol_from_addr(map, orig_addr, &sym_name, &sym_offset)) continue; - } =20 - if (addr =3D=3D sym->start) { + if (sym_offset =3D=3D 0) { scnprintf(buf, len, "\t# %"PRIx64" <%s>", - orig_addr, sym->name); + orig_addr, sym_name); } else { scnprintf(buf, len, "\t# %"PRIx64" <%s+%#"PRIx64">", - orig_addr, sym->name, addr - sym->start); + orig_addr, sym_name, sym_offset); } - map__put(found_map); break; } } =20 +static int print_default_format(struct cs_insn *insn, char *buf, size_t le= n) +{ + return scnprintf(buf, len, " %-7s %s", + insn->mnemonic, insn->op_str); +} + +static void format_capstone_insn_x86(struct cs_insn *insn, char *buf, + size_t len, struct annotate_args *args, + u64 addr) +{ + int printed; + + printed =3D print_default_format(insn, buf, len); + buf +=3D printed; + len -=3D printed; + + print_capstone_detail(insn, buf, len, args, addr); +} + +static bool needs_symbolic_address(struct cs_insn *insn) +{ + int i; + + if (insn->id =3D=3D ARM64_INS_ADR || insn->id =3D=3D ARM64_INS_ADRP) + return true; + + if (insn->detail =3D=3D NULL) + return false; + + for (i =3D 0; i < insn->detail->groups_count; i++) { + if (insn->detail->groups[i] =3D=3D ARM64_GRP_JUMP || + insn->detail->groups[i] =3D=3D ARM64_GRP_CALL || + insn->detail->groups[i] =3D=3D ARM64_GRP_BRANCH_RELATIVE) + return true; + } + + return false; +} + +static void format_capstone_insn_arm64(struct cs_insn *insn, char *buf, + size_t len, struct annotate_args *args) +{ + struct map *map =3D args->ms->map; + char *last_imm, *endptr; + u64 addr; + + print_default_format(insn, buf, len); + /* + * Adjust instructions to keep the existing behavior with objdump. + * + * Example conversion: + * From: b #0xffff8000800114c8 + * To: b ffff8000800114c8 + */ + if (needs_symbolic_address(insn)) { + const char *sym_name =3D NULL; + u64 sym_offset; + + /* Extract last immediate value as address */ + last_imm =3D strrchr(buf, '#'); + if (!last_imm) + return; + + addr =3D strtoull(last_imm + 1, &endptr, 16); + if (endptr =3D=3D last_imm + 1) + return; + + if (resolve_symbol_from_addr(map, addr, &sym_name, &sym_offset)) + return; + + /* Symbolize the resolved address */ + len =3D len - (last_imm - buf); + if (sym_offset =3D=3D 0) { + scnprintf(last_imm, len, "%"PRIx64" <%s>", + addr, sym_name); + } else { + scnprintf(last_imm, len, "%"PRIx64" <%s+%#"PRIx64">", + addr, sym_name, sym_offset); + } + } +} + +static void format_capstone_insn(struct cs_insn *insn, char *buf, size_t l= en, + struct annotate_args *args, u64 addr) +{ + /* TODO: support more architectures */ + if (arch__is_x86(args->arch)) + format_capstone_insn_x86(insn, buf, len, args, addr); + else if (arch__is_arm64(args->arch)) + format_capstone_insn_arm64(insn, buf, len, args); + else + print_default_format(insn, buf, len); +} + struct find_file_offset_data { u64 ip; u64 offset; @@ -446,14 +560,9 @@ int symbol__disassemble_capstone(const char *filename,= struct symbol *sym, =20 free_count =3D count =3D perf_cs_disasm(handle, buf, buf_len, start, buf_= len, &insn); for (i =3D 0, offset =3D 0; i < count; i++) { - int printed; - - printed =3D scnprintf(disasm_buf, sizeof(disasm_buf), - " %-7s %s", - insn[i].mnemonic, insn[i].op_str); - print_capstone_detail(&insn[i], disasm_buf + printed, - sizeof(disasm_buf) - printed, args, - start + offset); + format_capstone_insn(&insn[i], disasm_buf, + sizeof(disasm_buf), args, + start + offset); =20 args->offset =3D offset; args->line =3D disasm_buf; diff --git a/tools/perf/util/disasm.c b/tools/perf/util/disasm.c index 6cfdbabbb8c7..0ba38f70fe1a 100644 --- a/tools/perf/util/disasm.c +++ b/tools/perf/util/disasm.c @@ -203,6 +203,11 @@ bool arch__is_powerpc(const struct arch *arch) return arch->id.e_machine =3D=3D EM_PPC || arch->id.e_machine =3D=3D EM_P= PC64; } =20 +bool arch__is_arm64(const struct arch *arch) +{ + return arch->id.e_machine =3D=3D EM_AARCH64; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPKt6TmWzYQw0V; Tue, 8 Sep 2026 21:04:50 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 6538640578; Tue, 8 Sep 2026 21:05:42 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S4; Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 02/26] perf llvm: Fix arm64 adrp instruction disassembly mismatch with objdump Date: Tue, 8 Sep 2026 13:05:05 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S4 X-Coremail-Antispam: 1UD129KBjvJXoWxWryxGryUCF1fAF43uF1fCrg_yoW5ur45pr ZFkFZ5Xry5Ar1Sv39IkF47Wrn0yrZ2gF4Yg3y3ArWvkr4ftF97C3yxGFy29F1UXryvq3y5 CrZ0vFyUGF1kArJanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUXw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYx C7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C26cxK 6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_Wryl IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWx JVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa7sRk sqAUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The operands of 'adrp' instructions parsed by libllvm are currently represented as raw immediates rather than the "address " format used by objdump. This inconsistency causes arm64_mov__parse() to fail when parsing these instructions during post-processing. Example of the mismatch: Current: adrp x18, 8014 Objdump: adrp x18, ffff800081f5f000 Fix this by manually extracting the target address from the raw adrp instruction via symbol_lookup_callback(). The address is then converted to a specific symbol during symbol__disassemble_llvm() and formatted to match objdump's output, ensuring compatibility with existing parsers. Signed-off-by: Tengda Wu Reviewed-by: Namhyung Kim --- tools/perf/util/llvm.c | 52 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/llvm.c b/tools/perf/util/llvm.c index a0deb742a733..a78845689aa1 100644 --- a/tools/perf/util/llvm.c +++ b/tools/perf/util/llvm.c @@ -9,8 +9,10 @@ #include "symbol.h" #include #include +#include #include #include +#include =20 #ifdef HAVE_LIBLLVM_SUPPORT #include "llvm-c-helpers.h" @@ -108,6 +110,16 @@ symbol_lookup_callback(void *disinfo, uint64_t value, storage->branch_addr =3D value; else if (*ref_type =3D=3D LLVMDisassembler_ReferenceType_In_PCrel_Load) storage->pcrel_load_addr =3D value; + else if (*ref_type =3D=3D LLVMDisassembler_ReferenceType_In_ARM64_ADRP) { + uint64_t adrp_imm; + + /* immhi (bits 23:5) and immlo (bits 30:29) */ + adrp_imm =3D ((value & 0x00ffffe0) >> 3) | ((value >> 29) & 0x3); + adrp_imm =3D sign_extend64(adrp_imm, 20); + + /* Calculate the target page address */ + storage->pcrel_load_addr =3D (address & ~0xfffULL) + (adrp_imm << 12); + } *ref_type =3D LLVMDisassembler_ReferenceType_InOut_None; return NULL; } @@ -228,12 +240,42 @@ int symbol__disassemble_llvm(const char *filename, st= ruct symbol *sym, } } if (storage.pcrel_load_addr !=3D 0) { - char *name =3D llvm_name_for_data(dso, filename, + char *name; + + if (arch__is_arm64(args->arch)) { + /* + * For arm64, replace the immediate operand with + * the resolved address to match objdump's output. + * + * Example conversion: + * From: adrp x18, 8014 + * To: adrp x18, ffff800081f5f000 + */ + char *s =3D strchr(disasm_buf, ','); + + if (s =3D=3D NULL) + goto err; + + s++; + *s =3D '\0'; + disasm_len =3D strlen(disasm_buf); + disasm_len +=3D scnprintf(disasm_buf + disasm_len, + sizeof(disasm_buf) - disasm_len, + " %"PRIx64, storage.pcrel_load_addr); - disasm_len +=3D scnprintf(disasm_buf + disasm_len, - sizeof(disasm_buf) - disasm_len, - " # %#"PRIx64, - storage.pcrel_load_addr); + } else { + /* + * For other archs, append the resolved address + * as an inline comment. + */ + disasm_len +=3D scnprintf(disasm_buf + disasm_len, + sizeof(disasm_buf) - disasm_len, + " # %#"PRIx64, + storage.pcrel_load_addr); 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Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 03/26] perf annotate-arm64: Generalize arm64_mov__parse to support more instructions Date: Tue, 8 Sep 2026 13:05:06 +0000 Message-Id: <872f51108191d20f65fc12f17c796863a36166da.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S5 X-Coremail-Antispam: 1UD129KBjvJXoWxtr1xurWfZFyfCw1kXw48Crg_yoWxJryDpa n2kw1rtr48Wr1Fgws3Jrs2vrn3Ww4fK34a9a48tas3Awsa9ryrKan3KF1akF4rGryxurWU tFnYvryrJr4DJaUanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUWw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYx C7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C26cxK 6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_Wryl IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWx JVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa7sRQ 2-bUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" As the default parser for arm64 instructions, arm64_mov__parse() currently only supports parsing instructions with the 'addr ' suffix. Other instructions are not supported, causing a lack of source and target information for most regular instructions. Generalize arm64_mov__parse to extend its parsing capabilities: 1. Parse 'ops->target.raw' and 'ops->source.raw' by default. 2. Utilize arm64__check_multi_regs() to identify if source and target contain multiple registers. 3. Maintain backward compatibility for instructions containing the 'addr ' suffix. Signed-off-by: Tengda Wu Reviewed-by: Namhyung Kim --- .../perf/util/annotate-arch/annotate-arm64.c | 166 ++++++++++++++---- 1 file changed, 134 insertions(+), 32 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 33080fdca125..151184210691 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -3,6 +3,8 @@ #include #include #include +#include +#include #include #include #include "../annotate.h" @@ -14,59 +16,158 @@ struct arch_arm64 { regex_t jump_insn; }; =20 -static int arm64_mov__parse(const struct arch *arch __maybe_unused, +static bool arm64__is_reg(const char *op) +{ + if (!op || !*op) + return false; + + /* + * General-purpose registers: x0-x30, w0-w30. + * Check for 'x' or 'w' prefix followed by a numeric index. + */ + if ((op[0] =3D=3D 'x' || op[0] =3D=3D 'w') && isdigit(op[1])) + return true; + + /* Special-purpose registers: sp, wzr, xzr. */ + if (!strncmp(op, "sp", 2) || !strncmp(op, "xzr", 3) || + !strncmp(op, "wzr", 3)) + return true; + + /* TODO: Support more registers. */ + return false; +} + +static bool arm64__check_multi_regs(const struct arch *arch, const char *o= p) +{ + const char *p =3D op; + int reg_count =3D 0; + + while (p && *p) { + p =3D skip_spaces(p); + if (*p =3D=3D arch->objdump.memory_ref_char) + p++; + + if (arm64__is_reg(p)) + reg_count++; + + if (reg_count >=3D 2) + return true; + + /* Move to next operand after comma */ + p =3D strchr(p, ','); + if (p) + p++; + } + + return false; +} + +/* + * Duplicate @insn, stripping the comment and trailing whitespace. + * Returns a newly allocated string which the caller must free(), + * or NULL on allocation failure or if @insn is NULL. + */ +static char *rstrip_space_and_comment(const char *insn, char comment_char) +{ + const char *end, *comment; + size_t len; + char *result; + + if (insn =3D=3D NULL) + return NULL; + + comment =3D strchr(insn, comment_char); + if (comment !=3D NULL) + end =3D comment; + else + end =3D insn + strlen(insn); + + while (end > insn && isspace(end[-1])) + --end; + + len =3D end - insn; + result =3D malloc(len + 1); + if (result =3D=3D NULL) + return NULL; + + memcpy(result, insn, len); + result[len] =3D '\0'; + + return result; +} + +static int arm64_mov__parse(const struct arch *arch, struct ins_operands *ops, struct map_symbol *ms __maybe_unused, struct disasm_line *dl __maybe_unused) { - char *s =3D strchr(ops->raw, ','), *target, *endptr; + char *s =3D strchr(ops->raw, ','), *source, *endptr; =20 if (s =3D=3D NULL) return -1; =20 + /* Parse target */ *s =3D '\0'; - ops->source.raw =3D strdup(ops->raw); + ops->target.raw =3D strdup(ops->raw); *s =3D ','; =20 - if (ops->source.raw =3D=3D NULL) - return -1; - - target =3D ++s; - ops->target.raw =3D strdup(target); if (ops->target.raw =3D=3D NULL) - goto out_free_source; + return -1; =20 - ops->target.addr =3D strtoull(target, &endptr, 16); - if (endptr =3D=3D target) - goto out_free_target; + ops->target.multi_regs =3D arm64__check_multi_regs(arch, ops->target.raw); =20 - s =3D strchr(endptr, '<'); - if (s =3D=3D NULL) - goto out_free_target; - endptr =3D strchr(s + 1, '>'); - if (endptr =3D=3D NULL) - goto out_free_target; - - *endptr =3D '\0'; - *s =3D ' '; - ops->target.name =3D strdup(s); - *s =3D '<'; - *endptr =3D '>'; - if (ops->target.name =3D=3D NULL) - goto out_free_target; + /* Parse source, stripping comment if present */ + source =3D skip_spaces(++s); + ops->source.raw =3D rstrip_space_and_comment(source, arch->objdump.commen= t_char); + if (ops->source.raw =3D=3D NULL) { + zfree(&ops->target.raw); + return -1; + } + + ops->source.multi_regs =3D arm64__check_multi_regs(arch, ops->source.raw); + + /* + * Parse 'addr ' from source (if any). + * + * A raw hex string may be a scalar immediate, not an address. + * Only validate 'source.addr' if accompanied by a '' tag, + * otherwise reset it to 0 to avoid false positive address tracking. + */ + ops->source.addr =3D strtoull(ops->source.raw, &endptr, 16); + if (endptr !=3D ops->source.raw) { + s =3D strchr(endptr, '<'); + if (s =3D=3D NULL) { + ops->source.addr =3D 0; + return 0; + } + endptr =3D strrchr(s + 1, '>'); + if (endptr =3D=3D NULL) { + ops->source.addr =3D 0; + return 0; + } + + *endptr =3D '\0'; + ops->source.name =3D strdup(s + 1); + *endptr =3D '>'; + if (ops->source.name =3D=3D NULL) { + ops->source.addr =3D 0; + return 0; + } + } =20 return 0; +} =20 -out_free_target: - zfree(&ops->target.raw); -out_free_source: - zfree(&ops->source.raw); - return -1; +static int arm64_mov__scnprintf(const struct ins *ins, char *bf, size_t si= ze, + struct ins_operands *ops, int max_ins_name) +{ + return scnprintf(bf, size, "%-*s %s, %s", max_ins_name, ins->name, + ops->target.raw, ops->source.name ?: ops->source.raw); } =20 static const struct ins_ops arm64_mov_ops =3D { .parse =3D arm64_mov__parse, - .scnprintf =3D mov__scnprintf, + .scnprintf =3D arm64_mov__scnprintf, }; =20 static const struct ins_ops *arm64__associate_instruction_ops(struct arch = *arch, const char *name) @@ -103,6 +204,7 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->id =3D *id; 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Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 04/26] perf annotate-arm64: Handle load and store instructions Date: Tue, 8 Sep 2026 13:05:07 +0000 Message-Id: <37f13e322f75aa96f9cb8b71f401c9911523f8c5.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S6 X-Coremail-Antispam: 1UD129KBjvJXoW3XF4rXr15Xr4xurW5Gry7GFg_yoWxXrWfpa 92k345tr42qr4rW3WftF4kZ34fGa18Ja4a9ry8Jwn3Ca1avryxtFn5Kr12kFs8Grykur43 XFn0vry0vF98A3DanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Add ldst_ops to handle load and store instructions in order to parse the data types and offsets associated with PMU events for memory access instructions. There are many variants of load and store instructions in arm64, making it difficult to match all of these instruction names completely. Therefore, only the instruction prefixes are matched. The prefix 'ld|st' covers most of the memory access instructions, 'cas|swp' matches atomic instructions, and 'prf' matches memory prefetch instructions. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu Reviewed-by: Namhyung Kim --- .../perf/util/annotate-arch/annotate-arm64.c | 140 ++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 151184210691..a7595a954cfa 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -14,6 +14,7 @@ struct arch_arm64 { struct arch arch; regex_t call_insn; regex_t jump_insn; + regex_t ldst_insn; /* load and store instruction */ }; =20 static bool arm64__is_reg(const char *op) @@ -170,6 +171,130 @@ static const struct ins_ops arm64_mov_ops =3D { .scnprintf =3D arm64_mov__scnprintf, }; =20 +static bool arm64__insn_is_target_on_right(const char *ins_name) +{ + /* + * Store instructions write to the memory operand on the right, + * unlike standard syntax where the target is the left operand. + */ + return !strncmp(ins_name, "st", 2); +} + +/* + * This function is used to parse arm64 load/store instructions into + * instruction operands. + * + * Typical instructions and their parsing logic: + * + * 1. Immediate offset: + * ldr x2, [x0] -> target=3D"x2", source=3D"[x0]" + * ldr x2, [x0, #24] -> target=3D"x2", source=3D"[x0, #24]" + * ldp x19, x20, [sp, #16] -> target=3D"x19, x20", source=3D"[sp,= #16]" + * + * 2. Pre-index addressing: + * stp x29, x30, [sp, #-64]! -> target=3D"[sp, #-64]!", source=3D"x= 29, x30" + * + * 3. Post-index addressing: + * str x1, [x0], #8 -> target=3D"[x0], #8", source=3D"x1" + * ldr w1, [x21], #4 -> target=3D"w1", source=3D"[x21], #4" + * ldp x29, x30, [sp], #32 -> target=3D"x29, x30", source=3D"[sp]= , #32" + * + * 4. Register offset / extension: + * ldr x0, [x1, w0, sxtw #3] -> target=3D"x0", source=3D"[x1, w0, s= xtw #3]" + * ldr x0, [x1, x0, lsl #3] -> target=3D"x0", source=3D"[x1, x0, l= sl #3]" + * + * 5. Atomic operations: + * cas w3, w1, [x0] -> target=3D"w3, w1", source=3D"[x0]" + * swp x3, x0, [x2] -> target=3D"x3, x0", source=3D"[x2]" + * + * 6. Prefetch memory: + * prfm pstl1strm, [x4] -> target=3D"pstl1strm", source=3D"[x4= ]" + * + * 7. PC-relative loads (No bracket found): + * ldr x0, ffff800080f40c68 <__kvm_nvhe_$d> -> Fallback to default p= arser + * + * Parsing strategy: + * Use the '[' bracket as the boundary to split the operands into left + * and right sides. For non-store instructions, the left side is the + * target and the right side is the source. For store instructions, the + * roles are reversed. + */ +static int arm64_ldst__parse(const struct arch *arch, struct ins_operands = *ops, + struct map_symbol *ms, struct disasm_line *dl) +{ + char *raw, *s, *left, *right; + int ret =3D -1; + + raw =3D rstrip_space_and_comment(ops->raw, arch->objdump.comment_char); + if (!raw) + return -1; + + s =3D strchr(raw, arch->objdump.memory_ref_char); + if (!s) { + /* Fallback to default parser for PC-relative loads. */ + free(raw); + return arm64_mov__parse(arch, ops, ms, dl); + } + + right =3D strdup(s); + if (!right) + goto out_free_raw; + + while (s > raw && *s !=3D ',') + --s; + + if (s =3D=3D raw) + goto out_free_right; + + *s =3D '\0'; + left =3D strdup(raw); + *s =3D ','; + if (!left) + goto out_free_right; + + free(raw); + + if (arm64__insn_is_target_on_right(dl->ins.name)) { + ops->source.raw =3D left; + ops->source.mem_ref =3D false; + + ops->target.raw =3D right; + ops->target.mem_ref =3D true; + } else { + ops->source.raw =3D right; + ops->source.mem_ref =3D true; + + ops->target.raw =3D left; + ops->target.mem_ref =3D false; + } + + ops->source.multi_regs =3D arm64__check_multi_regs(arch, ops->source.raw); + ops->target.multi_regs =3D arm64__check_multi_regs(arch, ops->target.raw); + + return 0; + +out_free_right: + free(right); +out_free_raw: + free(raw); + return ret; +} + +static int arm64_ldst__scnprintf(const struct ins *ins, char *bf, size_t s= ize, + struct ins_operands *ops, int max_ins_name) +{ + if (arm64__insn_is_target_on_right(ins->name)) + return scnprintf(bf, size, "%-*s %s", max_ins_name, ins->name, ops->raw); + + return scnprintf(bf, size, "%-*s %s, %s", max_ins_name, ins->name, + ops->target.raw, ops->source.name ?: ops->source.raw); +} + +static struct ins_ops arm64_ldst_ops =3D { + .parse =3D arm64_ldst__parse, + .scnprintf =3D arm64_ldst__scnprintf, +}; + static const struct ins_ops *arm64__associate_instruction_ops(struct arch = *arch, const char *name) { struct arch_arm64 *arm =3D container_of(arch, struct arch_arm64, arch); @@ -180,6 +305,8 @@ static const struct ins_ops *arm64__associate_instructi= on_ops(struct arch *arch, ops =3D &jump_ops; else if (!regexec(&arm->call_insn, name, 2, match, 0)) ops =3D &call_ops; + else if (!regexec(&arm->ldst_insn, name, 2, match, 0)) + ops =3D &arm64_ldst_ops; else if (!strcmp(name, "ret")) ops =3D &ret_ops; else @@ -205,6 +332,7 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.comment_char =3D '/'; arch->objdump.skip_functions_char =3D '+'; arch->objdump.memory_ref_char =3D '['; + arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; =20 /* bl, blr */ @@ -218,8 +346,20 @@ const struct arch *arch__new_arm64(const struct e_mach= ine_and_e_flags *id, if (err) goto out_free_call; =20 + /* + * The ARM64 architecture has many variants of load/store instructions. + * It is quite challenging to match all of them completely. Here, we + * only match the prefixes of these instructions. + */ + err =3D regcomp(&arm->ldst_insn, "^(ld|st|cas|prf|swp)", + REG_EXTENDED); + if (err) + goto out_free_jump; + return arch; =20 +out_free_jump: + regfree(&arm->jump_insn); out_free_call: regfree(&arm->call_insn); out_free_arm: --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15D79558213; Tue, 8 Sep 2026 13:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872750; cv=none; b=gOpyJKCXa6rzj/UIMr5XX8qedujuMXoiFW2OSqmN1Vk15ira52NcRPfTX0ZgeKdM6EpTNC4gKzyykW+nqrFVh9C5fBubJ7TVQN11vrgs/CtfzQ9WyTPh/R+GmoB3bAFCHAaUzKdJXLrYhMxJHtYwPsiQnv/QtKSm/Y/TFQRYYZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872750; c=relaxed/simple; bh=082KIMFqE+/uvlHTdBvoMV9qFKfen+dk73/eqLUYMKs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SzChI1iuiaUp/OhNMpV2iq0/0xDzpO81Wh8uKlib/6ak0S6zUrRpZGLZeNisB3VEiy17X3vx4HrDezOocnY6y6Dv8KkDO07u+29MocKR44RUt9vUIX00vnVWX7hZ8vmn1nl6VjdGEC9D5c+lsRcNbmDeEcMww4fzbzr+wEIQJhI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hfPLs2bclzKHN6r; Tue, 8 Sep 2026 21:05:41 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id A7DF740590; Tue, 8 Sep 2026 21:05:42 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S7; Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 05/26] perf annotate: Normalize arch__dwarf_regnum() error return values Date: Tue, 8 Sep 2026 13:05:08 +0000 Message-Id: <07d3cce3cb8561c07d7c77deac81eb9ab0540ccb.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S7 X-Coremail-Antispam: 1UD129KBjvdXoWrKw1rAr1kKw4xtFWDCFWkXrb_yoWfuFg_u3 WxtF1Utr18JrZ7tasFkFyrCryxJFy5ZrWxGry7Ga47ZFyfGr17tFWqyrn5G3yrGayUtrnI yw1kXrWxZr429jkaLaAFLSUrUUUU1b8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbpxYFVCjjxCrM7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20E Y4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s 0DM28IrcIa0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26F4UJVW0owA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Wrv_ZF1lc7CjxVAKzI0E Y4vE52x082I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWr XwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVWxJr0_GcWlIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v2 6F4j6r4UJwCI42IY6I8E87Iv6xkF7I0E14v26F4UJVW0obIYCTnIWIevJa73UjIFyTuYvj 4E73dUUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" arch__dwarf_regnum() returns inconsistent error values: early path returns -1 while the main lookup returns -ENOENT/-EINVAL from get_dwarf_regnum(). Callers only check for -1, so genuine failures can slip through. Normalize all failures to -1 to match the callers' expectation. Suggested-by: Shuai Xue Signed-off-by: Tengda Wu Reviewed-by: Ian Rogers Reviewed-by: Namhyung Kim --- tools/perf/util/annotate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index df70e95a8470..f3d17d153b67 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2492,7 +2492,7 @@ static int arch__dwarf_regnum(const struct arch *arch= , const char *str) =20 reg =3D get_dwarf_regnum(regname, arch->id.e_machine, arch->id.e_flags); free(regname); - return reg; + return reg < 0 ? -1 : reg; } =20 /* --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3B765505FC; Tue, 8 Sep 2026 13:05:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872750; cv=none; b=b9azXtYV6cUR7kmd7x4+beFLN8MujvAzZBStztWMPbr6WT4UZJS8XmgzvTg5gegaUD6dEPkeUO7t3ZmcUqC2kQGbfm0wpQX7MuJ9n8M8XpIhtOphKut0C5fzdFRrI6y5PfP7aGozrzaj+mg6GVbYHBma7kaDvceqVe2+ewayMRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872750; c=relaxed/simple; bh=6rKBnKbc8LbbUcnehDkEMcRqihU2QGf4nLMbOmEmLso=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FpGnFvGqUzjIvMwHcdJj8gzgrVDcx+o02JLGzk/VWiBKLbFSAQvKZ37qGIvLNtatpTKttlrax+Q4d/X8HZWPXxqbmV2ANqV3VrH961a5ocq638pZBgNqZADC5Sgkfgzqjppbh1/fDwhzSVCv2JA1Hy2eiTQybAXInnlH3I3iixY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPKv1mrNzYQw0n; Tue, 8 Sep 2026 21:04:51 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id BA5AC40579; Tue, 8 Sep 2026 21:05:42 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S8; Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 06/26] perf annotate: Introduce extract_op_location callback for arch-specific parsing Date: Tue, 8 Sep 2026 13:05:09 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S8 X-Coremail-Antispam: 1UD129KBjvJXoWxtr13tF45uFy8Wr1kuw1xZrb_yoWfKr48pw 4Du34Yyr1rKr4YqwsxXFs5W3Wakw4rWF1Y9r17KwsrAFn2vrn5Jan2gF1ayF1rtrZ5ur1j vF1qqr48XryrGaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Assembly syntax for operands varies significantly across different architectures, which prevents the operand location (op_loc) parsing logic in annotate_get_insn_location() from being directly reused. To simplify the core logic and improve maintainability, move the operand parsing inside the for_each_insn_op_loc loop into arch-specific extract_op_location callbacks. This refactoring is intended to be a cleanup with no functional changes. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu Reviewed-by: Namhyung Kim --- .../util/annotate-arch/annotate-powerpc.c | 9 ++ tools/perf/util/annotate-arch/annotate-x86.c | 79 ++++++++++++++++ tools/perf/util/annotate.c | 94 +------------------ tools/perf/util/annotate.h | 2 + tools/perf/util/disasm.h | 4 + 5 files changed, 99 insertions(+), 89 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-powerpc.c b/tools/perf/= util/annotate-arch/annotate-powerpc.c index 218207b52581..00b93296fc94 100644 --- a/tools/perf/util/annotate-arch/annotate-powerpc.c +++ b/tools/perf/util/annotate-arch/annotate-powerpc.c @@ -390,6 +390,14 @@ static void update_insn_state_powerpc(struct type_stat= e *state, } #endif /* HAVE_LIBDW_SUPPORT */ =20 +static void extract_op_location_powerpc(const struct arch *arch __maybe_un= used, + struct disasm_line *dl, + const char *op_str __maybe_unused, int op_idx, + struct annotated_op_loc *op_loc) +{ + get_powerpc_regs(dl->raw.raw_insn, !op_idx, op_loc); +} + const struct arch *arch__new_powerpc(const struct e_machine_and_e_flags *i= d, const char *cpuid __maybe_unused) { @@ -406,5 +414,6 @@ const struct arch *arch__new_powerpc(const struct e_mac= hine_and_e_flags *id, #ifdef HAVE_LIBDW_SUPPORT arch->update_insn_state =3D update_insn_state_powerpc; #endif + arch->extract_op_location =3D extract_op_location_powerpc; return arch; } diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index 7e6136536393..1acf31a2c759 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include +#include #include #include #include @@ -809,6 +811,82 @@ static void update_insn_state_x86(struct type_state *s= tate, } #endif =20 +/* + * Get register number and access offset from the given instruction. + * It assumes AT&T x86 asm format like OFFSET(REG). + * Fills @reg and @offset when return 0. + */ +static int extract_reg_offset(const struct arch *arch, const char *str, + struct annotated_op_loc *op_loc) +{ + char *p; + + if (arch->objdump.register_char =3D=3D 0) + return -1; + + /* + * It should start from offset, but it's possible to skip 0 + * in the asm. So 0(%rax) should be same as (%rax). + * + * However, it also start with a segment select register like + * %gs:0x18(%rbx). In that case it should skip the part. + */ + if (*str =3D=3D arch->objdump.register_char) { + /* FIXME: Handle other segment registers */ + if (!strncmp(str, "%gs:", 4)) + op_loc->segment =3D INSN_SEG_X86_GS; + + while (*str && !isdigit(*str) && + *str !=3D arch->objdump.memory_ref_char) + str++; + } + + op_loc->offset =3D strtol(str, &p, 0); + op_loc->reg1 =3D arch__dwarf_regnum(arch, p); + if (op_loc->reg1 =3D=3D -1) + return -1; + + /* Get the second register */ + if (op_loc->multi_regs) + op_loc->reg2 =3D arch__dwarf_regnum(arch, p + 1); + + return 0; +} + +static void extract_op_location_x86(const struct arch *arch, + struct disasm_line *dl __maybe_unused, + const char *op_str, int op_idx __maybe_unused, + struct annotated_op_loc *op_loc) +{ + if (op_str =3D=3D NULL) + return; + + if (strchr(op_str, arch->objdump.memory_ref_char)) { + op_loc->mem_ref =3D true; + extract_reg_offset(arch, op_str, op_loc); + } else { + const char *s =3D op_str; + char *p =3D NULL; + + /* FIXME: Handle other segment registers */ + if (!strncmp(op_str, "%gs:", 4)) { + op_loc->segment =3D INSN_SEG_X86_GS; + op_loc->offset =3D strtol(op_str + 4, &p, 0); + if (p && p !=3D op_str + 4) + op_loc->imm =3D true; + return; + } + + if (*s =3D=3D arch->objdump.register_char) { + op_loc->reg1 =3D arch__dwarf_regnum(arch, s); + } else if (*s =3D=3D arch->objdump.imm_char) { + op_loc->offset =3D strtol(s + 1, &p, 0); + if (p && p !=3D s + 1) + op_loc->imm =3D true; + } + } +} + const struct arch *arch__new_x86(const struct e_machine_and_e_flags *id, c= onst char *cpuid) { struct arch *arch =3D zalloc(sizeof(*arch)); @@ -848,5 +926,6 @@ const struct arch *arch__new_x86(const struct e_machine= _and_e_flags *id, const c #ifdef HAVE_LIBDW_SUPPORT arch->update_insn_state =3D update_insn_state_x86; #endif + arch->extract_op_location =3D extract_op_location_x86; return arch; } diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index f3d17d153b67..a3d48cf88dad 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2472,7 +2472,7 @@ int annotate_check_args(void) return 0; } =20 -static int arch__dwarf_regnum(const struct arch *arch, const char *str) +int arch__dwarf_regnum(const struct arch *arch, const char *str) { const char *p; char *regname, *q; @@ -2495,51 +2495,6 @@ static int arch__dwarf_regnum(const struct arch *arc= h, const char *str) return reg < 0 ? -1 : reg; } =20 -/* - * Get register number and access offset from the given instruction. - * It assumes AT&T x86 asm format like OFFSET(REG). Maybe it needs - * to revisit the format when it handles different architecture. - * Fills @reg and @offset when return 0. - */ -static int extract_reg_offset(const struct arch *arch, const char *str, - struct annotated_op_loc *op_loc) -{ - char *p; - - if (arch->objdump.register_char =3D=3D 0) - return -1; - - /* - * It should start from offset, but it's possible to skip 0 - * in the asm. So 0(%rax) should be same as (%rax). - * - * However, it also start with a segment select register like - * %gs:0x18(%rbx). In that case it should skip the part. - */ - if (*str =3D=3D arch->objdump.register_char) { - if (arch__is_x86(arch)) { - /* FIXME: Handle other segment registers */ - if (!strncmp(str, "%gs:", 4)) - op_loc->segment =3D INSN_SEG_X86_GS; - } - - while (*str && !isdigit(*str) && - *str !=3D arch->objdump.memory_ref_char) - str++; - } - - op_loc->offset =3D strtol(str, &p, 0); - op_loc->reg1 =3D arch__dwarf_regnum(arch, p); - if (op_loc->reg1 =3D=3D -1) - return -1; - - /* Get the second register */ - if (op_loc->multi_regs) - op_loc->reg2 =3D arch__dwarf_regnum(arch, p + 1); - - return 0; -} - /** * annotate_get_insn_location - Get location of instruction * @arch: the architecture info @@ -2595,50 +2550,11 @@ int annotate_get_insn_location(const struct arch *a= rch, struct disasm_line *dl, /* Invalidate the register by default */ op_loc->reg1 =3D -1; op_loc->reg2 =3D -1; + op_loc->mem_ref =3D mem_ref; + op_loc->multi_regs =3D multi_regs; =20 - if (insn_str =3D=3D NULL) { - if (!arch__is_powerpc(arch)) - continue; - } - - /* - * For powerpc, call get_powerpc_regs function which extracts the - * required fields for op_loc, ie reg1, reg2, offset from the - * raw instruction. - */ - if (arch__is_powerpc(arch)) { - op_loc->mem_ref =3D mem_ref; - op_loc->multi_regs =3D multi_regs; - get_powerpc_regs(dl->raw.raw_insn, !i, op_loc); - } else if (strchr(insn_str, arch->objdump.memory_ref_char)) { - op_loc->mem_ref =3D true; - op_loc->multi_regs =3D multi_regs; - extract_reg_offset(arch, insn_str, op_loc); - } else { - const char *s =3D insn_str; - char *p =3D NULL; - - if (arch__is_x86(arch)) { - /* FIXME: Handle other segment registers */ - if (!strncmp(insn_str, "%gs:", 4)) { - op_loc->segment =3D INSN_SEG_X86_GS; - op_loc->offset =3D strtol(insn_str + 4, - &p, 0); - if (p && p !=3D insn_str + 4) - op_loc->imm =3D true; - continue; - } - } - - if (*s =3D=3D arch->objdump.register_char) { - op_loc->reg1 =3D arch__dwarf_regnum(arch, s); - } - else if (*s =3D=3D arch->objdump.imm_char) { - op_loc->offset =3D strtol(s + 1, &p, 0); - if (p && p !=3D s + 1) - op_loc->imm =3D true; - } - } + if (arch->extract_op_location) + arch->extract_op_location(arch, dl, insn_str, i, op_loc); } =20 return 0; diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index fa08d09b80f7..11b6e4780c02 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -492,6 +492,8 @@ int annotate_parse_percent_type(const struct option *op= t, const char *_str, =20 int annotate_check_args(void); =20 +int arch__dwarf_regnum(const struct arch *arch, const char *str); + /** * struct annotated_op_loc - Location info of instruction operand * @reg1: First register in the operand diff --git a/tools/perf/util/disasm.h b/tools/perf/util/disasm.h index 06c664fd4fc2..62c2949c4c30 100644 --- a/tools/perf/util/disasm.h +++ b/tools/perf/util/disasm.h @@ -16,6 +16,7 @@ struct symbol; struct data_loc_info; struct type_state; struct disasm_line; +struct annotated_op_loc; =20 struct e_machine_and_e_flags { uint32_t e_flags; @@ -49,6 +50,9 @@ struct arch { struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl); 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Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 07/26] perf dwarf-regs: Adapt get_dwarf_regnum() for arm64 Date: Tue, 8 Sep 2026 13:05:10 +0000 Message-Id: <61714d93cd55cd461d5c37146713ddb9e1d04743.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S9 X-Coremail-Antispam: 1UD129KBjvJXoWxAFyxGrW7tFy3Xw1UCry7trb_yoW5Cw48pF srC347Jw4UW3WakwnxAF1fWF1rJw48Zr1FyrW0yw47CrsruF1UZw1fKr1j9F45X3yDJw10 kayDKr18Gr4rJF7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The current arm64 DWARF register lookup relies on 'aarch64_regstr_tbl', a static string table. While this works for kprobe-tracer where register names start with '%', it is insufficient for parsing register numbers directly from raw instructions (e.g., extracting '6' from 'x6' or 'w6') during annotation. Since get_dwarf_regnum() is currently used only by 'perf annotate' and does not affect kprobe-tracer, replace the limited table-based lookup with a programmatic implementation in __get_dwarf_regnum_arm64(). This allows resolving arm64 register names (x0-x30, w0-w30, sp, etc.) directly into their corresponding DWARF register numbers. Signed-off-by: Tengda Wu --- .../util/dwarf-regs-arch/dwarf-regs-arm64.c | 22 +++++++++++++++++++ tools/perf/util/dwarf-regs.c | 2 +- tools/perf/util/include/dwarf-regs.h | 1 + 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c b/tools/per= f/util/dwarf-regs-arch/dwarf-regs-arm64.c index 593ca7d4fccc..720c863d1869 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include +#include +#include #include #include "../../../arch/arm64/include/uapi/asm/perf_regs.h" =20 @@ -10,3 +13,22 @@ int __get_dwarf_regnum_for_perf_regnum_arm64(int perf_re= gnum) =20 return perf_regnum; } + +int __get_dwarf_regnum_arm64(const char *name) +{ + int reg; + + if (!strcmp(name, "sp")) + return 31; + + if (*name !=3D 'x' && *name !=3D 'w') + return -ENOENT; + + name++; + if (!isdigit(*name)) + return -ENOENT; + + reg =3D strtol(name, NULL, 10); + + return reg >=3D 0 && reg <=3D 30 ? reg : -ENOENT; +} diff --git a/tools/perf/util/dwarf-regs.c b/tools/perf/util/dwarf-regs.c index 797f455eba0d..bacf5c13c3bc 100644 --- a/tools/perf/util/dwarf-regs.c +++ b/tools/perf/util/dwarf-regs.c @@ -114,7 +114,7 @@ int get_dwarf_regnum(const char *name, unsigned int mac= hine, unsigned int flags) reg =3D _get_dwarf_regnum(arm_regstr_tbl, name); break; case EM_AARCH64: - reg =3D _get_dwarf_regnum(aarch64_regstr_tbl, name); + reg =3D __get_dwarf_regnum_arm64(name); break; case EM_CSKY: reg =3D __get_csky_regnum(name, flags); diff --git a/tools/perf/util/include/dwarf-regs.h b/tools/perf/util/include= /dwarf-regs.h index 46a764cf322f..a25f038bbff2 100644 --- a/tools/perf/util/include/dwarf-regs.h +++ b/tools/perf/util/include/dwarf-regs.h @@ -105,6 +105,7 @@ int __get_dwarf_regnum_x86_64(const char *name); int __get_dwarf_regnum_for_perf_regnum_i386(int perf_regnum); int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum); =20 +int __get_dwarf_regnum_arm64(const char *name); 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Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 08/26] perf annotate: Adapt arch__dwarf_regnum() for arm64 Date: Tue, 8 Sep 2026 13:05:11 +0000 Message-Id: <723d0c1e1261cb5b38af7ed4fda9d26ae2986319.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S10 X-Coremail-Antispam: 1UD129KBjvJXoW7ury3uw48Cr47ZF1DGF1Utrb_yoW8Cr1rpw srC343Jr10kr40qw4fXFs3WFW3Gw1fA3W5urWktwn7Can3WFyfJa1SyF1F9a17Ars7Aw1Y yF4qqw48WFnxAaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Currently, arch__dwarf_regnum() assumes that all architectures use a register prefix character (e.g., '%' for x86) defined by arch->objdump.register_char, and uses it to match register names in objdump output. However, this assumption does not hold for arm64, where assembly syntax uses bare register names like 'x0', 'w1' without any prefix. As a result, arm64 builds may fail to correctly recognize register names from objdump disassembly, leading to incomplete or incorrect annotation output. To address this: - Make the register prefix check optional, allowing architectures without a prefix character to be parsed correctly. - Extend the delimiter set in strpbrk() to include the closing square bracket ']'. In arm64 assembly, memory operands often use bracketed syntax such as '[x1, #16]' or '[x2]'. Adding ']' ensures clean extraction of register names like 'x2' without trailing characters. Signed-off-by: Tengda Wu Reviewed-by: Namhyung Kim --- tools/perf/util/annotate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index a3d48cf88dad..710a67980cea 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2474,19 +2474,21 @@ int annotate_check_args(void) =20 int arch__dwarf_regnum(const struct arch *arch, const char *str) { - const char *p; + const char *p =3D str; char *regname, *q; int reg; =20 - p =3D strchr(str, arch->objdump.register_char); - if (p =3D=3D NULL) - return -1; + if (arch->objdump.register_char) { + p =3D strchr(str, arch->objdump.register_char); + if (p =3D=3D NULL) + return -1; + } =20 regname =3D strdup(p); if (regname =3D=3D NULL) return -1; =20 - q =3D strpbrk(regname, ",) "); + q =3D strpbrk(regname, ",)] "); if (q) *q =3D '\0'; =20 --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6446D5476F8; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPKv3zy1zYQw1m; Tue, 8 Sep 2026 21:04:51 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 108054057E; Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S11; Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 09/26] perf annotate-arm64: Implement extract_op_location() callback Date: Tue, 8 Sep 2026 13:05:12 +0000 Message-Id: <73c9999d6089cd754ec5df65d1cca97ce3797b8d.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S11 X-Coremail-Antispam: 1UD129KBjvJXoWxKF1kXw1kCrWfAFyUKw45Jrb_yoW3Cry7pr 4Uu34rtr1UJwsIqw4Svrs8Wr15Cw4Ika4qgrW3CwnIyFsavFyfW3Wxta4a9FyrJrZxX3yj yrsYvr48Xr17GaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Implement the extract_op_location() callback for the arm64 architecture to handle its specific assembly syntax and addressing modes. The extractor handles: 1. Immediate operands (e.g., '#0x10' or '#0xc600, lsl #16'). 2. Memory references with diverse addressing modes: - Signed offset: [base{, #imm|reg}] - Pre-index: [base, #imm]! - Post-index: [base], #imm|reg 3. Multi-register operands and primary/secondary register extraction. 4. Register extension specifiers (e.g., uxtw, sxtx) and shift amounts for shifted/extended operands. With this callback in place, 'perf annotate' can now resolve memory locations and register types on arm64, marking the initial enablement of data type profiling for this architecture. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 127 ++++++++++++++++++ tools/perf/util/annotate.h | 61 +++++++++ 2 files changed, 188 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index a7595a954cfa..d8a5904359b1 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -316,6 +316,132 @@ static const struct ins_ops *arm64__associate_instruc= tion_ops(struct arch *arch, return ops; } =20 +static enum annotated_ext_type arm64__check_ext_type(const char *op) +{ + if (!strncmp(op, "uxtb", 4)) return PERF_EXT_UXTB; + if (!strncmp(op, "uxth", 4)) return PERF_EXT_UXTH; + if (!strncmp(op, "uxtw", 4)) return PERF_EXT_UXTW; + if (!strncmp(op, "uxtx", 4)) return PERF_EXT_UXTX; + if (!strncmp(op, "sxtb", 4)) return PERF_EXT_SXTB; + if (!strncmp(op, "sxth", 4)) return PERF_EXT_SXTH; + if (!strncmp(op, "sxtw", 4)) return PERF_EXT_SXTW; + if (!strncmp(op, "sxtx", 4)) return PERF_EXT_SXTX; + + return PERF_EXT_NONE; +} + +static enum annotated_shift_type arm64__check_shift_type(const char *op) +{ + if (!strncmp(op, "lsl", 3)) return PERF_SHIFT_LSL; + if (!strncmp(op, "lsr", 3)) return PERF_SHIFT_LSR; + if (!strncmp(op, "asr", 3)) return PERF_SHIFT_ASR; + if (!strncmp(op, "ror", 3)) return PERF_SHIFT_ROR; + + return PERF_SHIFT_NONE; +} + +static void extract_op_location_arm64(const struct arch *arch, + struct disasm_line *dl __maybe_unused, + const char *op_str, int op_idx __maybe_unused, + struct annotated_op_loc *op_loc) +{ + const char *s =3D op_str; + char *p =3D NULL; + + if (op_str =3D=3D NULL) + return; + + /* + * Handle immediate operand. + * e.g., "#0xc600" -> offset =3D 0xc600, imm =3D true + * + * After parsing, check for post-modifiers like "lsl #16", which + * typically occur in instructions such as movk, movz, movn, etc. + */ + if (*s =3D=3D arch->objdump.imm_char) { + op_loc->offset =3D strtol(s + 1, &p, 0); + if (p && p !=3D s + 1) { + op_loc->imm =3D true; + s =3D p; + } + goto check_modifiers; + } + + /* + * Handle memory references, identify arm64 specific addressing modes. + * Reference: Arm Architecture Reference Manual + * (DDI 0487), Chapter C1.3.3: Load/store addressing modes. + */ + if (*s =3D=3D arch->objdump.memory_ref_char) { + op_loc->mem_ref =3D true; + + p =3D strchr(s, ']'); + if (p =3D=3D NULL) + return; + + /* Pre-index: [base, #imm]! */ + if (p[1] =3D=3D '!') + op_loc->addr_mode =3D PERF_AAM_PRE_INDEX; + /* Post-index: [base], #imm|reg */ + else if (p[1] =3D=3D ',' && + (strchr(p + 1, arch->objdump.imm_char) || + arm64__is_reg(skip_spaces(p + 2)))) + op_loc->addr_mode =3D PERF_AAM_POST_INDEX; + /* Signed offset: [base{, #imm|reg}] */ + else + op_loc->addr_mode =3D PERF_AAM_SIGNED_OFFSET; + + s++; + } + + /* Extract the primary register */ + op_loc->reg1 =3D arch__dwarf_regnum(arch, s); + if (op_loc->reg1 =3D=3D -1) + return; + + /* Move to the next operand field, if present */ + s =3D strchr(s, ','); + if (s =3D=3D NULL) + return; + s =3D skip_spaces(s + 1); + + /* Extract secondary register or immediate offset */ + if (op_loc->multi_regs) + op_loc->reg2 =3D arch__dwarf_regnum(arch, s); + else if (*s =3D=3D arch->objdump.imm_char) + op_loc->offset =3D strtol(s + 1, NULL, 0); + +check_modifiers: + /* + * Look for a following shift or extension modifier: + * ", lsl #3" -> extend_type =3D PERF_EXT_NONE, + * shift_type =3D PERF_SHIFT_LSL, amount =3D 3 + * ", uxtw #3" -> extend_type =3D PERF_EXT_UXTW, + * shift_type =3D PERF_SHIFT_LSL, amount =3D 3 + * ", uxtw" -> extend_type =3D PERF_EXT_UXTW, + * shift_type =3D PERF_SHIFT_LSL, amount =3D 0 + */ + s =3D strchr(s, ','); + if (s =3D=3D NULL) + return; + s =3D skip_spaces(s + 1); + + op_loc->extend_type =3D arm64__check_ext_type(s); + op_loc->shift_type =3D arm64__check_shift_type(s); + /* ARM64 extended operands are implicitly shifted by LSL. */ + if (op_loc->extend_type !=3D PERF_EXT_NONE) + op_loc->shift_type =3D PERF_SHIFT_LSL; + + /* Parse shift amount if present */ + op_loc->amount =3D 0; + if (op_loc->extend_type !=3D PERF_EXT_NONE || + op_loc->shift_type !=3D PERF_SHIFT_NONE) { + s =3D strchr(s, arch->objdump.imm_char); + if (s) + op_loc->amount =3D (u8)strtol(s + 1, NULL, 0); + } +} + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -334,6 +460,7 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.memory_ref_char =3D '['; arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; + arch->extract_op_location =3D extract_op_location_arm64; =20 /* bl, blr */ err =3D regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 11b6e4780c02..f0ff4b7e8a28 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -500,6 +500,10 @@ int arch__dwarf_regnum(const struct arch *arch, const = char *str); * @reg2: Second register in the operand * @offset: Memory access offset in the operand * @segment: Segment selector register + * @addr_mode: Addressing mode, only valid if @mem_ref is true + * @extend_type: Operand extension type (enum annotated_ext_type) + * @shift_type: Operand shift type (enum annotated_shift_type) + * @amount: Number of bits to shift * @mem_ref: Whether the operand accesses memory * @multi_regs: Whether the second register is used * @imm: Whether the operand is an immediate value (in offset) @@ -509,6 +513,10 @@ struct annotated_op_loc { int reg2; int offset; u8 segment; + u8 addr_mode; + u8 extend_type; + u8 shift_type; + u8 amount; bool mem_ref; bool multi_regs; bool imm; @@ -532,6 +540,59 @@ enum annotated_x86_segment { INSN_SEG_X86_SS, }; =20 +/* + * ARM64 addressing modes for memory operations. + * + * [Xn, #imm] -> SIGNED_OFFSET (base + offset, base unchanged) + * [Xn, #imm]! -> PRE_INDEX (base +=3D offset, then access) + * [Xn], #imm -> POST_INDEX (access, then base +=3D offset) + */ +enum annotated_addr_mode { + PERF_AAM_NONE =3D 0, + + PERF_AAM_SIGNED_OFFSET, + PERF_AAM_PRE_INDEX, + PERF_AAM_POST_INDEX, +}; + +/* + * ARM64 register extension types. + * UXT* =3D zero-extend, SXT* =3D sign-extend. + * B=3D8bit, H=3D16bit, W=3D32bit, X=3D64bit. + * + * Example: UXTW =3D zero-extend 32-bit Wn to 64-bit Xn + */ +enum annotated_ext_type { + PERF_EXT_NONE =3D 0, + + PERF_EXT_UXTB, + PERF_EXT_UXTH, + PERF_EXT_UXTW, + PERF_EXT_UXTX, + PERF_EXT_SXTB, + PERF_EXT_SXTH, + PERF_EXT_SXTW, + PERF_EXT_SXTX, +}; + +/* + * ARM64 operand shift types. + * LSL =3D logical shift left. + * LSR =3D logical shift right. + * ASR =3D arithmetic shift right. + * ROR =3D rotate right. + * + * Example: LSL #3 =3D shift the operand left by 3 bits. + */ +enum annotated_shift_type { + PERF_SHIFT_NONE =3D 0, + + PERF_SHIFT_LSL, + PERF_SHIFT_LSR, + PERF_SHIFT_ASR, + PERF_SHIFT_ROR, +}; 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Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 10/26] perf annotate: Default to --itrace=i1i for data type profiling Date: Tue, 8 Sep 2026 13:05:13 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S12 X-Coremail-Antispam: 1UD129KBjvJXoW3JFy5ZrykXF4kZw1kXr4Utwb_yoW3Zrykpr nxCr9rKwnxXr4rKwnIyF4UZF1Yk34rXFyY9r1YkF4rA3yxur9rtFyxtr15tFW3Xw1DC3sI vws09wn8Za1rZaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" ARM SPE-based sampling can synthesize multiple events on a single instruction, as shown below. This would affect data type profiling statistics: Available samples 0 arm_spe_0/ts_enable=3D1,pa_enable=3D1,load_filter=3D1,store_filter=3D1,= min_latency=3D30/ 0 dummy:u 84K l1d-miss 95K l1d-access 77K llc-miss 58K llc-access 9K tlb-miss 108K tlb-access 0 branch 13K remote-access 108K memory 108K instructions While 'perf report' provides an interactive menu for users to select a specific event to prevent duplicate counting, 'perf annotate' lacks such a mechanism. Consequently, it counts all instructions across these overlapping events, which inflates the profile and distorts the data type statistics. Although using the '--itrace' option can work around this issue (e.g.: perf annotate --data-type --stdio --itrace=3Di1i), it is inconvenient for users to specify this explicitly every time. To address this, introduce itrace_synth_opts.default_single_event_per_ip. Set this field to true when data type profiling is enabled and the user has not explicitly specified an itrace option. In itrace_synth_opts__set_de= fault(), use this flag to default to synthesizing at most one event per IP (equivale= nt to --itrace=3Di1i) to prevent duplicate sample counts. Signed-off-by: Tengda Wu Reviewed-by: Adrian Hunter --- tools/perf/builtin-annotate.c | 8 ++++++++ tools/perf/util/arm-spe.c | 5 ++++- tools/perf/util/auxtrace.c | 12 ++++++++++-- tools/perf/util/auxtrace.h | 7 ++++++- tools/perf/util/cs-etm.c | 2 +- tools/perf/util/intel-bts.c | 2 +- tools/perf/util/intel-pt.c | 3 ++- 7 files changed, 32 insertions(+), 7 deletions(-) diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 69cb72b2082a..d5b66893c47c 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -873,6 +873,14 @@ int cmd_annotate(int argc, const char **argv) annotate.session =3D perf_session__new(&data, &annotate.tool); if (IS_ERR(annotate.session)) return PTR_ERR(annotate.session); + /* + * Hardware tracing (e.g., ARM SPE) may synthesize multiple events per + * instruction. When data type profiling is enabled, default to synthesiz= ing + * at most one event (equivalent to --itrace=3Di1i) to prevent skewed + * statistics. + */ + if (annotate.data_type && !itrace_synth_opts.set) + itrace_synth_opts.default_single_event_per_ip =3D true; =20 annotate.session->itrace_synth_opts =3D &itrace_synth_opts; =20 diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 401aab529309..ae7a5e9c3892 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -2029,7 +2029,10 @@ int arm_spe_process_auxtrace_info(union perf_event *= event, if (session->itrace_synth_opts && session->itrace_synth_opts->set) { spe->synth_opts =3D *session->itrace_synth_opts; } else { - itrace_synth_opts__set_default(&spe->synth_opts, false); + struct itrace_synth_opts *opts =3D session->itrace_synth_opts; + bool single_event_per_ip =3D opts ? opts->default_single_event_per_ip : = false; + + itrace_synth_opts__set_default(&spe->synth_opts, false, single_event_per= _ip); /* Default nanoseconds period not supported */ spe->synth_opts.period_type =3D PERF_ITRACE_PERIOD_INSTRUCTIONS; spe->synth_opts.period =3D 1; diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index aa749e1c3036..ed2113190785 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -1478,8 +1478,15 @@ s64 perf_event__process_auxtrace(const struct perf_t= ool *tool __maybe_unused, #define PERF_ITRACE_MAX_LAST_BRANCH_SZ 1024 =20 void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, - bool no_sample) + bool no_sample, bool single_event_per_ip) { + if (single_event_per_ip) { + synth_opts->instructions =3D true; + synth_opts->period_type =3D PERF_ITRACE_PERIOD_INSTRUCTIONS; + synth_opts->period =3D 1; + return; + } + synth_opts->branches =3D true; synth_opts->transactions =3D true; synth_opts->ptwrites =3D true; @@ -1582,7 +1589,8 @@ int itrace_do_parse_synth_opts(struct itrace_synth_op= ts *synth_opts, =20 if (!str) { itrace_synth_opts__set_default(synth_opts, - synth_opts->default_no_sample); + synth_opts->default_no_sample, + synth_opts->default_single_event_per_ip); return 0; } =20 diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index 6947f3f284c0..5012bead1b92 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -65,6 +65,10 @@ enum itrace_period_type { * struct itrace_synth_opts - AUX area tracing synthesis options. * @set: indicates whether or not options have been set * @default_no_sample: Default to no sampling. + * @default_single_event_per_ip: Default to synthesizing at most 1 event p= er IP + * (equivalent to --itrace=3Di1i). Used by c= ommands + * like 'perf annotate --data-type' to avoid= duplicate + * sample counts for a single instruction. * @inject: indicates the event (not just the sample) must be fully synthe= sized * because 'perf inject' will write it out * @instructions: whether to synthesize 'instructions' events @@ -117,6 +121,7 @@ enum itrace_period_type { struct itrace_synth_opts { bool set; bool default_no_sample; + bool default_single_event_per_ip; bool inject; bool instructions; bool cycles; @@ -622,7 +627,7 @@ int itrace_do_parse_synth_opts(struct itrace_synth_opts= *synth_opts, int itrace_parse_synth_opts(const struct option *opt, const char *str, int unset); void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, - bool no_sample); + bool no_sample, bool single_event_per_ip); =20 size_t perf_event__fprintf_auxtrace_error(union perf_event *event, FILE *f= p); void perf_session__auxtrace_error_inc(struct perf_session *session, diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 114b3cd2da49..2d1ab34f7b6b 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -3626,7 +3626,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, etm->synth_opts =3D *session->itrace_synth_opts; } else { itrace_synth_opts__set_default(&etm->synth_opts, - session->itrace_synth_opts->default_no_sample); + session->itrace_synth_opts->default_no_sample, false); etm->synth_opts.callchain =3D false; etm->synth_opts.thread_stack =3D session->itrace_synth_opts->thread_stac= k; } diff --git a/tools/perf/util/intel-bts.c b/tools/perf/util/intel-bts.c index 02df3e460489..4c9cca3acb6c 100644 --- a/tools/perf/util/intel-bts.c +++ b/tools/perf/util/intel-bts.c @@ -877,7 +877,7 @@ int intel_bts_process_auxtrace_info(union perf_event *e= vent, bts->synth_opts =3D *session->itrace_synth_opts; } else { itrace_synth_opts__set_default(&bts->synth_opts, - session->itrace_synth_opts->default_no_sample); + session->itrace_synth_opts->default_no_sample, false); bts->synth_opts.thread_stack =3D session->itrace_synth_opts->thread_stack; } diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 9d6628169fd9..8c21c9f52d57 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -4463,7 +4463,8 @@ int intel_pt_process_auxtrace_info(union perf_event *= event, } else { struct itrace_synth_opts *opts =3D session->itrace_synth_opts; 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Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S13; Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 11/26] perf arm-spe: Set default synthesized event period to 1 Date: Tue, 8 Sep 2026 13:05:14 +0000 Message-Id: <59d7bfeddd5ee06561e91876662d40fbf202ac6b.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S13 X-Coremail-Antispam: 1UD129KBjvJXoWxXFy7CFyxXFWkWw1kJryftFb_yoW5uw43pr nFga4ftr1kJry8Kw17Ar4UuFy3tw4FvF1fGF1xGrWUAw1UKry8tr17try5Cr4UWr1Fyr12 qFyqgw1UGr1Utr7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" When using --itrace=3DM for data type profiling on arm64, the 'Percent' values in perf annotate output are all zero: Annotate type: 'struct mmu_gather_batch' in [kernel.kallsyms] (15 samples): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Percent offset size field 0.00 0 0x10 struct mmu_gather_batch { 0.00 0 0x8 struct mmu_gather_batch* next; 0.00 0x8 0x4 unsigned int nr; 0.00 0xc 0x4 unsigned int max; 0.00 0x10 0 struct encoded_page*[] encoded_pag= es; }; However, adding the -n option (show-nr-samples) reveals non-zero sample cou= nts: Annotate type: 'struct mmu_gather_batch' in [kernel.kallsyms] (15 samples): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Samples offset size field 15 0 0x10 struct mmu_gather_batch { 13 0 0x8 struct mmu_gather_batch* next; 2 0x8 0x4 unsigned int nr; 0 0xc 0x4 unsigned int max; 0 0x10 0 struct encoded_page*[] encoded_pag= es; }; The root cause is that when --itrace is used with non-i/y options (e.g., --itrace=3DM), the period remains zero after parsing. During subsequent propagation, the final percentage calculation results in zero: arm_spe_prep_sample() sample->period =3D spe->synth_opts.period; __hists__add_entry() he.stat.period =3D sample->period; annotated_data_type__update_samples() h->period +=3D period; h->addr[offset].period +=3D period; print_annotated_data_value() double percent =3D h->period ? (100.0 * period / h->period) : 0; Fix this by defaulting the period to 1 in the ARM SPE auxtrace info processing path if it is not explicitly specified. This ensures that downstream tool components can correctly accumulate periods and compute event percentages for all synthesized SPE events. With this fix applied, the result is as follows: Annotate type: 'struct mmu_gather_batch' in [kernel.kallsyms] (15 samples): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Percent offset size field 100.00 0 0x10 struct mmu_gather_batch { 86.67 0 0x8 struct mmu_gather_batch* next; 13.33 0x8 0x4 unsigned int nr; 0.00 0xc 0x4 unsigned int max; 0.00 0x10 0 struct encoded_page*[] encoded_pag= es; }; Signed-off-by: Tengda Wu --- tools/perf/util/arm-spe.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index ae7a5e9c3892..7805a1a98a89 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -2043,6 +2043,17 @@ int arm_spe_process_auxtrace_info(union perf_event *= event, err =3D -EINVAL; goto err_free_queues; } + + /* + * When --itrace is used with non-i/y options (e.g., --itrace=3DM), + * the period remains 0 because the parser does not apply a default + * for those paths. However, synthesized SPE events such as memory + * accesses, TLB walks, and cache misses still require a valid + * sample->period to correctly accumulate periods and compute event + * percentages. Set it to 1 to ensure proper accounting. + */ + spe->synth_opts.period =3D spe->synth_opts.period ?: 1; + if (spe->synth_opts.period > 1) ui__warning("Arm SPE has a hardware-based sampling period.\n\n" "--itrace periods > 1i downsample by an interval of n SPE samples r= ather than n instructions.\n"); --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 392BF55931A; Tue, 8 Sep 2026 13:05:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872758; cv=none; b=oMXsdwebrjk/r9z6nwhhJVEDB6zHTqloOhW8avdAojY+4iVnDKRSf+rRhUdgOgfunAKaWC9RCpuG4RR0VczD3rytWmGlGgfCLubQYtRxP00+3XUutdvi8EWR6oyRWh5McffYDm24J98cddqfu80xL9AlqLnO/8zOeqEihqAEsIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872758; c=relaxed/simple; bh=msO7gvzMCmQxp+5FSP1qIEkxjs1eIW94fah/aqxDUBM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mGAzgHgua6x3BoKw7bTAnqC/z0lHIsZTQHQ65fqf/w2To+aM55RIu/XG6yw/raCYx2CnESxL3atrucBJxTCPLGpDujW5m9T1bfBTJI/YjAVB+/GVDAjUI/6ayOGNt8zLvlShyxnNkUkiHogRDLzzpN6D/IaYEjK0mt6F0nD/BmU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPKv5sD2zYQw6x; Tue, 8 Sep 2026 21:04:51 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 5353940578; Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S14; Tue, 08 Sep 2026 21:05:42 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 12/26] perf annotate-data: Extract invalidate_reg_state() as a common helper Date: Tue, 8 Sep 2026 13:05:15 +0000 Message-Id: <62d5646f6a60e40bfa765d9cf93b5d6279b7f8a7.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S14 X-Coremail-Antispam: 1UD129KBjvJXoWxGr1rJry8CF1ktr17Kr4UJwb_yoW5XrW5p3 yDC347Gw43Gr4FgwnxJFW3XFWF9r1fXa4Fk3sYyan2vFWIyrn3JF92qFy5tFW7Xr93Gw12 yw1qgr4DJayxKaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The invalidate_reg_state() function is currently static and only used within the x86 data type profiling implementation. To prepare for adding arm64 instruction tracking support, extract it as a common helper that can be shared across architectures. No functional change intended. Reviewed-by: Shuai Xue Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-x86.c | 9 --------- tools/perf/util/annotate-data.c | 9 +++++++++ tools/perf/util/annotate-data.h | 1 + 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index 1acf31a2c759..aa381d25a63b 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -207,15 +207,6 @@ static int x86__cpuid_parse(struct arch *arch, const c= har *cpuid) } =20 #ifdef HAVE_LIBDW_SUPPORT -static void invalidate_reg_state(struct type_state_reg *reg) -{ - reg->kind =3D TSR_KIND_INVALID; - reg->ok =3D false; - reg->lifetime_active =3D false; - reg->lifetime_end =3D 0; - reg->copied_from =3D -1; -} - static void update_insn_state_x86(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 4e4c58764082..104b80d471f1 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -638,6 +638,15 @@ struct type_state_stack *findnew_stack_state(struct ty= pe_state *state, return stack; } =20 +void invalidate_reg_state(struct type_state_reg *reg) +{ + reg->kind =3D TSR_KIND_INVALID; + reg->ok =3D false; + reg->lifetime_active =3D false; + reg->lifetime_end =3D 0; + reg->copied_from =3D -1; +} + /* Maintain a cache for quick global variable lookup */ struct global_var_entry { struct rb_node node; diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index c26130744260..453e13bbe3e2 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -258,6 +258,7 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, Dwarf_Die *type_die, int ptr_offset); struct type_state_stack *find_stack_state(struct type_state *state, int offset); +void invalidate_reg_state(struct type_state_reg *reg); bool get_global_var_type(Dwarf_Die *cu_die, struct data_loc_info *dloc, u64 ip, u64 var_addr, int *var_offset, Dwarf_Die *type_die); --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 798C955C1A3; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hfPLt0VNMzKHN7x; Tue, 8 Sep 2026 21:05:42 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 665864058D; Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S15; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 13/26] perf annotate-arm64: Enable instruction tracking support Date: Tue, 8 Sep 2026 13:05:16 +0000 Message-Id: <8ff5cfde0aad3d585b34f177fd87e8ec57ba4fa1.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S15 X-Coremail-Antispam: 1UD129KBjvJXoW3WFy7Wr48tF1UAF4rCry8Krg_yoW7Kw17pa yDC345KF4UJr42gwnxJF4UXry3G3yfW34Y9r9Ygw4SyFsFyryrtFs5KFWayF4rGrZ3Cw4Y q3WqyFWDXw4UCaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Enable basic instruction tracking for arm64 by implementing three essential functions in the find_data_type_block() call path: find_data_type_block -> arch_supports_insn_tracking (1) -> find_data_type_insn -> init_type_state (2) -> update_var_state -> update_insn_state (3) Changes: * arch_supports_insn_tracking(): add arm64 to the list of supported architectures, allowing find_data_type_block() to proceed with data type analysis. * init_type_state(): correctly identify ret_reg, stack_reg, and caller-saved registers for arm64 during type state initialization. * update_insn_state(): add the update_insn_state_arm64() callback with conservative register invalidation for call instructions and those with destination register(s), preventing stale type propagation. Full instruction-level analysis support will be added incrementally in later patches. With these changes, arm64 gains support for basic variable type inference during instruction tracking. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 78 +++++++++++++++++++ tools/perf/util/annotate-data.c | 11 ++- 2 files changed, 88 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index d8a5904359b1..8fda4d4d6888 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -9,6 +9,10 @@ #include #include "../annotate.h" #include "../disasm.h" +#include "../annotate-data.h" +#include "../debug.h" +#include "../map.h" +#include "../symbol.h" =20 struct arch_arm64 { struct arch arch; @@ -442,6 +446,77 @@ static void extract_op_location_arm64(const struct arc= h *arch, } } =20 +#ifdef HAVE_LIBDW_SUPPORT +static bool is_readonly_branch_or_cmp(const char *name) +{ + return !strncmp(name, "cb", 2) || !strncmp(name, "tb", 2) || + !strcmp(name, "tst") || !strcmp(name, "teq") || + !strcmp(name, "cmp") || !strcmp(name, "cmn") || + !strcmp(name, "ccmp") || !strcmp(name, "ccmn"); +} + +static void update_insn_state_arm64(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die *cu_die __maybe_unused, + struct disasm_line *dl) +{ + struct annotated_insn_loc loc; + struct annotated_op_loc *dst =3D &loc.ops[INSN_OP_TARGET]; + u32 insn_offset =3D dl->al.offset; + + /* Skip read-only instructions that do not affect register type state */ + if (is_readonly_branch_or_cmp(dl->ins.name)) + return; + + if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) + return; + + /* + * Invalidate caller-saved registers on function calls per ARM64 AAPCS64 + * ABI, unless DWARF location info indicates the register remains valid + * beyond the call address. + */ + if (ins__is_call(&dl->ins)) { + struct symbol *func =3D dl->ops.target.sym; + const char *call_name; + u64 call_addr; + + call_name =3D func ? func->name : dl->ops.target.name; + pr_debug_dtp("call [%x] %s\n", insn_offset, call_name ?: ""); + + /* Invalidate caller-saved registers after call */ + call_addr =3D map__rip_2objdump(dloc->ms->map, + dloc->ms->sym->start + dl->al.offset); + for (unsigned int i =3D 0; i < ARRAY_SIZE(state->regs); i++) { + struct type_state_reg *reg =3D &state->regs[i]; + + if (!reg->caller_saved) + continue; + /* Keep register valid within DWARF location lifetime */ + if (reg->lifetime_active && call_addr < reg->lifetime_end) + continue; + invalidate_reg_state(reg); + } + return; + } + + /* + * Invalidate destination register(s) for unsupported instructions to + * prevent stale type info from propagating to subsequent instructions. + */ + if (has_reg_type(state, dst->reg1) && !dst->mem_ref) { + pr_debug_dtp("%s [%x] invalidate reg%d", + dl->ins.name, insn_offset, dst->reg1); + invalidate_reg_state(&state->regs[dst->reg1]); + if (dst->multi_regs && has_reg_type(state, dst->reg2)) { + pr_debug_dtp(" and reg%d", dst->reg2); + invalidate_reg_state(&state->regs[dst->reg2]); + } + pr_debug_dtp("\n"); + return; + } +} +#endif + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -461,6 +536,9 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; arch->extract_op_location =3D extract_op_location_arm64; +#ifdef HAVE_LIBDW_SUPPORT + arch->update_insn_state =3D update_insn_state_arm64; +#endif =20 /* bl, blr */ err =3D regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 104b80d471f1..c51b20a7af9b 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -28,6 +28,7 @@ =20 /* register number of the stack pointer */ #define X86_REG_SP 7 +#define ARM64_REG_SP 31 =20 static void delete_var_types(struct die_var_type *var_types); =20 @@ -178,6 +179,13 @@ static void init_type_state(struct type_state *state, = const struct arch *arch) state->regs[11].caller_saved =3D true; state->ret_reg =3D 0; state->stack_reg =3D X86_REG_SP; + } else if (arch__is_arm64(arch)) { + int i; + + for (i =3D 0; i < 18; i++) + state->regs[i].caller_saved =3D true; + state->ret_reg =3D 0; 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Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S16; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 14/26] perf annotate-data: Add arch_get_reg_offset helper Date: Tue, 8 Sep 2026 13:05:17 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S16 X-Coremail-Antispam: 1UD129KBjvJXoW3AF1rZryUAryftry5tFyUtrb_yoW3XFyrpa 95GFyrGr43Xr43WrsrXrZ8Xr9Y9wsrGF9xCryq934ayryaqr18Ka1vyryYk3yUJrZYyr17 G3Z8tr47XwsrGaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa 7xRxnoUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Add a helper to compute the effective offset from a base register for instruction operands. Currently handles arm64 addressing modes including post-indexed, single-register, SIB-style indexed with shift/extension, and constant-offset register pairs. Fallback to instruction's raw offset for other architectures. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-data.c | 106 +++++++++++++++++++++++++++----- tools/perf/util/annotate-data.h | 4 +- 2 files changed, 94 insertions(+), 16 deletions(-) diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index c51b20a7af9b..754c0efe2077 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -1118,6 +1118,74 @@ static void setup_stack_canary(struct data_loc_info = *dloc) } } =20 +int arch_get_reg_offset(const struct arch *arch, struct annotated_op_loc *= op_loc, + int breg, struct type_state *state, bool apply_index, + int *offset) +{ + if (arch__is_arm64(arch)) { + int reg2; + + /* Post-indexed addressing: offset is 0 when not applying index */ + if (op_loc->addr_mode =3D=3D PERF_AAM_POST_INDEX && !apply_index) { + *offset =3D 0; + return 0; + } + + /* Single-register addressing: return the stored offset directly */ + if (!op_loc->multi_regs) { + *offset =3D op_loc->offset; + return 0; + } + + /* + * SIB (Scale-Index-Base) style indexed addressing, e.g.: + * Array element load: ldr dst, [base, index, lsl #3] + * Array element load: ldr dst, [base, index, uxtw #3] + * Array address calc: add dst, base, index lsl #3 + * + * The index reg only computes element offset without modifying + * the underlying data type; the dst type is inherited from base. + * Therefore, the base reg offset can be treated as 0. + */ + if (op_loc->extend_type || op_loc->shift_type) { + /* Memory references use the breg as the address base. */ + if (op_loc->mem_ref) { + *offset =3D 0; + return 0; + } + /* + * Otherwise, require breg to be a known pointer type to + * avoid treating integer operations as address calculations. + */ + if (has_reg_type(state, breg) && state->regs[breg].ok && + (state->regs[breg].kind =3D=3D TSR_KIND_POINTER || + (state->regs[breg].kind =3D=3D TSR_KIND_TYPE && + dwarf_tag(&state->regs[breg].type) =3D=3D DW_TAG_pointer_type))) { + *offset =3D 0; + return 0; + } + return -1; + } + + /* + * For register-based addressing without shift/extension, + * reg2 may be a constant offset. Use its value as the offset + * from the base register. + */ + reg2 =3D op_loc->reg1 =3D=3D breg ? op_loc->reg2 : op_loc->reg1; + if (has_reg_type(state, reg2) && state->regs[reg2].ok && + state->regs[reg2].kind =3D=3D TSR_KIND_CONST) { + *offset =3D (s64)state->regs[reg2].imm_value; + return 0; + } + + return -1; + } + + *offset =3D op_loc->offset; + return 0; +} + /* * It's at the target address, check if it has a matching type. * It returns PERF_TMR_BAIL_OUT when it looks up per-cpu variables which @@ -1132,18 +1200,26 @@ static enum type_match_result check_matching_type(s= truct type_state *state, Dwarf_Word size; u32 insn_offset =3D dl->al.offset; int reg =3D dloc->op->reg1; - int offset =3D dloc->op->offset; + int offset; const char *offset_sign =3D ""; bool retry =3D true; =20 - if (offset < 0) { - offset =3D -offset; - offset_sign =3D "-"; +again: + if (arch_get_reg_offset(dloc->arch, dloc->op, reg, state, false, &offset)= ) { + /* + * Fall back to the instruction's offset. This prevents the + * register type of the instruction from being completely lost. + * Compared to dropping this type inference entirely, providing + * a rough type hint is likely more useful. + */ + offset =3D dloc->op->offset; } =20 -again: + if (offset < 0) + offset_sign =3D "-"; + pr_debug_dtp("chk [%x] reg%d offset=3D%s%#x ok=3D%d kind=3D%d ", - insn_offset, reg, offset_sign, offset, + insn_offset, reg, offset_sign, abs(offset), state->regs[reg].ok, state->regs[reg].kind); =20 if (!state->regs[reg].ok) @@ -1166,7 +1242,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, */ ptr_type =3D die_get_pointer_type(&state->regs[reg].type, &ptr_die); if (!ptr_type) { - if (dloc->op->offset < 0 && reg !=3D state->stack_reg) + if (offset < 0 && reg !=3D state->stack_reg) goto check_kernel; =20 return PERF_TMR_NO_POINTER; @@ -1176,7 +1252,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, if (__die_get_real_type(ptr_type, type_die) =3D=3D NULL) return PERF_TMR_NO_POINTER; =20 - dloc->type_offset =3D dloc->op->offset + state->regs[reg].offset; + dloc->type_offset =3D offset + state->regs[reg].offset; =20 if (dwarf_tag(type_die) =3D=3D DW_TAG_typedef) die_get_real_type(type_die, &sized_type); @@ -1205,7 +1281,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, */ *type_die =3D state->regs[reg].type; =20 - dloc->type_offset =3D dloc->op->offset + state->regs[reg].offset; + dloc->type_offset =3D offset + state->regs[reg].offset; =20 /* Get the size of the actual type */ if (dwarf_aggregate_size(type_die, &size) < 0 || @@ -1224,7 +1300,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, */ *type_die =3D state->regs[reg].type; =20 - dloc->type_offset =3D dloc->op->offset; + dloc->type_offset =3D offset; =20 /* Get the size of the actual type */ if (dwarf_aggregate_size(type_die, &size) < 0 || @@ -1248,7 +1324,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, } =20 if (state->regs[reg].kind =3D=3D TSR_KIND_PERCPU_BASE) { - u64 var_addr =3D dloc->op->offset; + u64 var_addr =3D (s64) offset; int var_offset; =20 pr_debug_dtp("percpu var"); @@ -1275,7 +1351,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, =20 if (state->regs[reg].kind =3D=3D TSR_KIND_CONST && dso__kernel(map__dso(dloc->ms->map))) { - if (dloc->op->offset < 0 && reg !=3D state->stack_reg && reg !=3D dloc->= fbreg) + if (offset < 0 && reg !=3D state->stack_reg && reg !=3D dloc->fbreg) goto check_kernel; } check_non_register: @@ -1362,7 +1438,7 @@ static enum type_match_result check_matching_type(str= uct type_state *state, arch__is_x86(dloc->arch)) { pr_debug_dtp("this-cpu var"); =20 - addr =3D dloc->op->offset; + addr =3D (s64) offset; =20 if (get_global_var_type(cu_die, dloc, dloc->ip, addr, &offset, type_die)) { @@ -1373,8 +1449,8 @@ static enum type_match_result check_matching_type(str= uct type_state *state, } =20 /* Access to global variable like "-0x7dcf0500(,%rdx,8)" */ - if (dloc->op->offset < 0 && reg !=3D state->stack_reg) { - addr =3D (s64) dloc->op->offset; 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charset="utf-8" Enable data type profiling to track function return values in arm64 annotations by looking up the DWARF return type of called functions. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-arm64.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 8fda4d4d6888..9a3226526522 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -456,7 +456,7 @@ static bool is_readonly_branch_or_cmp(const char *name) } =20 static void update_insn_state_arm64(struct type_state *state, - struct data_loc_info *dloc, Dwarf_Die *cu_die __maybe_unused, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) { struct annotated_insn_loc loc; @@ -479,6 +479,8 @@ static void update_insn_state_arm64(struct type_state *= state, struct symbol *func =3D dl->ops.target.sym; const char *call_name; u64 call_addr; + struct type_state_reg *tsr; + Dwarf_Die type_die; =20 call_name =3D func ? func->name : dl->ops.target.name; pr_debug_dtp("call [%x] %s\n", insn_offset, call_name ?: ""); @@ -496,6 +498,20 @@ static void update_insn_state_arm64(struct type_state = *state, continue; invalidate_reg_state(reg); } + + /* Update register with the return type (if any) */ + if (call_name && die_find_func_rettype(cu_die, call_name, &type_die)) { + tsr =3D &state->regs[state->ret_reg]; + invalidate_reg_state(tsr); + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("call [%x] return -> reg%d", + insn_offset, state->ret_reg); + pr_debug_type_name(&type_die, tsr->kind); + } return; } =20 --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11CBE548553; Tue, 8 Sep 2026 13:05:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPKw1MTrzYQw9T; Tue, 8 Sep 2026 21:04:52 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id AB79F40577; Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S18; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 16/26] perf annotate-arm64: Support load instruction tracking Date: Tue, 8 Sep 2026 13:05:19 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S18 X-Coremail-Antispam: 1UD129KBjvJXoW3Xw1xKw4rtFyfXrWxXFW7XFb_yoWfuryfpF WDC3y5GrsrArs3WrsaqF48Wr9xuwn7Gr15Cr98Za9IyF42yrn5Ka93KFy2vF45Gr9ruw13 Ja1DKrnrXw42kaUanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHGb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW7JVWDJwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVW0oVCq3bIYCTnIWIevJa73UjIFyTuYvj 4E73dUUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to handle load instructions, tracking register state changes when data is loaded from memory to registers. Two main categories are considered: standard load (e.g, ldr variants) and load pair (ldp), for example: ldr dst, [src, #imm] ldp dst1, dst2, [src, #imm] For data type propagation, a load pair can be treated as two standard loads combined, first loading dst1 and then dst2. The difference is that when loading dst2, an additional memory offset 'mem_offset' after the first load must be added. This mem_offset can be derived from the instruction mnemonic and the size of the dst register. Each load operation is handled by introducing propagate_load_reg_state(). When processing a load pair, the case where dst and src registers are the same (e.g., ldp x0, x1, [x0]) also needs to be considered. Therefore, before propagating data types, a snapshot of the src register's state must be saved and then passed to propagate_load_reg_state(). Finally, handle the side effects of pre-index and post-index addressing via adjust_reg_index_state(). A real-world example is shown below: ffff80008011f5b0 : ffff80008011f5b8: ldr x0, [x0, #2712] // x0: struct rq* -> task_struct* * ffff80008011f5c0: ldr w1, [x0, #104] Before this commit, the type of x0 was incorrectly inferred as 'struct rq': find data type for 0x68(reg0) at pick_task_stop+0x10 var [8] reg0 offset 0 type=3D'struct rq*' chk [10] reg0 offset=3D0x68 ok=3D1 kind=3D1 (struct rq*) : Good! final result: type=3D'struct rq' After this commit, the type of x0 is correctly inferred as 'struct task_str= uct': find data type for 0x68(reg0) at pick_task_stop+0x10 var [8] reg0 offset 0 type=3D'struct rq*' ldr [8] 0xa98(reg0) -> reg0 type=3D'struct task_struct*' chk [10] reg0 offset=3D0x68 ok=3D1 kind=3D1 (struct task_struct*) : Good! final result: type=3D'struct task_struct' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 202 +++++++++++++++++- 1 file changed, 201 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 9a3226526522..c239ad9473dc 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -455,11 +455,206 @@ static bool is_readonly_branch_or_cmp(const char *na= me) !strcmp(name, "ccmp") || !strcmp(name, "ccmn"); } =20 +static int arm64__reg_size(const char *reg) +{ + if (!reg || !*reg || !arm64__is_reg(reg)) + return -1; + + if (reg[0] =3D=3D 'w') + return 4; + + if (reg[0] =3D=3D 'x' || !strncmp(reg, "sp", 2)) + return 8; + + return -1; +} + +/* Apply addressing mode (pre-index, post-index) to register state */ +static void adjust_reg_index_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, + struct annotated_op_loc *op_loc) +{ + struct type_state_reg *tsr; + int reg =3D op_loc->reg1; + int offset; + + if (op_loc->addr_mode !=3D PERF_AAM_PRE_INDEX && + op_loc->addr_mode !=3D PERF_AAM_POST_INDEX) + return; + + if (!has_reg_type(state, reg) || !state->regs[reg].ok) + return; + + tsr =3D &state->regs[reg]; + tsr->copied_from =3D -1; + + if (arch_get_reg_offset(dloc->arch, op_loc, reg, state, true, &offset)) { + invalidate_reg_state(tsr); + return; + } + + tsr->offset +=3D offset; + + pr_debug_dtp("%s [%x] %s-index %#x(reg%d) -> reg%d", dl->ins.name, + (u32) dl->al.offset, op_loc->addr_mode =3D=3D PERF_AAM_PRE_INDEX ? + "pre" : "post", offset, reg, reg); + pr_debug_type_name(&tsr->type, tsr->kind); +} + +/* + * Match standard load variants (ldr, ldur, ldar, ldp) that follow + * straightforward load semantics: memory source on the right + * and target registers on the left (written). Excludes exclusive loads + * (ldxr, ldxp, etc.) and acquire/exclusive combination variants. + */ +static bool is_standard_load_insn(const char *name) +{ + return !strncmp(name, "ldr", 3) || /* ldr, ldrb, ldrh, ldrsb, ldrsh, ld= rsw */ + !strncmp(name, "ldur", 4) || /* ldur, ldurb, ldurh, ldursb, ldurs= h, ldursw */ + !strncmp(name, "ldar", 4) || /* ldar, ldarb, ldarh */ + !strncmp(name, "ldp", 3); /* ldp, ldpsw */ +} + +/* + * For load insns: propagate type from source reg state @src_states to @dr= eg. + * + * @mem_offset accounts for additional memory byte offset when handling mu= lti-reg + * loads (e.g. second target reg in 'ldp'), which is added to the reg offs= et. + */ +static int propagate_load_reg_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, int dreg, + struct annotated_op_loc *src, + struct type_state_reg **src_states, + int mem_offset) +{ + struct type_state_reg *tsr; + struct type_state_reg *src_tsr =3D src_states[0]; + Dwarf_Die type_die; + u32 insn_offset =3D dl->al.offset; + int sreg =3D src->reg1; + int reg_offset; + + if (!has_reg_type(state, dreg)) + return -1; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + +retry: + if (arch_get_reg_offset(dloc->arch, src, sreg, state, false, ®_offset)) + return -1; + + reg_offset +=3D mem_offset; + + if (!src_tsr || !src_tsr->ok) + return -1; + + /* Dereference the pointer if it has one */ + if (src_tsr->kind =3D=3D TSR_KIND_TYPE && + die_deref_ptr_type(&src_tsr->type, + src_tsr->offset + reg_offset, &type_die)) { + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->ok =3D true; + + if (src->multi_regs) { + pr_debug_dtp("%s [%x] %#x(reg%d, reg%d) -> reg%d", + dl->ins.name, insn_offset, reg_offset, + src->reg1, src->reg2, dreg); + } else { + pr_debug_dtp("%s [%x] %#x(reg%d) -> reg%d", + dl->ins.name, insn_offset, reg_offset, + sreg, dreg); + } + pr_debug_type_name(&tsr->type, tsr->kind); + return 0; + } + + /* Or try another register if any */ + if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2 && + !(src->extend_type || src->shift_type)) { + sreg =3D src->reg2; + src_tsr =3D src_states[1]; + goto retry; + } + + return -1; +} + +static void update_load_insn_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + struct type_state_reg snapshots[2]; + struct type_state_reg *src_states[2] =3D {}; + + if (!src->mem_ref || /* exclude PC-relative loads */ + !has_reg_type(state, dst->reg1) || + (dst->multi_regs && !has_reg_type(state, dst->reg2))) + goto out_err_adjust; + + /* + * Snapshot source register states before updating destination registers. + * This avoids state corruption in aliased instructions (e.g., ldp x0, x1= , [x0]), + * ensuring the second destination load still uses the original base + * register state. + */ + if (has_reg_type(state, src->reg1)) { + snapshots[0] =3D state->regs[src->reg1]; + src_states[0] =3D &snapshots[0]; + } + if (src->multi_regs && has_reg_type(state, src->reg2)) { + snapshots[1] =3D state->regs[src->reg2]; + src_states[1] =3D &snapshots[1]; + } + + /* Handle the first destination register */ + if (propagate_load_reg_state(state, dloc, dl, dst->reg1, + src, src_states, /*mem_offset=3D*/0)) + goto out_err_adjust; + + /* Handle the second destination register (if any) */ + if (dst->multi_regs) { + int mem_offset; + + /* + * ldpsw loads two 32-bit signed words into 64-bit registers. + * Memory spacing between elements is 4 bytes, not the register size. + */ + if (!strcmp(dl->ins.name, "ldpsw")) + mem_offset =3D 4; + else + mem_offset =3D arm64__reg_size(dl->ops.target.raw); + + if (mem_offset < 0 || + propagate_load_reg_state(state, dloc, dl, dst->reg2, + src, src_states, mem_offset)) + goto out_err_adjust; + } + +out_adjust: + adjust_reg_index_state(state, dloc, dl, src); + return; + +out_err_adjust: + if (has_reg_type(state, dst->reg1)) + invalidate_reg_state(&state->regs[dst->reg1]); + if (dst->multi_regs && has_reg_type(state, dst->reg2)) + invalidate_reg_state(&state->regs[dst->reg2]); + goto out_adjust; +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) { struct annotated_insn_loc loc; + struct annotated_op_loc *src =3D &loc.ops[INSN_OP_SOURCE]; struct annotated_op_loc *dst =3D &loc.ops[INSN_OP_TARGET]; u32 insn_offset =3D dl->al.offset; =20 @@ -519,7 +714,8 @@ static void update_insn_state_arm64(struct type_state *= state, * Invalidate destination register(s) for unsupported instructions to * prevent stale type info from propagating to subsequent instructions. */ - if (has_reg_type(state, dst->reg1) && !dst->mem_ref) { + if (has_reg_type(state, dst->reg1) && !dst->mem_ref && + !is_standard_load_insn(dl->ins.name)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); invalidate_reg_state(&state->regs[dst->reg1]); @@ -530,6 +726,10 @@ static void update_insn_state_arm64(struct type_state = *state, pr_debug_dtp("\n"); return; } + + /* Memory to register transfers */ + if (is_standard_load_insn(dl->ins.name)) + update_load_insn_state(state, dloc, dl, src, dst); } #endif =20 --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A7A2559CB8; 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charset="utf-8" Extend update_insn_state_arm64() to handle standard store instructions (str, stur, stlr, stp). Exclusive stores (e.g., stxr, stxp) are omitted as they exhibit different operand semantics. Unlike load instructions, a store instruction sets a value in the struct within the memory where the destination register resides, and does not alter its type. Therefore, no processing is required for the transfer. The only point to note is that store instructions support pre-index and post-index addressing modes, so calling adjust_reg_index_state() is still necessary to handle their addressing. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index c239ad9473dc..9d43e2c2041c 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -649,6 +649,20 @@ static void update_load_insn_state(struct type_state *= state, goto out_adjust; } =20 +/* + * Match standard store variants (str, stur, stlr, stp) that follow + * straightforward store semantics: source registers on the left (read-onl= y) + * and memory target on the right. Excludes exclusive stores (stxr, stxp, = etc.) + * which have status/result register side effects. + */ +static bool is_standard_store_insn(const char *name) +{ + return !strncmp(name, "str", 3) || /* str, strb, strh */ + !strncmp(name, "stur", 4) || /* stur, sturb, sturh */ + !strncmp(name, "stlr", 4) || /* stlr, stlrb, stlrh */ + !strncmp(name, "stp", 3); /* stp */ +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -730,6 +744,17 @@ static void update_insn_state_arm64(struct type_state = *state, /* Memory to register transfers */ if (is_standard_load_insn(dl->ins.name)) update_load_insn_state(state, dloc, dl, src, dst); + /* Register to memory transfers */ + else if (is_standard_store_insn(dl->ins.name)) { + /* + * Ignore transfers since it'd set a value in a struct + * and won't change the type. + * + * Needs to update the pre-index and post-index addressing + * modes for the destination register. + */ + adjust_reg_index_state(state, dloc, dl, dst); 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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hfPLt3VgczKHN8r; Tue, 8 Sep 2026 21:05:42 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id CD9F74056E; Tue, 8 Sep 2026 21:05:43 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S20; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 18/26] perf annotate-data: Expand type_state_reg imm_value to u64 Date: Tue, 8 Sep 2026 13:05:21 +0000 Message-Id: <288e59160bf51e04ba6112676bf8315279635d13.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S20 X-Coremail-Antispam: 1UD129KBjvJXoWxJr18try5GrW7ZF1DCr4kZwb_yoW8Cw43p3 90k347Gw15Wr4YgrnxtFWrXFyS9F13Za4fGryYgw1fZFWSqFn3tFyIqrWYyFW8W3s7Cw1U JwnYgr4Dt3ykGaUanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHGb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_GcCE3s1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8 JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20V AGYxC7M4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26rWY6Fy7MxkF7I0Ew4C2 6cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c 02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_ WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW7JVWDJwCI42IY6xIIjxv20xvEc7 CjxVAFwI0_Cr1j6rxdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVW0oVCq3bIYCTnIWIevJa73UjIFyTuYvj 4E73dUUUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The arm64 'adrp + add/ldr' instruction pair involves global variable address calculation and passing, which requires storing the 64-bit address in type_state_reg. Currently, there is no field in type_state_reg that can hold such an address. The most likely candidate for reuse is imm_value, but it is defined as u32, which limits the size of values it can carry. To address this, expand imm_value from u32 to u64. Also update related compilation warnings and fix the sign-extension issue introduced by this change. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-x86.c | 4 ++-- tools/perf/util/annotate-data.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index aa381d25a63b..f5e40cef08ab 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -536,11 +536,11 @@ static void update_insn_state_x86(struct type_state *= state, =20 if (src->imm) { tsr->kind =3D TSR_KIND_CONST; - tsr->imm_value =3D src->offset; + tsr->imm_value =3D (s64)src->offset; tsr->offset =3D 0; tsr->ok =3D true; =20 - pr_debug_dtp("mov [%x] imm=3D%#x -> reg%d\n", + pr_debug_dtp("mov [%x] imm=3D%#"PRIx64" -> reg%d\n", insn_offset, tsr->imm_value, dst->reg1); return; } diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index e6ca47e25e04..3bce63e23a58 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -173,7 +173,7 @@ extern struct annotated_data_stat ann_data_stat; */ struct type_state_reg { Dwarf_Die type; - u32 imm_value; + u64 imm_value; /* * The offset within the struct that the register points to. * A value of 0 means the register points to the beginning. --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBC9855C1D1; Tue, 8 Sep 2026 13:05:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872764; cv=none; b=rGaVle9kZ9cyU96BHaIlwzJ0dc0Xihn/0VLajmIR96pXkNAc2bdT0xNoRXTblX/CdxEOoWZjD3gQpnJb3pNB3tAG6yz8aMOJTIXPdm3OpLFxUNqvUJ/dJtpP3XmfFaUG4TQH5P9+fkz4AZnC8jQq/7higFvPrrsyK5PfsC3zHxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872764; c=relaxed/simple; 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Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 19/26] perf annotate-data: Track imm_value for stack variables Date: Tue, 8 Sep 2026 13:05:22 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S21 X-Coremail-Antispam: 1UD129KBjvJXoWxGF18uw17Jw1DGFyUGFW8Crg_yoW7JF4xpr WDWFy7W3W7Wr4IqrsxJF4UXr93Gws2gr1Fk34qqFnavFyxtr1fG3s7tFW5tF47Aryvyw17 Jwn0kr4DXw47KaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHlb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Wrv_ZF1lc7CjxVAKzI0E Y4vE52x082I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWr XwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVWxJr0_GcWlIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v2 6F4j6r4UJwCI42IY6I8E87Iv6xkF7I0E14v26rxl6s0DYxBIdaVFxhVjvjDU0xZFpf9x0z CjgJUUUUUU= X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Currently, imm_value is tracked in registers but dropped when values are saved to or loaded from stack variables during type profiling. If a register of type TSR_KIND_CONST is stored to the stack, its value will be lost. Add an imm_value field to struct type_state_stack and update set_stack_state() and findnew_stack_state() to accept and preserve the immediate value when updating stack state. Reviewed-by: Shuai Xue Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-x86.c | 8 ++++++-- tools/perf/util/annotate-data.c | 13 +++++++------ tools/perf/util/annotate-data.h | 5 +++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index f5e40cef08ab..21729e153fa0 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -591,6 +591,7 @@ static void update_insn_state_x86(struct type_state *st= ate, tsr->type =3D stack->type; tsr->kind =3D stack->kind; tsr->offset =3D stack->ptr_offset; + tsr->imm_value =3D stack->imm_value; tsr->ok =3D true; } else if (die_get_member_type(&stack->type, offset - stack->offset, @@ -598,6 +599,7 @@ static void update_insn_state_x86(struct type_state *st= ate, tsr->type =3D type_die; tsr->kind =3D TSR_KIND_TYPE; tsr->offset =3D 0; + tsr->imm_value =3D 0; tsr->ok =3D true; } else { invalidate_reg_state(tsr); @@ -773,10 +775,12 @@ static void update_insn_state_x86(struct type_state *= state, */ if (!stack->compound) set_stack_state(stack, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->imm_value); } else { findnew_stack_state(state, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->imm_value); } =20 if (dst->reg1 =3D=3D fbreg) { diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 754c0efe2077..2150af5599fb 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -590,7 +590,7 @@ struct type_state_stack *find_stack_state(struct type_s= tate *state, } =20 void set_stack_state(struct type_state_stack *stack, int offset, u8 kind, - Dwarf_Die *type_die, int ptr_offset) + Dwarf_Die *type_die, int ptr_offset, u64 imm_value) { int tag; Dwarf_Word size; @@ -607,8 +607,9 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, stack->offset =3D offset; stack->ptr_offset =3D ptr_offset; stack->kind =3D kind; + stack->imm_value =3D imm_value; =20 - if (kind =3D=3D TSR_KIND_POINTER) { + if (kind =3D=3D TSR_KIND_POINTER || kind =3D=3D TSR_KIND_CONST) { stack->compound =3D false; return; } @@ -629,18 +630,18 @@ void set_stack_state(struct type_state_stack *stack, = int offset, u8 kind, struct type_state_stack *findnew_stack_state(struct type_state *state, int offset, u8 kind, Dwarf_Die *type_die, - int ptr_offset) + int ptr_offset, u64 imm_value) { struct type_state_stack *stack =3D find_stack_state(state, offset); =20 if (stack) { - set_stack_state(stack, offset, kind, type_die, ptr_offset); + set_stack_state(stack, offset, kind, type_die, ptr_offset, imm_value); return stack; } =20 stack =3D malloc(sizeof(*stack)); if (stack) { - set_stack_state(stack, offset, kind, type_die, ptr_offset); + set_stack_state(stack, offset, kind, type_die, ptr_offset, imm_value); list_add(&stack->list, &state->stack_vars); } return stack; @@ -935,7 +936,7 @@ static void update_var_state(struct type_state *state, = struct data_loc_info *dlo continue; =20 findnew_stack_state(state, offset, TSR_KIND_TYPE, - &mem_die, /*ptr_offset=3D*/0); + &mem_die, /*ptr_offset=3D*/0, /*imm_value=3D*/0); =20 if (var->reg =3D=3D state->stack_reg) { pr_debug_dtp("var [%"PRIx64"] %#x(reg%d)", diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index 3bce63e23a58..36ca7819a6f0 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -199,6 +199,7 @@ struct type_state_stack { int size; bool compound; u8 kind; + u64 imm_value; }; =20 /* @@ -253,9 +254,9 @@ bool has_reg_type(struct type_state *state, int reg); struct type_state_stack *findnew_stack_state(struct type_state *state, int offset, u8 kind, Dwarf_Die *type_die, - int ptr_offset); + int ptr_offset, u64 imm_value); void set_stack_state(struct type_state_stack *stack, int offset, u8 kind, - Dwarf_Die *type_die, int ptr_offset); + Dwarf_Die *type_die, int ptr_offset, u64 imm_value); struct type_state_stack *find_stack_state(struct type_state *state, int offset); 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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPKw3t30zYQw9W; Tue, 8 Sep 2026 21:04:52 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 0E0F540579; Tue, 8 Sep 2026 21:05:44 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S22; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 20/26] perf annotate-x86: Delete stale stack state on store of untracked register Date: Tue, 8 Sep 2026 13:05:23 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S22 X-Coremail-Antispam: 1UD129KBjvJXoWxur4xGry8KFyxKrWUGF4xCrg_yoW5KrW7pr yDC343Ww17Gr4SqFnxAFW5XF95Crs7X3WrC3s0qwn2vF1xJr1fG3s7tFWYyF47Xr92kw12 yw1DKr4DXa12gaDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHlb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Wrv_ZF1lc7CjxVAKzI0E Y4vE52x082I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWr XwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVWxJr0_GcWlIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v2 6F4j6r4UJwCI42IY6I8E87Iv6xkF7I0E14v26rxl6s0DYxBIdaVFxhVjvjDU0xZFpf9x0z CjgJUUUUUU= X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" When a register without a tracked type is stored to a stack slot that previously held a valid type, the code currently performs an early return. This leaves the old type information intact in the stack state. As a result, a stale type bug occurs: 1. A tracked register is stored into a stack slot. 2. The register becomes untracked/invalid (e.g., across a function call). 3. The now-untracked register is stored into the same stack slot. 4. Subsequent loads from that slot erroneously pick up the old stale type because the stack entry was never invalidated. Fix this by introducing delete_stack_state() to search and free a stack entry for a given offset. When storing an untracked or invalid source register into a stack location, call delete_stack_state() to delete the stale entry before returning. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-x86.c | 17 +++++++++++++---- tools/perf/util/annotate-data.c | 10 ++++++++++ tools/perf/util/annotate-data.h | 1 + 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index 21729e153fa0..3a6ea7e978e0 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -753,15 +753,24 @@ static void update_insn_state_x86(struct type_state *= state, } /* Case 3. register to memory transfers */ if (!src->mem_ref && dst->mem_ref) { - if (!has_reg_type(state, src->reg1) || - !state->regs[src->reg1].ok) - return; - /* Check stack variables with offset */ if (dst->reg1 =3D=3D fbreg || dst->reg1 =3D=3D state->stack_reg) { struct type_state_stack *stack; int offset =3D dst->offset - fboff; =20 + if (!has_reg_type(state, src->reg1) || + !state->regs[src->reg1].ok) { + stack =3D find_stack_state(state, offset); + /* + * Preserve compound states when only a member + * is overwritten. + */ + if (stack && !stack->compound) + delete_stack_state(state, offset); + + return; + } + tsr =3D &state->regs[src->reg1]; =20 stack =3D find_stack_state(state, offset); diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 2150af5599fb..1936822c73f2 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -647,6 +647,16 @@ struct type_state_stack *findnew_stack_state(struct ty= pe_state *state, return stack; } =20 +void delete_stack_state(struct type_state *state, int offset) +{ + struct type_state_stack *stack =3D find_stack_state(state, offset); + + if (stack) { + list_del(&stack->list); + free(stack); + } +} + void invalidate_reg_state(struct type_state_reg *reg) { reg->kind =3D TSR_KIND_INVALID; diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index 36ca7819a6f0..02d5602c5e20 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -259,6 +259,7 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, Dwarf_Die *type_die, int ptr_offset, u64 imm_value); struct type_state_stack *find_stack_state(struct type_state *state, int offset); +void delete_stack_state(struct type_state *state, int offset); void invalidate_reg_state(struct type_state_reg *reg); bool get_global_var_type(Dwarf_Die *cu_die, struct data_loc_info *dloc, u64 ip, u64 var_addr, int *var_offset, --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB45555C1CF; Tue, 8 Sep 2026 13:05:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872762; cv=none; b=uUoF2uKP0dHT++5AoTZPk8uXw3/YQtL7WG/fKicguURE1B7rzPJYMB3aSXUYB3MiEECLahKrQlLd7qLCKajR+AW+cCTWG4M/1AA4/5zXJTpX25buAZ/g8f2T25pllKEg2I4CUMs1D83z+Bky+ZOLBxN5shPV5Uk3PSMPUheF72w= ARC-Message-Signature: i=1; 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Tue, 8 Sep 2026 21:05:44 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S23; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 21/26] perf annotate-arm64: Support stack variable tracking Date: Tue, 8 Sep 2026 13:05:24 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S23 X-Coremail-Antispam: 1UD129KBjvJXoW3XryDCr1rWr1UJrW3Wr1DAwb_yoWxZr18pF 4DGFyagrs7Ar4SgFs3XF48Xr93Cws7KF1qkr90kan2yFy3tr1FkayktFWavay5Jr97Zw13 Jw1DKrsrXw47taDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Wrv_ZF1lc7CjxVAKzI0E Y4vE52x082I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWr XwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVW0oVCq3wCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_ Cr0_Gr1UMIIF0xvEx4A2jsIEc7CjxVAFwI0_GcCE3sUvcSsGvfC2KfnxnUUI43ZEXa7xRx noUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to track data types stored on the stack. The implementation handles: 1. Stack Loads: Identify when a register is loaded from a stack slot and update the register's type state based on the tracked stack content or compound member types. 2. Stack Stores: Update or create new stack state entries when a tracked register type is stored to the stack. Similar to loads, stores also support saving one or two registers (in the case of 'stp'). Therefore, propagate_store_reg_state() is introduced. With these changes, the instruction tracker can now follow data types as they move between registers and memory, specifically for function local variables and compiler-spilled values on arm64. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 159 ++++++++++++++++-- 1 file changed, 149 insertions(+), 10 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 9d43e2c2041c..d520975c5936 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -535,6 +535,8 @@ static int propagate_load_reg_state(struct type_state *= state, u32 insn_offset =3D dl->al.offset; int sreg =3D src->reg1; int reg_offset; + int fbreg =3D dloc->fbreg; + int fboff =3D 0; =20 if (!has_reg_type(state, dreg)) return -1; @@ -542,12 +544,57 @@ static int propagate_load_reg_state(struct type_state= *state, tsr =3D &state->regs[dreg]; tsr->copied_from =3D -1; =20 + if (dloc->fb_cfa) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 pc =3D map__rip_2objdump(dloc->ms->map, ip); + + if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0) + fbreg =3D -1; + } + retry: if (arch_get_reg_offset(dloc->arch, src, sreg, state, false, ®_offset)) return -1; =20 reg_offset +=3D mem_offset; =20 + /* Check stack variables with offset */ + if (sreg =3D=3D fbreg || sreg =3D=3D state->stack_reg) { + struct type_state_stack *stack; + int offset =3D sreg =3D=3D fbreg ? reg_offset - fboff : reg_offset; + + stack =3D find_stack_state(state, offset); + if (stack =3D=3D NULL) { + return -1; + } else if (!stack->compound) { + tsr->type =3D stack->type; + tsr->kind =3D stack->kind; + tsr->offset =3D stack->ptr_offset; + tsr->imm_value =3D stack->imm_value; + tsr->ok =3D true; + } else if (die_get_member_type(&stack->type, + offset - stack->offset, + &type_die)) { + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->imm_value =3D 0; + tsr->ok =3D true; + } else { + return -1; + } + + if (sreg =3D=3D fbreg) { + pr_debug_dtp("%s [%x] -%#x(stack) -> reg%d", + dl->ins.name, insn_offset, -offset, dreg); + } else { + pr_debug_dtp("%s [%x] %#x(reg%d) -> reg%d", + dl->ins.name, insn_offset, offset, sreg, dreg); + } + pr_debug_type_name(&tsr->type, tsr->kind); + return 0; + } + if (!src_tsr || !src_tsr->ok) return -1; =20 @@ -663,6 +710,106 @@ static bool is_standard_store_insn(const char *name) !strncmp(name, "stp", 3); /* stp */ } =20 +/* + * For store insns: propagate type from @sreg to the memory location refer= enced + * by @dst, applying @mem_offset to account for multi-regs stores (e.g. st= p). + */ +static void propagate_store_reg_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, int sreg, + struct annotated_op_loc *dst, + int mem_offset) +{ + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + int dreg =3D dst->reg1; + int reg_offset; + int fbreg =3D dloc->fbreg; + int fboff =3D 0; + + if (arch_get_reg_offset(dloc->arch, dst, dreg, state, false, ®_offset)) + return; + + reg_offset +=3D mem_offset; + + if (dloc->fb_cfa) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 pc =3D map__rip_2objdump(dloc->ms->map, ip); + + if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0) + fbreg =3D -1; + } + + /* Check stack variables with offset */ + if (dreg =3D=3D fbreg || dreg =3D=3D state->stack_reg) { + struct type_state_stack *stack; + int offset =3D dreg =3D=3D fbreg ? reg_offset - fboff : reg_offset; + + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) { + stack =3D find_stack_state(state, offset); + /* Preserve compound states when only a member is overwritten. */ + if (stack && !stack->compound) + delete_stack_state(state, offset); + + return; + } + + tsr =3D &state->regs[sreg]; + + stack =3D find_stack_state(state, offset); + if (stack) { + if (!stack->compound) + set_stack_state(stack, offset, tsr->kind, &tsr->type, + tsr->offset, tsr->imm_value); + /* + * If it's a compound type, it means attempting to + * write to a member value of the compound type without + * changing the compound type itself, so do nothing. + */ + } else { + findnew_stack_state(state, offset, tsr->kind, &tsr->type, + tsr->offset, tsr->imm_value); + } + + if (dreg =3D=3D fbreg) { + pr_debug_dtp("%s [%x] reg%d -> -%#x(stack)", + dl->ins.name, insn_offset, sreg, -offset); + } else { + pr_debug_dtp("%s [%x] reg%d -> %#x(reg%d)", + dl->ins.name, insn_offset, sreg, offset, dreg); + } + if (tsr->offset !=3D 0) + pr_debug_dtp(" reg%d offset %#x ->", sreg, tsr->offset); + + pr_debug_type_name(&tsr->type, tsr->kind); + } + /* + * Ignore other transfers since it'd set a value in a struct + * and won't change the type. + */ +} + +static void update_store_insn_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + /* Handle the first source register */ + propagate_store_reg_state(state, dloc, dl, src->reg1, dst, /*mem_offset= =3D*/0); + + /* Handle the second source register (if any) */ + if (src->multi_regs) { + int mem_offset =3D arm64__reg_size(dl->ops.source.raw); + + if (mem_offset >=3D 0) + propagate_store_reg_state(state, dloc, dl, src->reg2, + dst, mem_offset); + } + + adjust_reg_index_state(state, dloc, dl, dst); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -745,16 +892,8 @@ static void update_insn_state_arm64(struct type_state = *state, if (is_standard_load_insn(dl->ins.name)) update_load_insn_state(state, dloc, dl, src, dst); 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Tue, 8 Sep 2026 21:05:44 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S24; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 22/26] perf annotate-arm64: Support 'mov' instruction tracking Date: Tue, 8 Sep 2026 13:05:25 +0000 Message-Id: <6516a18b5618a169c2e180c296632e12c7f6697a.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S24 X-Coremail-Antispam: 1UD129KBjvJXoWxKw15JF18trWxGr4fGw47XFb_yoW7GFWrpa 1DCw15G39Fqr42grsIqF47Xr9a9w4Igr12kryqq39IyFW3tr1rKa97tFWavF45JrykCw17 Ja1DKFW5Xw42kaUanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Wrv_ZF1lc7CjxVAKzI0E Y4vE52x082I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWr XwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVW0oVCq3wCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_ Cr0_Gr1UMIIF0xvEx4A2jsIEc7CjxVAFwI0_GcCE3sUvcSsGvfC2KfnxnUUI43ZEXa7xRx noUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to support register-to-register and immediate-to-register 'mov' instructions. For register-to-register 'mov' (e.g., mov dreg, sreg), propagate data type information from the source register to the destination register. For immediate-to-register 'mov' (e.g., mov dreg, #imm), store the immediate value in the destination register's imm_value field and set its kind to TSR_KIND_CONST, allowing subsequent instructions to resolve it as a constant. A real-world example is shown below: ffff8000803eebf8 : ffff8000803eec20: mov x21, x0 // x0 (struct vm_area_struct*) -= > x21 ffff8000803eec28: ldr x2, [x0, #112] ffff8000803eec2c: cbz x2, ffff8000803eec94 * ffff8000803eec94: ldr x0, [x21, #152] Before this commit, the type of x21 was unknown, causing the subsequent inference to fail: var [0] reg0 offset 0 type=3D'struct vm_area_struct*' size=3D0x8 chk [9c] reg21 offset=3D0x98 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the type of x21 is correctly inferred as 'vm_area_struct= ': var [0] reg0 offset 0 type=3D'struct vm_area_struct*' size=3D0x8 mov [28] reg0 -> reg21 type=3D'struct vm_area_struct*' size=3D0x8 chk [9c] reg21 offset=3D0x98 ok=3D1 kind=3D1 (struct vm_area_struct*) : G= ood! found by insn track: 0x98(reg21) type-offset=3D0x98 final result: type=3D'struct vm_area_struct' size=3D0xb0 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 60 ++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index d520975c5936..2f8bedf583c1 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include #include #include @@ -605,6 +606,7 @@ static int propagate_load_reg_state(struct type_state *= state, tsr->type =3D type_die; tsr->kind =3D TSR_KIND_TYPE; tsr->offset =3D 0; + tsr->imm_value =3D 0; tsr->ok =3D true; =20 if (src->multi_regs) { @@ -810,6 +812,58 @@ static void update_store_insn_state(struct type_state = *state, adjust_reg_index_state(state, dloc, dl, dst); } =20 +static void update_mov_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + int sreg =3D src->reg1; + int dreg =3D dst->reg1; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + + if (src->imm) { + invalidate_reg_state(tsr); + tsr->kind =3D TSR_KIND_CONST; + tsr->imm_value =3D (s64)src->offset; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("mov [%x] imm=3D%#"PRIx64" -> reg%d\n", + insn_offset, tsr->imm_value, dreg); + return; + } + + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) { + invalidate_reg_state(tsr); + return; + } + + tsr->type =3D state->regs[sreg].type; + tsr->kind =3D state->regs[sreg].kind; + tsr->imm_value =3D state->regs[sreg].imm_value; + tsr->offset =3D state->regs[sreg].offset; + tsr->ok =3D state->regs[sreg].ok; + /* + * lifetime_active and lifetime_end represent DWARF variable lifetime + * ranges tied to the source register. Copying them risks incorrectly + * invalidating the destination register after a call instruction, + * so intentionally omit them. + */ + + if (tsr->kind =3D=3D TSR_KIND_TYPE || tsr->kind =3D=3D TSR_KIND_POINTER) + tsr->copied_from =3D sreg; + + pr_debug_dtp("mov [%x] reg%d -> reg%d", insn_offset, sreg, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -876,6 +930,7 @@ static void update_insn_state_arm64(struct type_state *= state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && !dst->mem_ref && + strcmp(dl->ins.name, "mov") && !is_standard_load_insn(dl->ins.name)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); @@ -888,8 +943,11 @@ static void update_insn_state_arm64(struct type_state = *state, return; } =20 + /* Register to register or imm value to register transfers */ + if (!strcmp(dl->ins.name, "mov")) + update_mov_insn_state(state, dl, src, dst); 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Tue, 8 Sep 2026 21:05:44 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHLUoeCKBqX3XjBA--.22748S25; Tue, 08 Sep 2026 21:05:43 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 23/26] perf annotate-arm64: Support 'add' instruction tracking Date: Tue, 8 Sep 2026 13:05:26 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgDHLUoeCKBqX3XjBA--.22748S25 X-Coremail-Antispam: 1UD129KBjvJXoWxXw15Xw1fJw1UJrWkurWruFg_yoWrtr4kpF ZFk34UWws2yrsFgrs3JFWfXr9akwsrGr1jkr98XwsayFW3trn5Ka93KrW2vFW5Gr93Cw13 tw4DKrs3Xw42kaUanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Wrv_ZF1lc7CjxVAKzI0E Y4vE52x082I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWr XwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVW0oVCq3wCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_ Cr0_Gr1UMIIF0xvEx4A2jsIEc7CjxVAFwI0_GcCE3sUvcSsGvfC2KfnxnUUI43ZEXa7xRx noUUUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to track 'add' instructions for structure member address calculation. Unlike x86, the arm64 'add' instruction has an extra base register among its source operands. Therefore, in terms of propagating the data type, it is essentially performing a 'mov', except that before the 'mov', it first needs to be updated by adding the offset or reg2. A real-world example is shown below: ffff80008001c9a8 : ffff80008001c9c4: add x19, x0, #0xeb8 // x0 (task_struct*) + 0xeb8 ->= x19 * ffff80008001c9d0: ldr x0, [x19] Before this commit, the type flow broke at the 'add' instruction, leaving the subsequent load with no type information: chk [28] reg19 offset=3D0 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker correctly follows the member address calculation: var [0] reg0 offset 0 type=3D'struct task_struct*' add [1c] address of 0xeb8(reg0) -> reg19 type=3D'struct task_struct*' chk [28] reg19 offset=3D0 ok=3D1 kind=3D1 (struct task_struct*) : Good! found by insn track: 0(reg19) type-offset=3D0xeb8 final result: type=3D'struct task_struct' Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 72 ++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 2f8bedf583c1..e237b9142684 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -864,6 +864,72 @@ static void update_mov_insn_state(struct type_state *s= tate, pr_debug_type_name(&tsr->type, tsr->kind); } =20 +static void update_add_insn_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + struct type_state_reg src_tsr; + u32 insn_offset =3D dl->al.offset; + int sreg =3D src->reg1; + int dreg =3D dst->reg1; + int reg_offset; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + +retry: + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) { + invalidate_reg_state(tsr); + return; + } + + src_tsr =3D state->regs[sreg]; + + if (arch_get_reg_offset(dloc->arch, src, sreg, state, false, ®_offset)) + goto try_other_reg; + + if (src_tsr.kind =3D=3D TSR_KIND_CONST) { + tsr->kind =3D src_tsr.kind; + tsr->imm_value =3D src_tsr.imm_value + reg_offset; + tsr->offset =3D 0; + tsr->ok =3D src_tsr.ok; + + pr_debug_dtp("add [%x] imm %#x(reg%d) -> reg%d\n", + insn_offset, reg_offset, sreg, dreg); + return; + } + + if (src_tsr.kind =3D=3D TSR_KIND_POINTER || + (src_tsr.kind =3D=3D TSR_KIND_TYPE && + dwarf_tag(&src_tsr.type) =3D=3D DW_TAG_pointer_type)) { + tsr->type =3D src_tsr.type; + tsr->kind =3D src_tsr.kind; + tsr->imm_value =3D src_tsr.imm_value; + tsr->offset =3D src_tsr.offset + reg_offset; + tsr->ok =3D src_tsr.ok; + + pr_debug_dtp("add [%x] address of %#x(reg%d) -> reg%d", + insn_offset, reg_offset, sreg, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + +try_other_reg: + /* Try another register if any */ + if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2 && + !(src->extend_type || src->shift_type)) { + sreg =3D src->reg2; + goto retry; + } + invalidate_reg_state(tsr); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -930,7 +996,7 @@ static void update_insn_state_arm64(struct type_state *= state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && !dst->mem_ref && - strcmp(dl->ins.name, "mov") && + strcmp(dl->ins.name, "add") && strcmp(dl->ins.name, "mov") && !is_standard_load_insn(dl->ins.name)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); @@ -943,8 +1009,10 @@ static void update_insn_state_arm64(struct type_state= *state, return; } =20 + if (!strcmp(dl->ins.name, "add")) + update_add_insn_state(state, dloc, dl, src, dst); /* Register to register or imm value to register transfers */ - if (!strcmp(dl->ins.name, "mov")) + else if (!strcmp(dl->ins.name, "mov")) update_mov_insn_state(state, dl, src, dst); /* Memory to register transfers */ else if (is_standard_load_insn(dl->ins.name)) --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E378356511D; Tue, 8 Sep 2026 13:06:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872785; cv=none; b=OeDeUNLj0i8cJ0wrmvBJPXHzHBzglcPv6BHyXxGD8YudvZUcvC8uG9BdoaJklT6CNFZrd6Qu/75unOBe5tjYSOrb3MsREnpzZJUFaZ0RZUbKpMTfscC/47nWT/SdHvxgcqznPV26JsbyRStnMWZhNEXC2IDMVG1UAxxiSe1Z1Us= ARC-Message-Signature: i=1; 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Tue, 8 Sep 2026 21:06:20 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with UTF8SMTPA id _Ch0CgBHurdFCKBqUhjWBA--.26443S2; Tue, 08 Sep 2026 21:06:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 24/26] perf annotate-arm64: Support 'adrp' instruction to track global variables Date: Tue, 8 Sep 2026 13:06:05 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgBHurdFCKBqUhjWBA--.26443S2 X-Coremail-Antispam: 1UD129KBjvJXoW3AF4UZr1xXrWfGr13CF17ZFb_yoWfKw4rpF yDC34UWw47tr4Sgrs3XFWUXr9a9ws7GFyjkryqvrsayFW7trn3Ga97tFWaqFW5GF95Zw13 Jw1DKr4DXw42kaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBlb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxV AFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2 j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7x kEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIE c7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wrylc7CjxVAKzI0EY4vE52x082I5Mx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_ Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW0oVCq 3wCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Cr0_Gr1UMIIF0x vEx4A2jsIEc7CjxVAFwI0_GcCE3sUvcSsGvfC2KfnxnUUI43ZEXa7sRM2-ntUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to track global variable types calculated via page-relative addressing. On arm64, global variables are typically accessed by first calculating the page address using 'adrp', followed by an 'add' or 'ldr' to get the specific symbol address. Without tracking 'adrp', the instruction tracker loses the base address, making it impossible to resolve global symbols and their associated DWARF types. Introduce TSR_KIND_GLOBAL_ADDR to represent a partial global address state. When encountering 'adrp', store the page-aligned target address in the register's type state. Upon a subsequent 'add' or 'ldr' instruction that references a TSR_KIND_GLOBAL_ADDR register, combine the page address with the immediate offset. A real-world example is shown below: ffff80008032e008 : ffff80008032e048: adrp x24, ffff80008202f000 ffff80008032e050: add x24, x24, #0xd40 * ffff80008032e078: ldr x0, [x24] Before this commit, x24 was unknown, leading to no type information: chk [70] reg24 offset=3D0 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker correctly follows the adrp/add flow: adrp [40] global addr=3D0xffff80008202f000 -> reg24 add [48] global 0xd40(reg24) -> reg24 chk [70] reg24 offset=3D0 ok=3D1 kind=3D7 global addr : Good! final result: type=3D'struct folio*' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 83 +++++++++++++++++-- tools/perf/util/annotate-data.c | 25 +++++- tools/perf/util/annotate-data.h | 1 + 3 files changed, 99 insertions(+), 10 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index e237b9142684..9daf95905545 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -524,7 +524,7 @@ static bool is_standard_load_insn(const char *name) * loads (e.g. second target reg in 'ldp'), which is added to the reg offs= et. */ static int propagate_load_reg_state(struct type_state *state, - struct data_loc_info *dloc, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl, int dreg, struct annotated_op_loc *src, struct type_state_reg **src_states, @@ -622,6 +622,33 @@ static int propagate_load_reg_state(struct type_state = *state, return 0; } =20 + /* Or check if it's a global variable */ + if (src_tsr->kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 addr =3D src_tsr->imm_value + reg_offset; + int offset; + + if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, &type_die) || + !die_get_member_type(&type_die, offset, &type_die)) + return -1; + + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->imm_value =3D 0; + tsr->ok =3D true; + + if (src->multi_regs) { + pr_debug_dtp("%s [%x] global (reg%d, reg%d) -> reg%d", + dl->ins.name, insn_offset, src->reg1, src->reg2, dreg); + } else { + pr_debug_dtp("%s [%x] global (reg%d) -> reg%d", + dl->ins.name, insn_offset, sreg, dreg); + } + pr_debug_type_name(&tsr->type, tsr->kind); + return 0; + } + /* Or try another register if any */ if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2 && !(src->extend_type || src->shift_type)) { @@ -634,7 +661,7 @@ static int propagate_load_reg_state(struct type_state *= state, } =20 static void update_load_insn_state(struct type_state *state, - struct data_loc_info *dloc, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl, struct annotated_op_loc *src, struct annotated_op_loc *dst) @@ -663,7 +690,7 @@ static void update_load_insn_state(struct type_state *s= tate, } =20 /* Handle the first destination register */ - if (propagate_load_reg_state(state, dloc, dl, dst->reg1, + if (propagate_load_reg_state(state, dloc, cu_die, dl, dst->reg1, src, src_states, /*mem_offset=3D*/0)) goto out_err_adjust; =20 @@ -681,7 +708,7 @@ static void update_load_insn_state(struct type_state *s= tate, mem_offset =3D arm64__reg_size(dl->ops.target.raw); =20 if (mem_offset < 0 || - propagate_load_reg_state(state, dloc, dl, dst->reg2, + propagate_load_reg_state(state, dloc, cu_die, dl, dst->reg2, src, src_states, mem_offset)) goto out_err_adjust; } @@ -894,14 +921,16 @@ static void update_add_insn_state(struct type_state *= state, if (arch_get_reg_offset(dloc->arch, src, sreg, state, false, ®_offset)) goto try_other_reg; =20 - if (src_tsr.kind =3D=3D TSR_KIND_CONST) { + if (src_tsr.kind =3D=3D TSR_KIND_CONST || src_tsr.kind =3D=3D TSR_KIND_GL= OBAL_ADDR) { tsr->kind =3D src_tsr.kind; + /* For 'adrp + add' pair: resolve the full global variable address. */ tsr->imm_value =3D src_tsr.imm_value + reg_offset; tsr->offset =3D 0; tsr->ok =3D src_tsr.ok; =20 - pr_debug_dtp("add [%x] imm %#x(reg%d) -> reg%d\n", - insn_offset, reg_offset, sreg, dreg); + pr_debug_dtp("add [%x] %s %#x(reg%d) -> reg%d\n", + insn_offset, src_tsr.kind =3D=3D TSR_KIND_CONST ? + "imm" : "global", reg_offset, sreg, dreg); return; } =20 @@ -930,6 +959,39 @@ static void update_add_insn_state(struct type_state *s= tate, invalidate_reg_state(tsr); } =20 +static void update_adrp_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + int dreg =3D dst->reg1; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + + if (!dl->ops.source.addr) { + invalidate_reg_state(tsr); + return; + } + + tsr->kind =3D TSR_KIND_GLOBAL_ADDR; + /* + * Stores a partial page-relative address. The full absolute address + * of the global variable will be resolved when a subsequent 'add' or + * 'ldr' instruction consumes this register. + */ + tsr->imm_value =3D dl->ops.source.addr; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("adrp [%x] global addr=3D%#"PRIx64" -> reg%d\n", + insn_offset, tsr->imm_value, dreg); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -996,6 +1058,7 @@ static void update_insn_state_arm64(struct type_state = *state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && !dst->mem_ref && + strcmp(dl->ins.name, "adrp") && strcmp(dl->ins.name, "add") && strcmp(dl->ins.name, "mov") && !is_standard_load_insn(dl->ins.name)) { pr_debug_dtp("%s [%x] invalidate reg%d", @@ -1009,14 +1072,16 @@ static void update_insn_state_arm64(struct type_sta= te *state, return; } =20 - if (!strcmp(dl->ins.name, "add")) + if (!strcmp(dl->ins.name, "adrp")) + update_adrp_insn_state(state, dl, dst); + else if (!strcmp(dl->ins.name, "add")) update_add_insn_state(state, dloc, dl, src, dst); /* Register to register or imm value to register transfers */ else if (!strcmp(dl->ins.name, "mov")) update_mov_insn_state(state, dl, src, dst); /* Memory to register transfers */ else if (is_standard_load_insn(dl->ins.name)) - update_load_insn_state(state, dloc, dl, src, dst); + update_load_insn_state(state, dloc, cu_die, dl, src, dst); /* Register to memory transfers */ else if (is_standard_store_insn(dl->ins.name)) update_store_insn_state(state, dloc, dl, src, dst); diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 1936822c73f2..6897bd275e59 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -70,6 +70,9 @@ void pr_debug_type_name(Dwarf_Die *die, enum type_state_k= ind kind) case TSR_KIND_CANARY: pr_info(" stack canary\n"); return; + case TSR_KIND_GLOBAL_ADDR: + pr_info(" global address\n"); + return; case TSR_KIND_TYPE: default: break; @@ -609,7 +612,8 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, stack->kind =3D kind; stack->imm_value =3D imm_value; =20 - if (kind =3D=3D TSR_KIND_POINTER || kind =3D=3D TSR_KIND_CONST) { + if (kind =3D=3D TSR_KIND_POINTER || kind =3D=3D TSR_KIND_CONST || + kind =3D=3D TSR_KIND_GLOBAL_ADDR) { stack->compound =3D false; return; } @@ -1365,6 +1369,25 @@ static enum type_match_result check_matching_type(st= ruct type_state *state, if (offset < 0 && reg !=3D state->stack_reg && reg !=3D dloc->fbreg) goto check_kernel; } + + if (state->regs[reg].kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + u64 var_addr =3D state->regs[reg].imm_value + offset; + int var_offset; + + pr_debug_dtp("global addr"); + + /* + * The register holds the address of a global variable. Try to + * find the variable by the address and get its type. + */ + if (get_global_var_type(cu_die, dloc, dloc->ip, var_addr, + &var_offset, type_die)) { + dloc->type_offset =3D var_offset; + return PERF_TMR_OK; + } + /* No need to retry global variables */ + return PERF_TMR_BAIL_OUT; + } check_non_register: if (reg =3D=3D dloc->fbreg || reg =3D=3D state->stack_reg) { struct type_state_stack *stack; diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index 02d5602c5e20..885d441e3768 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -37,6 +37,7 @@ enum type_state_kind { TSR_KIND_PERCPU_POINTER, TSR_KIND_POINTER, TSR_KIND_CANARY, + TSR_KIND_GLOBAL_ADDR, }; =20 /** --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4163548572; Tue, 8 Sep 2026 13:06:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872785; cv=none; b=js/SY8LDgXf53F8/TDDPzlGTSsf1TvkAU0ziemQh/3EqeoDy+VEiTQafh+XUyb1W6aIIo5y/1Xxrs9aiWWwD1uzZQRXLD7tCBCriGBuoSu4NItyTpdZYnF5ZDxAdXCQpVLp+rQVwkR5vq9LgykoFbsi9tvFoY9oku0yiQsxYTT0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872785; c=relaxed/simple; bh=EHVD5fqPR9gI1/IWrXrCmVkZK0PlrrQmg7nTwXcFqlc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YS2+dHMLTJnR7pmHxcXLcUDh2AfzSv1YKCpGW4/1LGXnyQ4M5KWV1dUpQPkHUkWBqNPPmOOpxhHRtOBFpKAzZpF9W5UKxENX0dAEhWPH1OukWF9DIBbbcxdSM1OY9RncOzcwapXgjKJF6s4CBPzI/5xUzrRya3UBE7iymXBzIkc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPLc4bK8zYQv3L; Tue, 8 Sep 2026 21:05:28 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 2556340574; Tue, 8 Sep 2026 21:06:20 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with UTF8SMTPA id _Ch0CgBHurdFCKBqUhjWBA--.26443S3; Tue, 08 Sep 2026 21:06:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 25/26] perf annotate-arm64: Support per-cpu variable access tracking Date: Tue, 8 Sep 2026 13:06:06 +0000 Message-Id: <4cebb0f4d2db4d66c4ec19c4c007d6761e5aad8e.1788872630.git.wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgBHurdFCKBqUhjWBA--.26443S3 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr15KrWDAF15Cr4ftw4UCFg_yoWxWFyfp3 95KryUW34ktrsrWws3tFW5XryF9393Ja4Ik34Y9w1avr1Igr1UG397KrW5tF4UGFnay3W7 tr9xtrZrXrnFkaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV W0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0 oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x0262 8vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IY c2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s 026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF 0xvE2Ix0cI8IcVAFwI0_Ar0_tr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26rxl6s0DMIIF0x vE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWxJVW8Jr1lIxAIcVC2z280 aVCY1x0267AKxVW0oVCq3bIYCTnIWIevJa73UjIFyTuYvjTRLSdqDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to handle per-cpu variable addressing. On arm64, per-cpu variables are accessed by adding a per-cpu offset (typically from the '__per_cpu_offset' array) to the address of a global variable or a structure field with '__percpu' modifier (e.g., 's32 __percpu *counters' in struct percpu_counter). This results in instruction patterns like: ldr x0, [x6, x5] // Pattern A: direct load per-cpu instance add x0, x6, x5 // Pattern B: compute per-cpu address where x6 holds the per-cpu offset retrieved from: adrp x4, add x4, x4, #offset // x4 =3D &__per_cpu_offset ldr x6, [x4, w0, sxtw #3] // x6 =3D __per_cpu_offset[cpu] and x5 is one of the following: case 1: global variable adrp x5, add x5, x5, #offset // x5 =3D &global_var case 2: '__percpu' field embedded in a structure ldr x5, [x25, #32] // x5 =3D &percpu_field To handle such cases: 1. Identify per-cpu base initialization: Detect 'adrp + ldr' pairs that resolve to the '__per_cpu_offset' symbol and mark the destination register as TSR_KIND_PERCPU_BASE. 2. Propagate type information: During subsequent 'ldr' or 'add' instructions, if one register is TSR_KIND_PERCPU_BASE, attempt to resolve the type from the other register. A real-world example is shown below: ffff8000808f2d28 : ffff8000808f2d38: adrp x2, ffff800082033000 ffff8000808f2d3c: add x5, x2, #0x3f8 // x5 =3D &__per_cpu_offs= et ffff8000808f2d44: adrp x2, ffff800081f73000 ffff8000808f2d48: add x2, x2, #0x6b8 // x2 =3D &cpu_pcc_subspa= ce_idx ffff8000808f2d6c: ldr x5, [x5, w0, sxtw #3] // x5 =3D __per_cpu_offse= t[cpu] * ffff8000808f2d80: ldr w23, [x5, x2] // per_cpu_var(cpu_pcc_su= bspace_idx) Before this commit, the tracker could not link x5 back to a per-cpu context, resulting in an incorrect data type resolution: adrp [10] global addr=3D0xffff800082033000 -> reg2 add [14] global 0x3f8(reg2) -> reg5 adrp [1c] global addr=3D0xffff800081f73000 -> reg2 add [20] global 0x6b8(reg2) -> reg2 ldr [44] global (reg5, reg0) -> reg5 type=3D'long unsigned int[]' size=3D= 0x1000 chk [58] reg5 offset=3D0 ok=3D1 kind=3D1 (long unsigned int[]) : Good! found by insn track: 0(reg5, reg2) type-offset=3D0 final result: type=3D'long unsigned int' size=3D0x8 After this commit, the tracker correctly identifies the per-cpu flow and resolves the actual variable type: ldr [44] global (reg5, reg0) -> reg5 percpu base chk [58] reg5 offset=3D0 ok=3D1 kind=3D2 percpu var : retry chk [58] reg2 offset=3D0 ok=3D1 kind=3D7 global addr : Good! found by insn track: 0(reg5, reg2) type-offset=3D0 final result: type=3D'int' size=3D0x4 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 47 ++++++++++++++++++- tools/perf/util/annotate-data.c | 22 ++++++++- 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 9daf95905545..33fef3d15378 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -12,6 +12,7 @@ #include "../disasm.h" #include "../annotate-data.h" #include "../debug.h" +#include "../dso.h" #include "../map.h" #include "../symbol.h" =20 @@ -627,13 +628,23 @@ static int propagate_load_reg_state(struct type_state= *state, u64 ip =3D dloc->ms->sym->start + dl->al.offset; u64 addr =3D src_tsr->imm_value + reg_offset; int offset; + u8 kind; + const char *var_name =3D NULL; + + /* it might be per-cpu offset */ + if (dso__kernel(map__dso(dloc->ms->map)) && + get_global_var_info(dloc, addr, &var_name, &offset) && + !strcmp(var_name, "__per_cpu_offset")) + kind =3D TSR_KIND_PERCPU_BASE; + else + kind =3D TSR_KIND_TYPE; =20 if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, &type_die) || !die_get_member_type(&type_die, offset, &type_die)) return -1; =20 tsr->type =3D type_die; - tsr->kind =3D TSR_KIND_TYPE; + tsr->kind =3D kind; tsr->offset =3D 0; tsr->imm_value =3D 0; tsr->ok =3D true; @@ -649,6 +660,12 @@ static int propagate_load_reg_state(struct type_state = *state, return 0; } =20 + /* + * If src_tsr->kind is TSR_KIND_PERCPU_BASE, treat it as an array. + * No special handling is needed here; just fall through to retry + * and resolve the type from the second register. + */ + /* Or try another register if any */ if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2 && !(src->extend_type || src->shift_type)) { @@ -949,6 +966,34 @@ static void update_add_insn_state(struct type_state *s= tate, return; } =20 + if (src_tsr.kind =3D=3D TSR_KIND_PERCPU_BASE) { + int reg2; + + if (!src->multi_regs) { + invalidate_reg_state(tsr); + return; + } + + reg2 =3D (sreg =3D=3D src->reg1) ? src->reg2 : src->reg1; + + if (!has_reg_type(state, reg2) || !state->regs[reg2].ok) { + invalidate_reg_state(tsr); + return; + } + + /* Treat percpu as array: inherit type from reg2 */ + tsr->type =3D state->regs[reg2].type; + tsr->kind =3D state->regs[reg2].kind; + tsr->offset =3D state->regs[reg2].offset; + tsr->imm_value =3D state->regs[reg2].imm_value; + tsr->ok =3D state->regs[reg2].ok; + + pr_debug_dtp("add [%x] percpu (reg%d, reg%d) -> reg%d", + insn_offset, src->reg1, src->reg2, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + try_other_reg: /* Try another register if any */ if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2 && diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 6897bd275e59..eb6a592cda84 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -1339,11 +1339,31 @@ static enum type_match_result check_matching_type(s= truct type_state *state, } =20 if (state->regs[reg].kind =3D=3D TSR_KIND_PERCPU_BASE) { - u64 var_addr =3D (s64) offset; + u64 var_addr; int var_offset; =20 pr_debug_dtp("percpu var"); =20 + if (arch__is_arm64(dloc->arch)) { + int reg2; + + if (!retry || !dloc->op->multi_regs || + dloc->op->reg1 =3D=3D dloc->op->reg2 || + dloc->op->extend_type || dloc->op->shift_type) + return PERF_TMR_BAIL_OUT; + + reg2 =3D dloc->op->reg2; + if (!has_reg_type(state, reg2) || !state->regs[reg2].ok) + return PERF_TMR_NO_TYPE; + + pr_debug_dtp(" : retry\n"); + retry =3D false; + reg =3D reg2; + goto again; + } + + var_addr =3D (s64) offset; + if (dloc->op->multi_regs) { int reg2 =3D dloc->op->reg2; =20 --=20 2.34.1 From nobody Fri Sep 25 21:40:23 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE84555409D; Tue, 8 Sep 2026 13:06:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hfPMb16yJzKHN5m; Tue, 8 Sep 2026 21:06:19 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 39B934058F; Tue, 8 Sep 2026 21:06:20 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with UTF8SMTPA id _Ch0CgBHurdFCKBqUhjWBA--.26443S4; Tue, 08 Sep 2026 21:06:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 26/26] perf annotate-arm64: Support 'mrs' instruction to track 'current' pointer Date: Tue, 8 Sep 2026 13:06:07 +0000 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _Ch0CgBHurdFCKBqUhjWBA--.26443S4 X-Coremail-Antispam: 1UD129KBjvJXoW3JrW3KFW3JFW3JrW5Kr48WFg_yoW7Xr4fpa yDC345Wr4kJr42ganxXFWxZr93Wws7W34Uur90qwsayFW7Kr1fKa1ktFW2ya15Jrykuw13 GrWUKr4DWw4IvFJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQmb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUXw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV W0oVCq3wA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0 oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x0262 8vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl42xK82IY c2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s 026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF 0xvE2Ix0cI8IcVAFwI0_Ar0_tr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26rxl6s0DMIIF0x vE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWxJVW8Jr1lIxAIcVC2z280 aVCY1x0267AKxVW0oVCq3bIYCTnIWIevJa73UjIFyTuYvjTRlg4TDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to handle the 'mrs' instruction, enabling the tracking of the 'current' task pointer in the kernel. On arm64, the kernel uses the 'sp_el0' system register to store the address of the currently executing 'struct task_struct'. This is typically accessed via the 'get_current()' inline function, resulting in the instruction 'mrs xN, sp_el0'. To resolve the data type of the target register, first verify the access is to 'sp_el0' within a kernel DSO. Then, locate the 'get_current()' inline function's DWARF Die at the current PC and extract its return type (which should be 'struct task_struct*'). A real-world example is shown below: ffff8000800deee8 : ffff8000800deef0: mrs x0, sp_el0 // x0 =3D current * ffff8000800deef4: ldr w1, [x0, #44] Before this commit, the type flow starts with no information: chk [c] reg0 offset=3D0x2c ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker identifies the 'current' pointer from the system register: mrs [8] sp_el0 -> reg0 type=3D'struct task_struct*' chk [c] reg0 offset=3D0x2c ok=3D1 kind=3D1 (struct task_struct*) : Good! found by insn track: 0x2c(reg0) type-offset=3D0x2c final result: type=3D'struct task_struct' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 73 ++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 33fef3d15378..d4b8c8d57dd7 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include "../dso.h" #include "../map.h" #include "../symbol.h" +#include "../strbuf.h" =20 struct arch_arm64 { struct arch arch; @@ -1037,6 +1039,71 @@ static void update_adrp_insn_state(struct type_state= *state, insn_offset, tsr->imm_value, dreg); } =20 +static void update_mrs_insn_state(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die *cu_die, + struct disasm_line *dl, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + Dwarf_Die type_die; + u32 insn_offset =3D dl->al.offset; + int dreg =3D dst->reg1; + Dwarf_Die func_die; + Dwarf_Attribute attr; + u64 ip, pc; + struct strbuf sb; + char *type_name; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + + /* Handle case difference: LLVM (SP_EL0) vs objdump (sp_el0) */ + if (!dso__kernel(map__dso(dloc->ms->map)) || + strcasecmp(dl->ops.source.raw, "sp_el0")) { + invalidate_reg_state(tsr); + return; + } + + ip =3D dloc->ms->sym->start + dl->al.offset; + pc =3D map__rip_2objdump(dloc->ms->map, ip); + + /* + * Find the inline function 'get_current()' Dwarf_Die and obtain its + * return value data type, which should be 'struct task_struct*'. + */ + if (!die_find_inlinefunc(cu_die, pc, &func_die) || + !die_compare_name(&func_die, "get_current") || + !dwarf_attr_integrate(&func_die, DW_AT_type, &attr) || + !dwarf_formref_die(&attr, &type_die)) { + invalidate_reg_state(tsr); + return; + } + + strbuf_init(&sb, 32); + die_get_typename_from_type(&type_die, &sb); + type_name =3D strbuf_detach(&sb, NULL); + + if (!type_name || strcmp(type_name, "struct task_struct*")) { + invalidate_reg_state(tsr); + goto out_free; + } + + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->imm_value =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("mrs [%x] sp_el0 -> reg%d", insn_offset, dreg); + pr_debug_type_name(&type_die, tsr->kind); + +out_free: + free(type_name); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -1103,7 +1170,7 @@ static void update_insn_state_arm64(struct type_state= *state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && !dst->mem_ref && - strcmp(dl->ins.name, "adrp") && + strcmp(dl->ins.name, "mrs") && strcmp(dl->ins.name, "adrp") && strcmp(dl->ins.name, "add") && strcmp(dl->ins.name, "mov") && !is_standard_load_insn(dl->ins.name)) { pr_debug_dtp("%s [%x] invalidate reg%d", @@ -1117,7 +1184,9 @@ static void update_insn_state_arm64(struct type_state= *state, return; } =20 - if (!strcmp(dl->ins.name, "adrp")) + if (!strcmp(dl->ins.name, "mrs")) + update_mrs_insn_state(state, dloc, cu_die, dl, dst); + else if (!strcmp(dl->ins.name, "adrp")) update_adrp_insn_state(state, dl, dst); else if (!strcmp(dl->ins.name, "add")) update_add_insn_state(state, dloc, dl, src, dst); --=20 2.34.1