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charset="utf-8" Correct a typo in vendor company name: "Analog Device" -> "Analog Devices". Signed-off-by: Marcelo Schmitt Reviewed-by: Andy Shevchenko --- Now find drivers/iio/ -type f | xargs grep -i "Analog Device " finds no leftover occurrence of such typo. Also, grep -nrIi drivers/iio/ -e "Analog Device" | wc -l and grep -nrIi drivers/iio/ -e "Analog Devices" | wc -l both count the same number of lines. drivers/iio/adc/Kconfig | 12 ++++++------ drivers/iio/dac/ad3552r.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 38e212a6f789..02f189e90c30 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -105,7 +105,7 @@ config AD4080 called ad4080. =20 config AD4130 - tristate "Analog Device AD4130 ADC Driver" + tristate "Analog Devices AD4130 ADC Driver" depends on SPI depends on GPIOLIB select IIO_BUFFER @@ -121,7 +121,7 @@ config AD4130 called ad4130. =20 config AD4134 - tristate "Analog Device AD4134 ADC Driver" + tristate "Analog Devices AD4134 ADC Driver" depends on SPI select REGMAP_SPI select CRC8 @@ -133,7 +133,7 @@ config AD4134 called ad4134_spi. =20 config AD4170_4 - tristate "Analog Device AD4170-4 ADC Driver" + tristate "Analog Devices AD4170-4 ADC Driver" depends on SPI select REGMAP_SPI select IIO_BUFFER @@ -164,7 +164,7 @@ config AD4691 called ad4691. =20 config AD4695 - tristate "Analog Device AD4695 ADC Driver" + tristate "Analog Devices AD4695 ADC Driver" depends on SPI select IIO_BUFFER select IIO_BUFFER_DMAENGINE @@ -179,7 +179,7 @@ config AD4695 called ad4695. =20 config AD4851 - tristate "Analog Device AD4851 DAS Driver" + tristate "Analog Devices AD4851 DAS Driver" depends on SPI depends on PWM select REGMAP_SPI @@ -347,7 +347,7 @@ config AD7380 called ad7380. =20 config AD7405 - tristate "Analog Device AD7405 ADC Driver" + tristate "Analog Devices AD7405 ADC Driver" depends on IIO_BACKEND help Say yes here to build support for Analog Devices AD7405, ADUM7701, diff --git a/drivers/iio/dac/ad3552r.c b/drivers/iio/dac/ad3552r.c index 16db94fef9d4..039af514adde 100644 --- a/drivers/iio/dac/ad3552r.c +++ b/drivers/iio/dac/ad3552r.c @@ -696,6 +696,6 @@ static struct spi_driver ad3552r_driver =3D { module_spi_driver(ad3552r_driver); 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charset="utf-8" Drop unused name space that somehow remained being included by the device driver. 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charset="utf-8" Add includes that were missing (according to include-what-you-use tool) to comply with include what is used principles. Namely, add bits.h for BIT and GENMASK, and time64.h for USEC_PER_SEC. Remove time.h which is covered by time64.h and iio/types.h which is covered by iio/iio.h. While updating the list, organize it to follow current IIO include list convention. Signed-off-by: Marcelo Schmitt Reviewed-by: Andy Shevchenko --- drivers/iio/adc/ad4134.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 70f80bf1825f..7a3b05aacc74 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -14,18 +15,18 @@ #include #include #include -#include -#include #include #include #include #include #include -#include +#include #include #include #include =20 +#include + #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC) =20 #define AD4134_REG_READ_MASK BIT(7) --=20 2.53.0 From nobody Sat Sep 26 09:19:13 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 497684AC17C; Wed, 2 Sep 2026 17:23:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Protect single-sample read operations from going wrong if two or more of them run concurrently. Serialize the data read operation so to avoid single-sample read requests disrupting each other. Signed-off-by: Marcelo Schmitt Reviewed-by: Andy Shevchenko --- drivers/iio/adc/ad4134.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 7a3b05aacc74..3460ecf4cafd 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -100,6 +102,11 @@ struct ad4134_state { unsigned long sys_clk_hz; struct gpio_desc *odr_gpio; int refin_mv; + /* + * Synchronize access to members the of driver state, and ensure + * atomicity of consecutive register access operations. + */ + struct mutex lock; /* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. @@ -257,6 +264,7 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, =20 switch (info) { case IIO_CHAN_INFO_RAW: + guard(mutex)(&st->lock); gpiod_set_value_cansleep(st->odr_gpio, 1); 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charset="utf-8" When AD4134 has its SPI CRC feature enabled, one extra byte (the CRC code) is sent through SPI for both ends to verify the integrity of data transfers. Though, when CRC is not enabled, SPI transfers can be shorter. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4134.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 3460ecf4cafd..7da6734d4609 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -102,6 +102,7 @@ struct ad4134_state { unsigned long sys_clk_hz; struct gpio_desc *odr_gpio; int refin_mv; + bool crc_en; /* * Synchronize access to members the of driver state, and ensure * atomicity of consecutive register access operations. @@ -160,7 +161,7 @@ static int ad4134_reg_write(void *context, unsigned int= reg, unsigned int val) struct spi_transfer xfer =3D { .tx_buf =3D st->tx_buf, .rx_buf =3D st->rx_buf, - .len =3D AD4134_SPI_MAX_XFER_LEN, + .len =3D st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2, }; int ret; =20 @@ -170,7 +171,7 @@ static int ad4134_reg_write(void *context, unsigned int= reg, unsigned int val) if (ret) return ret; =20 - if (st->rx_buf[2] !=3D st->tx_buf[2]) + if (st->crc_en && st->rx_buf[2] !=3D st->tx_buf[2]) dev_dbg(&st->spi->dev, "reg write CRC check failed\n"); =20 return 0; @@ -216,7 +217,7 @@ static int ad4134_register_read(struct ad4134_state *st= , unsigned int reg, struct spi_transfer xfer =3D { .tx_buf =3D st->tx_buf, .rx_buf =3D st->rx_buf, - .len =3D AD4134_SPI_MAX_XFER_LEN, + .len =3D st->crc_en ? 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charset="utf-8" AD4134 supports four types of programmable digital filters that allow users to choose between different output data rates and input bandwidths. Enable basic digital filter configuration by providing a way to select which filter type is activated for each channel. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4134.c | 80 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 7da6734d4609..a1474316e330 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -64,6 +64,9 @@ #define AD4134_PW_DOWN_CTRL_REG 0x13 #define AD4134_DEVICE_STATUS_REG 0x15 #define AD4134_ODR_VAL_INT_LSB_REG 0x16 +#define AD4134_CHAN_DIG_FILTER_SEL_REG 0x1E +#define AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(ch) (GENMASK(1, 0) << 2 * (ch)) + #define AD4134_CH3_OFFSET_MSB_REG 0x3E #define AD4134_AIN_OR_ERROR_REG 0x48 =20 @@ -81,12 +84,48 @@ #define AD4134_SPI_CRC_INIT_VALUE 0xA5 static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE]; =20 +enum ad4134_filter_type { + AD4134_WIDEBAND, + AD4134_SINC6, + AD4134_SINC3, + AD4134_SINC3_REJ60, +}; + +static const char * const ad4134_filt_names[] =3D { + [AD4134_WIDEBAND] =3D "wideband", + [AD4134_SINC6] =3D "sinc6", + [AD4134_SINC3] =3D "sinc3", + [AD4134_SINC3_REJ60] =3D "sinc3+rej60", +}; + +static int ad4134_get_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan); + +static int ad4134_set_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + unsigned int val); + +static const struct iio_enum ad4134_filter_type_enum =3D { + .items =3D ad4134_filt_names, + .num_items =3D ARRAY_SIZE(ad4134_filt_names), + .get =3D ad4134_get_filter_type, + .set =3D ad4134_set_filter_type, +}; + +static const struct iio_chan_spec_ext_info ad4134_filter_type_ext_info[] = =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ad4134_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, + &ad4134_filter_type_enum), + { } +}; + #define AD4134_CHANNEL(_index) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ .channel =3D (_index), \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .ext_info =3D ad4134_filter_type_ext_info, \ } =20 static const struct iio_chan_spec ad4134_chan_set[] =3D { @@ -116,6 +155,47 @@ struct ad4134_state { u8 tx_buf[AD4134_SPI_MAX_XFER_LEN]; }; =20 +static int ad4134_set_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + unsigned int val) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int mask, reg_val; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + + mask =3D AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(chan->channel); + reg_val =3D field_prep(mask, val); + return regmap_update_bits(st->regmap, AD4134_CHAN_DIG_FILTER_SEL_REG, + mask, reg_val); +} + +static int ad4134_get_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + enum ad4134_filter_type f_type; + unsigned int mask, reg_val; + int ret; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + ret =3D regmap_read(st->regmap, AD4134_CHAN_DIG_FILTER_SEL_REG, ®_val); + if (ret) + return ret; + + mask =3D AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(chan->channel); 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charset="utf-8" Enable users to run buffered data captures triggered by IIO trigger device. Add an IIO timestamp channel so each data scan is provided with measurement time information. Require single-read operations to be in IIO device direct access mode to prevent buffered and single-shot data captures to disrupt each other. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/Kconfig | 2 ++ drivers/iio/adc/ad4134.c | 59 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 02f189e90c30..584251a3f45c 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -125,6 +125,8 @@ config AD4134 depends on SPI select REGMAP_SPI select CRC8 + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER help Say yes here to build support for Analog Devices AD4134 SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index a1474316e330..0751b89dec8f 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -27,7 +27,10 @@ #include #include =20 +#include #include +#include +#include =20 #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC) =20 @@ -126,6 +129,14 @@ static const struct iio_chan_spec_ext_info ad4134_filt= er_type_ext_info[] =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ .ext_info =3D ad4134_filter_type_ext_info, \ + .scan_index =3D (_index), \ + .scan_type =3D { \ + .format =3D IIO_SCAN_FORMAT_SIGNED_INT, \ + .realbits =3D AD4134_CHAN_PRECISION_BITS, \ + .storagebits =3D 32, \ + .shift =3D 8, \ + .endianness =3D IIO_BE, \ + }, \ } =20 static const struct iio_chan_spec ad4134_chan_set[] =3D { @@ -133,6 +144,7 @@ static const struct iio_chan_spec ad4134_chan_set[] =3D= { AD4134_CHANNEL(1), AD4134_CHANNEL(2), AD4134_CHANNEL(3), + IIO_CHAN_SOFT_TIMESTAMP(4), }; =20 struct ad4134_state { @@ -151,7 +163,8 @@ struct ad4134_state { * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. */ - u8 rx_buf[AD4134_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN); + u32 scan[AD4134_NUM_CHANNELS] __aligned(IIO_DMA_MINALIGN); + u8 rx_buf[AD4134_SPI_MAX_XFER_LEN]; u8 tx_buf[AD4134_SPI_MAX_XFER_LEN]; }; =20 @@ -336,6 +349,36 @@ static const struct regmap_config ad4134_regmap_config= =3D { .max_register =3D AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)), }; =20 +static irqreturn_t ad4134_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int i =3D 0; + int ret; + + gpiod_set_value_cansleep(st->odr_gpio, 1); + fsleep(1); + gpiod_set_value_cansleep(st->odr_gpio, 0); + + for (unsigned int ch =3D 0; ch < iio_get_masklength(indio_dev); ch++) { + ret =3D spi_write_then_read(st->spi, NULL, 0, &st->scan[ch], + BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS)); + if (ret) + goto err_out; + + if (test_bit(ch, indio_dev->active_scan_mask)) + memcpy(&st->scan[i++], &st->scan[ch], sizeof(st->scan[ch])); + } + + iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), + pf->timestamp); + +err_out: + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; +} + static int ad4134_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -344,7 +387,11 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, int ret; =20 switch (info) { - case IIO_CHAN_INFO_RAW: + case IIO_CHAN_INFO_RAW: { + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + guard(mutex)(&st->lock); gpiod_set_value_cansleep(st->odr_gpio, 1); /* @@ -364,6 +411,7 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, return ret; =20 return IIO_VAL_INT; + } case IIO_CHAN_INFO_SCALE: *val =3D st->refin_mv; *val2 =3D AD4134_CHAN_PRECISION_BITS - 1; @@ -547,6 +595,13 @@ static int ad4134_probe(struct spi_device *spi) return dev_err_probe(dev, ret, "failed to setup minimum I/O mode\n"); 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charset="utf-8" Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations. Signed-off-by: Marcelo Schmitt --- .../bindings/iio/adc/adi,ad4134.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index ea6d7e026419..d843c02a394a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -131,6 +131,28 @@ properties: enum: [ free-running, gated ] default: gated =20 + adi,spi-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ] + description: | + This property indicates the SPI wiring configuration. + + When this property is omitted, it is assumed that the device is using + 'no-cs' wiring. When this property is present, it indicates that the + device is using one of the following wiring configurations: + + * no-cs: The datasheet calls this "minimum I/O mode". In this mode, = the CS + line is not used (tied to GND). + * 4-wire: Specifies a conventional SPI wiring configuration. + * one-channel-chain: In this mode, the DOUT0 line of one chip is con= nected + to DOUT2 of the next chip upstream in the chain. Only the data int= erface + of the upmost device in the stream is in direct connection with the + digital host. + * two-channel-chain: In this mode, the DOUT0 and DOUT1 lines of one = chip + are respectively connected to DOUT2 and DOUT3 of the next chip ups= tream + in the chain. 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charset="utf-8" AD4134 devices can be wired in a few different ways. So far, only minimum I/O mode was supported. While minimum I/O mode allows interfacing with AD4134 with a reduced number of wires, that wiring configuration is not optimal for high-throughput data acquisition. Extend AD4134 support to enable interfacing in SPI 4-wire configuration. Signed-off-by: Marcelo Schmitt --- The reason for the input multiplexer is enable both register access and multi-lane read. Before coming to the current solution, we tried the follow= ing configuration. +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface | | | | for register SCLK |<--------------------------| SCLK | | access CS |<--------------------------| CS | | SDI |<--------------------------| SDO | | SDO |---+ | | | | | | | | Data interface DOUT0 |---+---------------------->| SDI0 | | for ADC data DOUT1 |-------------------------->| SDI1 | | read back DOUT2 |-------------------------->| SDI2 | | DOUT3 |-------------------------->| SDI3 | | DCLK |<--------------------------| DCLK | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the da= ta line, causing register read to fail (always get 0xFF). Another solution wou= ld be to connect SDO to SDI0 and DOUT pins to SDI1, SDI2, SDI3, SDI4. That would = then require a special multi-lane mode. Please, see patch 13 for a better view of how the proposed setup works. drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4134.c | 162 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 158 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 584251a3f45c..ef77ee60df4e 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -127,6 +127,7 @@ config AD4134 select CRC8 select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select MULTIPLEXER help Say yes here to build support for Analog Devices AD4134 SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 0751b89dec8f..8453b44ef368 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include #include @@ -73,6 +75,9 @@ #define AD4134_CH3_OFFSET_MSB_REG 0x3E #define AD4134_AIN_OR_ERROR_REG 0x48 =20 +#define AD4134_SDO_INPUT 0 +#define AD4134_DOUT0_INPUT 1 + /* * AD4134 register map ends at address 0x48 and there is no register for * retrieving ADC sample data. Though, to make use of Linux regmap API both @@ -87,6 +92,17 @@ #define AD4134_SPI_CRC_INIT_VALUE 0xA5 static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE]; =20 +enum ad4134_spi_mode { + AD4134_SPI_MODE_NO_CS, /* datasheet calls this "minimum I/O mode" */ + AD4134_SPI_MODE_4_WIRE, +}; + +/* maps adi,spi-mode property value to enum */ +static const char * const ad4134_spi_modes[] =3D { + [AD4134_SPI_MODE_NO_CS] =3D "no-cs", + [AD4134_SPI_MODE_4_WIRE] =3D "4-wire", +}; + enum ad4134_filter_type { AD4134_WIDEBAND, AD4134_SINC6, @@ -154,11 +170,17 @@ struct ad4134_state { struct gpio_desc *odr_gpio; int refin_mv; bool crc_en; + enum ad4134_spi_mode spi_mode; + struct mux_state *mux_st[2]; /* * Synchronize access to members the of driver state, and ensure * atomicity of consecutive register access operations. */ struct mutex lock; + /* + * Ensure atomicity of access mode switch operations. + */ + struct mutex access_mode_lock; /* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. @@ -233,6 +255,73 @@ static const struct regmap_access_table ad4134_regmap_= wr_table =3D { .n_yes_ranges =3D ARRAY_SIZE(ad4134_regmap_wr_range), }; =20 +/* + * When AD4134 SDO and DOUT0 pins are multiplexed, this function changes t= he + * multiplexer state to route SDO to the SPI controller. + */ +static int ad4134_set_register_access(struct ad4134_state *st) +{ + int ret; + + guard(mutex)(&st->access_mode_lock); + st->spi->mode =3D SPI_MODE_0; + ret =3D spi_setup(st->spi); + if (ret) + return ret; + + ret =3D mux_state_deselect(st->mux_st[AD4134_DOUT0_INPUT]); + if (ret) + dev_err(&st->spi->dev, "error on DOUT0 deselect: %d\n", ret); + + ret =3D mux_state_try_select(st->mux_st[AD4134_SDO_INPUT]); + if (ret && ret !=3D -EBUSY) + return ret; + + return 0; +} + +/* + * When AD4134 SDO and DOUT0 pins are multiplexed, this function changes t= he + * multiplexer state to route DOUT0 to the SPI controller. On failure, fall + * back to routing SDO to the controller and return an errno. + */ +static int ad4134_set_sample_access(struct ad4134_state *st) +{ + int ret, ret2; + + guard(mutex)(&st->access_mode_lock); + ret =3D mux_state_deselect(st->mux_st[AD4134_SDO_INPUT]); + if (ret) + dev_err(&st->spi->dev, "error on SDO deselect: %d\n", ret); + + ret =3D mux_state_try_select(st->mux_st[AD4134_DOUT0_INPUT]); + if (ret) { + dev_err(&st->spi->dev, "error on DOUT0 select: %d\n", ret); + return mux_state_select(st->mux_st[AD4134_SDO_INPUT]); + } + + /* + * Data output on the DOUT lines is sampled on the falling edge + * (SPI mode 1). + */ + st->spi->mode =3D SPI_MODE_1; + ret =3D spi_setup(st->spi); + if (ret) { + dev_err(&st->spi->dev, "failed to setup SPI mode 1: %d\n", ret); + ret2 =3D mux_state_deselect(st->mux_st[AD4134_DOUT0_INPUT]); + if (ret2) + dev_err(&st->spi->dev, "error on DOUT0 deselect: %d\n", ret2); + + ret2 =3D mux_state_select(st->mux_st[AD4134_SDO_INPUT]); + if (ret2) + dev_err(&st->spi->dev, "error on SDO select: %d\n", ret2); + + return ret; + } + + return 0; +} + static int ad4134_calc_spi_crc(u8 inst, u8 data) { u8 buf[] =3D { inst, data }; @@ -334,9 +423,25 @@ static int ad4134_register_read(struct ad4134_state *s= t, unsigned int reg, static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *= val) { struct ad4134_state *st =3D context; + int ret, ret2; =20 - if (reg >=3D AD4134_CH_VREG(0)) - return ad4134_data_read(st, reg, val); + if (reg >=3D AD4134_CH_VREG(0)) { + if (st->spi_mode =3D=3D AD4134_SPI_MODE_4_WIRE) { + ret =3D ad4134_set_sample_access(st); + if (ret) + return ret; + } + + ret =3D ad4134_data_read(st, reg, val); + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_4_WIRE) { + ret2 =3D ad4134_set_register_access(st); + if (ret2) + dev_err(&st->spi->dev, "access mode error: %d\n", ret2); + } + + return ret; + } =20 return ad4134_register_read(st, reg, val); } @@ -379,6 +484,21 @@ static irqreturn_t ad4134_trigger_handler(int irq, voi= d *p) return IRQ_HANDLED; } =20 +static int ad4134_buffer_postenable(struct iio_dev *indio_dev) +{ + return ad4134_set_sample_access(iio_priv(indio_dev)); +} + +static int ad4134_buffer_predisable(struct iio_dev *indio_dev) +{ + return ad4134_set_register_access(iio_priv(indio_dev)); +} + +static const struct iio_buffer_setup_ops ad4134_buffer_setup_ops =3D { + .postenable =3D &ad4134_buffer_postenable, + .predisable =3D &ad4134_buffer_predisable, +}; + static int ad4134_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -590,10 +710,42 @@ static int ad4134_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->regmap), "failed to initialize regmap"); =20 - ret =3D ad4134_min_io_mode_setup(st); - if (ret) + ret =3D device_property_match_property_string(dev, "adi,spi-mode", + ad4134_spi_modes, + ARRAY_SIZE(ad4134_spi_modes)); + /* Default to "no-cs" mode if adi,spi-mode is not specified */ + if (ret =3D=3D -EINVAL) + st->spi_mode =3D AD4134_SPI_MODE_NO_CS; + else if (ret < 0) return dev_err_probe(dev, ret, - "failed to setup minimum I/O mode\n"); + "getting adi,spi-mode property failed\n"); + else + st->spi_mode =3D ret; + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_NO_CS) { + st->mux_st[AD4134_SDO_INPUT] =3D + devm_mux_state_get_optional_selected(dev, "reg_access"); + if (IS_ERR(st->mux_st[AD4134_SDO_INPUT])) + return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_SDO_INPUT]), + "failed to get reg_access mux-state\n"); + + ret =3D ad4134_min_io_mode_setup(st); + if (ret) + return dev_err_probe(dev, ret, + "failed to setup minimum I/O mode\n"); + } else { + st->mux_st[AD4134_SDO_INPUT] =3D devm_mux_state_get_selected(dev, "reg_a= ccess"); + if (IS_ERR(st->mux_st[AD4134_SDO_INPUT])) + return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_SDO_INPUT]), + "failed to get reg_access mux-state\n"); + + st->mux_st[AD4134_DOUT0_INPUT] =3D devm_mux_state_get(dev, "data_read"); + if (IS_ERR(st->mux_st[AD4134_DOUT0_INPUT])) + return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_DOUT0_INPUT]), + "failed to get data_read mux-state\n"); + + indio_dev->setup_ops =3D &ad4134_buffer_setup_ops; + } =20 ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, iio_pollfunc_store_time, --=20 2.53.0 From nobody Sat Sep 26 09:19:13 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C406F4AC162; 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charset="utf-8" Advenced setups may connect a PWM signal to AD4134 ODR pin for faster output data rates. Signed-off-by: Marcelo Schmitt Acked-by: Conor Dooley --- Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index d843c02a394a..34043f89730b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -104,6 +104,10 @@ properties: GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mo= de. maxItems: 1 =20 + pwms: + description: PWM signal connected to the ODR pin. + maxItems: 1 + adi,asrc-mode: $ref: /schemas/types.yaml#/definitions/string description: --=20 2.53.0 From nobody Sat Sep 26 09:19:13 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9BE4AC154; Wed, 2 Sep 2026 17:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788369933; cv=none; b=l0pNS+t5YgeeyEs16kJDNhYpQRJiAKVby2NCJMXiw9TRHqARVz3wr54STR4JQNTdlhKBRcOr2tonrQLdJDAfaaV32tEY3fWkblFVlqtQmADZW00b00NJH50Thq3aSv0VFiR4WpbpHmm5rdlFyiMAjF2EnezkGqhYihnHXsXm5U4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788369933; 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charset="utf-8" Add device tree example for AD4134 operation in 4-wire SPI mode with 4 lines to transfer data samples to the host controller. Signed-off-by: Marcelo Schmitt --- The reason for the input multiplexer is enable both register access and multi-lane read. Before coming to the current solution, we tried the follow= ing configuration. +-----------------------+ +-----------------+ | AD4134 | | SPI Controller | | | | | | SPI interface | | | | for register SCLK |<--------------------------| SCLK | | access CS |<--------------------------| CS | | SDI |<--------------------------| SDO | | SDO |---+ | | | | | | | | Data interface DOUT0 |---+---------------------->| SDI0 | | for ADC data DOUT1 |-------------------------->| SDI1 | | read back DOUT2 |-------------------------->| SDI2 | | DOUT3 |-------------------------->| SDI3 | | DCLK |<--------------------------| DCLK | ODR |<------------------+ +->| Offload Trigger | +-----------------------+ | | +-----------------+ | +--| PWM1 | +-------| PWM0 | +-------| GPIO | +-----------------+ Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the da= ta line, causing register read to fail (always get 0xFF). Another solution wou= ld be to connect SDO to SDI0 and DOUT pins to SDI1, SDI2, SDI3, SDI4. That would = then require a special multi-lane mode. Please, see patch 13 for a better view of how the proposed setup works. .../bindings/iio/adc/adi,ad4134.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml index 34043f89730b..6f0b4346426a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -214,4 +214,46 @@ examples: =20 }; }; + - | + #include + + ad4134_sdo_dout0_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&gpio0 100 GPIO_ACTIVE_HIGH>; + }; + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4134"; + reg =3D <0>; + + spi-max-frequency =3D <1000000>; + spi-rx-bus-width =3D <1>, <1>, <1>, <1>; /* 4 lanes of 1 bit e= ach */ + + pwms =3D <&ad4134_odr_generator 1 1000000 0>; + reset-gpios =3D <&gpio0 86 GPIO_ACTIVE_LOW>; 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charset="utf-8" Make use of SPI transfer offloading to speed up data capture, enabling data acquisition at faster sample rates (up to 1.496 MSPS). Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/Kconfig | 5 + drivers/iio/adc/ad4134.c | 379 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 375 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index ef77ee60df4e..369cc0659073 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -123,9 +123,14 @@ config AD4130 config AD4134 tristate "Analog Devices AD4134 ADC Driver" depends on SPI + depends on PWM select REGMAP_SPI + select SPI_OFFLOAD + select SPI_OFFLOAD_TRIGGER_PWM select CRC8 select IIO_BUFFER + select IIO_BUFFER_DMA + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER select MULTIPLEXER help diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c index 8453b44ef368..cf84d2b24417 100644 --- a/drivers/iio/adc/ad4134.c +++ b/drivers/iio/adc/ad4134.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -20,9 +21,12 @@ #include #include #include +#include #include #include #include +#include +#include #include #include #include @@ -30,11 +34,16 @@ #include =20 #include +#include +#include #include #include #include =20 #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC) +#define AD4134_DCLK_RISING_OFFSET_NS 8 +#define AD4134_MIN_ODR_FREQ_HZ 10 +#define AD4134_MAX_ODR_FREQ_HZ (1496 * HZ_PER_KHZ) =20 #define AD4134_REG_READ_MASK BIT(7) #define AD4134_SPI_MAX_XFER_LEN 3 @@ -65,6 +74,7 @@ #define AD4134_DIG_IF_CFG_REG 0x12 #define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0) #define AD4134_DATA_FORMAT_SINGLE_CH_MODE 0x0 +#define AD4134_DATA_FORMAT_QUAD_CH_PARALLEL 0x2 =20 #define AD4134_PW_DOWN_CTRL_REG 0x13 #define AD4134_DEVICE_STATUS_REG 0x15 @@ -117,6 +127,10 @@ static const char * const ad4134_filt_names[] =3D { [AD4134_SINC3_REJ60] =3D "sinc3+rej60", }; =20 +static const int ad4134_max_samp_freq_range_Hz[3] =3D { + AD4134_MIN_ODR_FREQ_HZ, 1, AD4134_MAX_ODR_FREQ_HZ, +}; + static int ad4134_get_filter_type(struct iio_dev *indio_dev, struct iio_chan_spec const *chan); =20 @@ -163,6 +177,39 @@ static const struct iio_chan_spec ad4134_chan_set[] = =3D { IIO_CHAN_SOFT_TIMESTAMP(4), }; =20 +/* + * Hardcoded 32-bit storagebits and CPU endianness because the currently + * available HDL only supports that configuration. + */ +#define AD4134_OFFLOAD_CHANNEL(_index) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (_index), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .ext_info =3D ad4134_filter_type_ext_info, \ + .scan_index =3D (_index), \ + .scan_type =3D { \ + .format =3D IIO_SCAN_FORMAT_SIGNED_INT, \ + .realbits =3D AD4134_CHAN_PRECISION_BITS, \ + .storagebits =3D 32, \ + .endianness =3D IIO_CPU, \ + }, \ +} + +/* + * It's not possible for software to record when offloaded SPI transfers r= un so + * no additional timestamp channel is added. + */ +static const struct iio_chan_spec ad4134_offload_chan_set[] =3D { + AD4134_OFFLOAD_CHANNEL(0), + AD4134_OFFLOAD_CHANNEL(1), + AD4134_OFFLOAD_CHANNEL(2), + AD4134_OFFLOAD_CHANNEL(3), +}; + struct ad4134_state { struct spi_device *spi; struct regmap *regmap; @@ -172,6 +219,14 @@ struct ad4134_state { bool crc_en; enum ad4134_spi_mode spi_mode; struct mux_state *mux_st[2]; + struct spi_transfer xfers; + struct spi_message msg; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger_config offload_trigger_config; + struct pwm_device *odr_pwm; + struct pwm_waveform odr_wf; + unsigned int odr_hz; /* * Synchronize access to members the of driver state, and ensure * atomicity of consecutive register access operations. @@ -454,6 +509,90 @@ static const struct regmap_config ad4134_regmap_config= =3D { .max_register =3D AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)), }; =20 +static int ad4134_update_conversion_rate(struct ad4134_state *st, + unsigned int freq_Hz) +{ + struct spi_offload_trigger_config config =3D st->offload_trigger_config; + struct pwm_waveform odr_wf =3D { }; + u64 offload_period_ns; + u64 offload_offset_ns; + u64 odr_high_time_ns; + unsigned int count; + u64 target =3D 10; + int ret; + + if (!in_range(freq_Hz, AD4134_MIN_ODR_FREQ_HZ, AD4134_MAX_ODR_FREQ_HZ)) + return -ERANGE; + + odr_wf.period_length_ns =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq_Hz); + /* + * Set the PWM duty cycle to keep ODR high for at least minimum required + * time. If the rounded PWM's value is less than the minimum required, + * increase the target value by 10 and attempt to round the waveform + * again, until the minimum (or try count limit) is reached. + */ + odr_high_time_ns =3D div64_ul(6ULL * NSEC_PER_SEC, st->sys_clk_hz); + count =3D 100; + do { + odr_wf.duty_length_ns =3D target; + ret =3D pwm_round_waveform_might_sleep(st->odr_pwm, &odr_wf); + if (ret) + return ret; + target +=3D 10; /* Increment by PWM duty cycle period */ + } while (count-- && odr_wf.duty_length_ns < odr_high_time_ns); + + /* Check the minimum ODR high time is met */ + if (odr_wf.duty_length_ns < odr_high_time_ns) + return -EDOM; + + if (odr_wf.period_length_ns < 2 * odr_high_time_ns) + return -EDOM; + + /* + * Configure SPI offload PWM trigger. + * For gated DCLK, the minimum required time between ODR rising edge + * and DCLK rising edge is the sum of ODR high time and ODR falling + * edge to DCLK rising edge time. Delay the offload trigger for at least + * that amount of time so the ADC sample data will be available when the + * SPI transfer begin. + * + * Use the same period as ODR PWM to avoid timing issues. + * Convert back from period to frequency for the SPI offload API. + */ + offload_period_ns =3D odr_wf.period_length_ns; + config.periodic.frequency_hz =3D DIV_ROUND_UP_ULL(HZ_PER_GHZ, offload_per= iod_ns); + offload_offset_ns =3D odr_high_time_ns + AD4134_DCLK_RISING_OFFSET_NS; + count =3D 100; + do { + config.periodic.offset_ns =3D offload_offset_ns; + ret =3D spi_offload_trigger_validate(st->offload_trigger, &config); + if (ret) + return ret; + + offload_offset_ns +=3D 10; + } while (count-- && config.periodic.offset_ns < odr_high_time_ns + + AD4134_DCLK_RISING_OFFSET_NS); + + /* Check the minimum ODR to DCLK delay is met */ + if (config.periodic.offset_ns < odr_high_time_ns + AD4134_DCLK_RISING_OFF= SET_NS) + return -EDOM; + + /* Check the PWM periods remain the same */ + offload_period_ns =3D DIV_ROUND_UP_ULL(HZ_PER_GHZ, config.periodic.freque= ncy_hz); + if (odr_wf.period_length_ns !=3D offload_period_ns) + return -EDOM; + + ret =3D pwm_set_waveform_might_sleep(st->odr_pwm, &odr_wf, false); + if (ret) + return ret; + + st->offload_trigger_config =3D config; + st->odr_wf =3D odr_wf; + st->odr_hz =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, odr_wf.period_length_ns); + + return 0; +} + static irqreturn_t ad4134_trigger_handler(int irq, void *p) { struct iio_poll_func *pf =3D p; @@ -537,6 +676,42 @@ static int ad4134_read_raw(struct iio_dev *indio_dev, *val2 =3D AD4134_CHAN_PRECISION_BITS - 1; =20 return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D st->odr_hz; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} +static int ad4134_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals =3D (int *)ad4134_max_samp_freq_range_Hz; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + default: + return -EINVAL; + } +} + +static int ad4134_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4134_update_conversion_rate(st, val); default: return -EINVAL; } @@ -588,6 +763,176 @@ static const struct iio_info ad4134_info =3D { .debugfs_reg_access =3D ad4134_debugfs_reg_access, }; =20 +static const struct iio_info ad4134_offload_info =3D { + .read_raw =3D ad4134_read_raw, + .read_avail =3D ad4134_read_avail, + .write_raw =3D ad4134_write_raw, + .debugfs_reg_access =3D ad4134_debugfs_reg_access, +}; + +static void ad4134_prepare_offload_msg(struct iio_dev *indio_dev) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + unsigned int base_len =3D roundup_pow_of_two(BITS_TO_BYTES(AD4134_CHAN_PR= ECISION_BITS)); + unsigned int bpw =3D AD4134_CHAN_PRECISION_BITS; + + st->xfers.cs_off =3D 1; + st->xfers.bits_per_word =3D bpw; + st->xfers.len =3D base_len * st->spi->num_rx_lanes; + if (st->spi->num_rx_lanes > 1) + st->xfers.multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + + st->xfers.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + + spi_message_init_with_transfers(&st->msg, &st->xfers, 1); +} + +static int ad4134_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + int ret, ret2; + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_4_WIRE) { + ret =3D ad4134_set_sample_access(st); + if (ret) + return ret; + } + + ad4134_prepare_offload_msg(indio_dev); + st->msg.offload =3D st->offload; + ret =3D spi_optimize_message(st->spi, &st->msg); + if (ret) + goto out_set_register_input; + + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &st->offload_trigger_config); + if (ret) + goto out_unoptimize; + + return 0; + +out_unoptimize: + spi_unoptimize_message(&st->msg); + +out_set_register_input: + ret2 =3D ad4134_set_register_access(st); + if (ret2) + dev_err(&st->spi->dev, "reg input select error: %d\n", ret2); + + return ret; +} + +static int ad4134_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + int ret =3D 0; + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + if (st->spi_mode =3D=3D AD4134_SPI_MODE_4_WIRE) + ret =3D ad4134_set_register_access(st); + + spi_unoptimize_message(&st->msg); + + return ret; +} + +static const struct iio_buffer_setup_ops ad4134_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4134_offload_buffer_postenable, + .predisable =3D &ad4134_offload_buffer_predisable, +}; + +static int ad4134_pwm_get(struct ad4134_state *st) +{ + struct device *dev =3D &st->spi->dev; + + st->odr_pwm =3D devm_pwm_get(dev, NULL); + if (IS_ERR(st->odr_pwm)) + return dev_err_probe(dev, PTR_ERR(st->odr_pwm), + "failed to get ODR PWM\n"); + + return 0; +} + +static const struct spi_offload_config ad4134_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + +static int ad4134_offload_buffer_setup(struct iio_dev *indio_dev, struct s= pi_device *spi) +{ + struct ad4134_state *st =3D iio_priv(indio_dev); + struct device *dev =3D &spi->dev; + struct dma_chan *rx_dma; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + + st->offload_trigger_config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + +/* The chip converts and outputs all 4 channels on each sample request */ +static const unsigned long ad4134_scan_masks[] =3D { + GENMASK(3, 0), + 0 +}; + +static int ad4134_offload_setup(struct iio_dev *indio_dev, struct ad4134_s= tate *st) +{ + struct device *dev =3D &st->spi->dev; + int ret; + + ret =3D ad4134_pwm_get(st); + if (ret) + return ret; + + ret =3D ad4134_offload_buffer_setup(indio_dev, st->spi); + if (ret) + return ret; + + /* + * Start with a sampling rate slower than 374 kSPS because that is the + * maximum rate supported with wideband filter (default on power up). + */ + st->odr_hz =3D 250 * HZ_PER_KHZ; + ret =3D ad4134_update_conversion_rate(st, st->odr_hz); + if (ret) + return dev_err_probe(dev, ret, "failed to set sampling freq\n"); + + indio_dev->setup_ops =3D &ad4134_offload_buffer_setup_ops; + indio_dev->available_scan_masks =3D ad4134_scan_masks; + + switch (st->spi->num_rx_lanes) { + case 1: + return regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG, + AD4134_DIF_IF_CFG_FORMAT_MASK, + FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK, + AD4134_DATA_FORMAT_SINGLE_CH_MODE)); + case 4: + return regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG, + AD4134_DIF_IF_CFG_FORMAT_MASK, + FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK, + AD4134_DATA_FORMAT_QUAD_CH_PARALLEL)); + default: + return dev_err_probe(dev, -EINVAL, + "unsupported number of spi-rx-bus-width elements: %d\n", + st->spi->num_rx_lanes); + } + + return 0; +} + static const char * const ad4143_required_regulators[] =3D { "avdd5", "dvdd5", "iovdd", }; @@ -681,10 +1026,7 @@ static int ad4134_probe(struct spi_device *spi) st->spi =3D spi; =20 indio_dev->name =3D "ad4134"; - indio_dev->channels =3D ad4134_chan_set; - indio_dev->num_channels =3D ARRAY_SIZE(ad4134_chan_set); indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->info =3D &ad4134_info; =20 ret =3D ad4134_regulator_setup(st); if (ret) @@ -747,12 +1089,30 @@ static int ad4134_probe(struct spi_device *spi) indio_dev->setup_ops =3D &ad4134_buffer_setup_ops; } =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - ad4134_trigger_handler, - NULL); - if (ret) - return ret; + st->offload =3D devm_spi_offload_get(dev, spi, &ad4134_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + /* Fall back to low speed usage when no SPI offload is available. */ + if (ret =3D=3D -ENODEV) { + indio_dev->info =3D &ad4134_info; + indio_dev->channels =3D ad4134_chan_set; + indio_dev->num_channels =3D ARRAY_SIZE(ad4134_chan_set); + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4134_trigger_handler, + NULL); + if (ret) + return ret; + } else if (ret) { + return dev_err_probe(dev, ret, "failed to get offload\n"); + } else { + indio_dev->info =3D &ad4134_offload_info; + indio_dev->channels =3D ad4134_offload_chan_set; + indio_dev->num_channels =3D ARRAY_SIZE(ad4134_offload_chan_set); + ret =3D ad4134_offload_setup(indio_dev, st); + if (ret) + return dev_err_probe(dev, ret, + "failed to setup SPI offload\n"); + } =20 /* Bump precision to 24-bit */ ret =3D regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG, @@ -798,3 +1158,4 @@ module_spi_driver(ad4134_driver); MODULE_AUTHOR("Marcelo Schmitt "); MODULE_DESCRIPTION("Analog Devices AD4134 SPI driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); --=20 2.53.0 From nobody Sat Sep 26 09:19:13 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5482E4A8A38; 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Signed-off-by: Marcelo Schmitt --- Documentation/iio/ad4134.rst | 128 +++++++++++++++++++++++++++++++++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 130 insertions(+) create mode 100644 Documentation/iio/ad4134.rst diff --git a/Documentation/iio/ad4134.rst b/Documentation/iio/ad4134.rst new file mode 100644 index 000000000000..4e93d670e2db --- /dev/null +++ b/Documentation/iio/ad4134.rst @@ -0,0 +1,128 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD4134 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Device driver for Analog Devices Inc. AD4134 and similar ADCs. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* `AD4134 `_ +* `AD7134 `_ + +Wiring connections +------------------ + +AD4134 and similar ADCs can operate in a few different wiring configuratio= ns. +Because AD4134 also supports control modes other than through SPI protocol, +the following pins must be statically set for all of the wiring modes desc= ribed +below. + ++----------------------------+----------------------+--------------------+ +| Pin Function | Level | Description | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| PIN/SPI | High | SPI control mode | ++----------------------------+----------------------+--------------------+ +| MODE | Low | ASRC slave mode | ++----------------------------+----------------------+--------------------+ +| DEC0/DCLKI | Low | DCLK input | ++----------------------------+----------------------+--------------------+ +| DEC1/DCLKMODE | Low | Gated DCLK | ++----------------------------+----------------------+--------------------+ + +Minimum I/O mode +^^^^^^^^^^^^^^^^ + +The minimum I/O mode wiring allows AD4134 register and data access with the +conventional set of SPI bus lines. In this mode, the peripheral CS pin mus= t be +tied to GND. A possible connection schema that sets AD4134 digital interfa= ce for +minimum I/O mode is:: + + +------------+ +-------------+ + | AD4134 | | SPI | + | | | Controller | + | DCLK |<--+ | | + | SCLK |<--+---- | SCLK | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | ODR |<--------| GPIO | + | CS |----+ | | + +------------+ | +-------------+ + V + GND + +Set ``adi,spi-mode =3D "no-cs"`` in device tree to indicate the device is +connected in minimum I/O wiring configuration. + +SPI 4-wire mode - single lane +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The conventional SPI 4-wire configuration except a multiplexer is used to +select between SDO (for register data) and DOUT0 (for ADC sample data).:: + + +-----------------------+ +-----------------+ + | AD4134 | | SPI Controller | + | | | | + | SPI interface | | | + | for register SCLK |<------------------------| SCLK | + | access CS |<------------------------| CS | + | SDI |<------------------------| SDO | + | SDO |------->|=C2=AF=C2=AF=C2=AF=C2=AF\ | = | + | Data interface | |MUX >--------->| SDI | + | for ADC sample DOUT0 |------->|____/ | | + | data read | ^ | | + | | +--------------| GPIO | + | DCLK |<------------------------| DCLK | + | ODR |<----------------+ +->| Offload Trigger | + +-----------------------+ | | +-----------------+ + | +--| PWM1 | + +-------| PWM0 | + +-------| GPIO | + +-----------------+ + +Set ``adi,spi-mode =3D "4-wire"`` in device tree to indicate the device is +connected in SPI 4-wire configuration. + +For SPI offload operation, a PWM is connected to the ADC ODR pin. The ``pw= ms`` +firmware property specifies the PWM that is connected to the ADC. The SPI +offload will have a ``trigger-sources`` property to indicate the SPI offlo= ad +(PWM) trigger source. + +To achieve high sample rates while meeting ADC timing requirements, an off= set +must be added between the rising edges of PWM0 and PWM1 to delay the SPI +transfer until ADC sample data is available. This requires a specialized P= WM +controller that can provide such an offset. The `AD4134-FMC HDL project`_= , for +example, can be configured to sample AD4134 at high speed sample rates. + +.. _AD4134-FMC HDL project: https://analogdevicesinc.github.io/hdl/project= s/ad4134_fmc/index.html + +SPI 4-wire mode - multi-lane +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Maximum througput rate can be achieved by reading 4 input lines simultaneo= usly.:: + + +-----------------------+ +-----------------+ + | AD4134 | | SPI Controller | + | | | | + | SPI interface | | | + | for register SCLK |<------------------------| SCLK | + | access CS |<------------------------| CS | + | SDI |<------------------------| SDO | + | SDO |------->|=C2=AF=C2=AF=C2=AF=C2=AF\ | = | + | Data interface | |MUX >--------->| SDI0 | + | for ADC sample DOUT0 |------->|____/<--------- | GPIO | + | data read DOUT1 |------------------------>| SDI1 | + | DOUT2 |------------------------>| SDI2 | + | DOUT3 |------------------------>| SDI3 | + | DCLK |<------------------------| DCLK | + | ODR |<----------------+ +->| Offload Trigger | + +-----------------------+ | | +-----------------+ + | +--| PWM1 | + +-------| PWM0 | + +-------| GPIO | + +-----------------+ + +Each of SDI0 to SDI3 connect to a different SPI controller deserializer +(``spi-rx-bus-width =3D <1>, <1>, <1>, <1>``). diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index b02b879b053a..e4ec8a05dded 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers ad4000 ad4030 ad4062 + ad4134 ad4691 ad4695 ad7191 diff --git a/MAINTAINERS b/MAINTAINERS index f3be900e5b9d..7b972c1f9833 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1514,6 +1514,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +F: Documentation/iio/ad4134.rst F: drivers/iio/adc/ad4134.c =20 ANALOG DEVICES INC AD4170-4 DRIVER --=20 2.53.0