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Sun, 30 Aug 2026 16:18:31 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v10 01/13] iommu/arm-smmu-v3: Init the vmid_map ida before the stream table setup Date: Sun, 30 Aug 2026 16:18:02 -0700 Message-ID: <8c1b88d58b26b97be0b2c9c78a254aaccfbd0baf.1788130528.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|IA0PPFAF4999BF6:EE_ X-MS-Office365-Filtering-Correlation-Id: dfbc572a-fd47-4bb3-7c3b-08df06ed0785 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|23010399003|82310400026|36860700016|56012099006|10067099003|11063799006|6133799003|18002099003|22082099003; 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charset="utf-8" The vmid_map ida is initialized after the stream table setup, along with the devres action that destroys it. An upcoming change will reserve the crashed kernel's in-use VMIDs in this ida, from a kdump kernel's stream table adoption that runs in place of the regular setup and returns early. Move the ida_init() and its devres registration to the entry of the whole function, so that the ida is ready by the time the adoption path runs. Reviewed-by: Jason Gunthorpe Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5732f3ba0122d..1c4322d87d8df 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4584,17 +4584,17 @@ static int arm_smmu_init_strtab(struct arm_smmu_dev= ice *smmu) { int ret; =20 + ida_init(&smmu->vmid_map); + ret =3D devm_add_action_or_reset(smmu->dev, arm_smmu_destroy_vmid_map, + &smmu->vmid_map); + if (ret) + return ret; + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) ret =3D arm_smmu_init_strtab_2lvl(smmu); else ret =3D arm_smmu_init_strtab_linear(smmu); - if (ret) - return ret; - - ida_init(&smmu->vmid_map); - - return devm_add_action_or_reset(smmu->dev, arm_smmu_destroy_vmid_map, - &smmu->vmid_map); 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charset="utf-8" An ASID tags the TLB entries within one SMMU, so two instances can use the same ASID without ever aliasing each other. Yet the driver allocates them out of a single global xarray, which makes the instances share a space that the hardware keeps apart, and lets one instance exhaust the IDs of another. That global space is a leftover from the BTM support that shared ASIDs with the CPU. Now ARM_SMMU_FEAT_BTM is never set, nothing looks a domain up by its ASID, and a domain is pinned to one SMMU at the attach. Give each SMMU its own asid_map, mirroring the per-SMMU vmid_map, and clean it up with devres, so that both of the ID maps get the same lifetime as the SMMU device structure that holds them. An upcoming change will need this, to reserve the crashed kernel's in-use ASIDs in the new map during a kdump kernel's stream table adoption. Note that arm_smmu_asid_lock stays global, as it serializes the STE and CD updates against any ASID change rather than guarding the map itself, which does its own locking. Giving each SMMU its own lock looks possible now, but that would touch every attach path and belongs to a separate change. Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 6 +++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 +++++++++++++++--- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 50f8321e979ce..fd6f489cfedf2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -952,6 +952,7 @@ struct arm_smmu_device { #define ARM_SMMU_MAX_VMIDS (1 << 16) unsigned int vmid_bits; struct ida vmid_map; + struct xarray asid_map; =20 unsigned int ssid_bits; unsigned int sid_bits; @@ -1128,7 +1129,6 @@ to_smmu_nested_domain(struct iommu_domain *dom) return container_of(dom, struct arm_smmu_nested_domain, domain); } =20 -extern struct xarray arm_smmu_asid_xa; extern struct mutex arm_smmu_asid_lock; =20 struct arm_smmu_domain *arm_smmu_domain_alloc(void); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 0a429c64fbf3e..2433ec61f5336 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -301,7 +301,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domai= n *domain) * reused, and if there is a race then it just suffers harmless * unnecessary invalidation. */ - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); + xa_erase(&smmu_domain->smmu->asid_map, smmu_domain->cd.asid); =20 /* * Actual free is defered to the SRCU callback @@ -341,7 +341,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, smmu_domain->stage =3D ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu =3D smmu; =20 - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, + ret =3D xa_alloc(&smmu->asid_map, &asid, smmu_domain, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); if (ret) goto err_free; @@ -355,7 +355,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, return &smmu_domain->domain; =20 err_asid: - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); + xa_erase(&smmu_domain->smmu->asid_map, smmu_domain->cd.asid); err_free: arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1c4322d87d8df..c1d04f84870f6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -85,7 +85,6 @@ struct arm_smmu_option_prop { const char *prop; }; =20 -DEFINE_XARRAY_ALLOC1(arm_smmu_asid_xa); DEFINE_MUTEX(arm_smmu_asid_lock); =20 static struct arm_smmu_option_prop arm_smmu_options[] =3D { @@ -2839,7 +2838,7 @@ static void arm_smmu_domain_free_paging(struct iommu_= domain *domain) if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); + xa_erase(&smmu->asid_map, smmu_domain->cd.asid); mutex_unlock(&arm_smmu_asid_lock); } else { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; @@ -2859,7 +2858,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_device *smmu, =20 /* Prevent SVA from modifying the ASID until it is written to the CD */ mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, + ret =3D xa_alloc(&smmu->asid_map, &asid, smmu_domain, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); cd->asid =3D (u16)asid; mutex_unlock(&arm_smmu_asid_lock); @@ -4483,6 +4482,13 @@ static void arm_smmu_destroy_vmid_map(void *data) ida_destroy(ida); } =20 +static void arm_smmu_destroy_asid_map(void *data) +{ + struct xarray *xa =3D data; + + xa_destroy(xa); +} + static int arm_smmu_init_queues(struct arm_smmu_device *smmu) { int ret; @@ -4590,6 +4596,12 @@ static int arm_smmu_init_strtab(struct arm_smmu_devi= ce *smmu) if (ret) return ret; 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charset="utf-8" The driver programs and enables the event queue unconditionally, while the PRI queue has an ARM_SMMU_FEAT_PRI gating each of its touch points. Yet a kdump kernel wants to leave both of the queues alone, which would take an is_kdump_kernel() test at every one of those places. Add an ARM_SMMU_FEAT_EVTQ that the probe always sets, as the event queue is architecturally mandatory, and gate the queue's allocation, its interrupt and its CR0 and IRQ_CTRL enables on it, so that a later change can turn the queue off in a single place. No functional change intended. Suggested-by: Jason Gunthorpe Suggested-by: Robin Murphy Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen Acked-by: Kiryl Shutsemau (Meta) Reviewed-by: Jason Gunthorpe Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 79 +++++++++++++-------- 2 files changed, 52 insertions(+), 28 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index fd6f489cfedf2..75e768b3d66d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -927,6 +927,7 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_BBML2 (1 << 24) #define ARM_SMMU_FEAT_HAFT (1 << 25) #define ARM_SMMU_FEAT_DS (1 << 26) +#define ARM_SMMU_FEAT_EVTQ (1 << 27) u32 features; =20 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c1d04f84870f6..c776fdd43325d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2349,7 +2349,8 @@ static irqreturn_t arm_smmu_combined_irq_thread(int i= rq, void *dev) { struct arm_smmu_device *smmu =3D dev; =20 - arm_smmu_evtq_thread(irq, dev); + if (smmu->features & ARM_SMMU_FEAT_EVTQ) + arm_smmu_evtq_thread(irq, dev); if (smmu->features & ARM_SMMU_FEAT_PRI) arm_smmu_priq_thread(irq, dev); =20 @@ -2358,7 +2359,12 @@ static irqreturn_t arm_smmu_combined_irq_thread(int = irq, void *dev) =20 static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) { - arm_smmu_gerror_handler(irq, dev); + struct arm_smmu_device *smmu =3D dev; + irqreturn_t ret =3D arm_smmu_gerror_handler(irq, dev); + + /* Without either queue, the thread would have nothing to drain */ + if (!(smmu->features & (ARM_SMMU_FEAT_EVTQ | ARM_SMMU_FEAT_PRI))) + return ret; return IRQ_WAKE_THREAD; } =20 @@ -4505,11 +4511,14 @@ static int arm_smmu_init_queues(struct arm_smmu_dev= ice *smmu) return ret; =20 /* evtq */ - ret =3D arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, - ARM_SMMU_EVTQ_PROD, ARM_SMMU_EVTQ_CONS, - EVTQ_ENT_DWORDS, "evtq"); - if (ret) - return ret; + if (smmu->features & ARM_SMMU_FEAT_EVTQ) { + ret =3D arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, + ARM_SMMU_EVTQ_PROD, + ARM_SMMU_EVTQ_CONS, + EVTQ_ENT_DWORDS, "evtq"); + if (ret) + return ret; + } =20 if ((smmu->features & ARM_SMMU_FEAT_SVA) && (smmu->features & ARM_SMMU_FEAT_STALLS)) { @@ -4729,16 +4738,20 @@ static void arm_smmu_setup_unique_irqs(struct arm_s= mmu_device *smmu) arm_smmu_setup_msis(smmu); =20 /* Request interrupt lines */ - irq =3D smmu->evtq.q.irq; - if (irq) { - ret =3D devm_request_threaded_irq(smmu->dev, irq, NULL, - arm_smmu_evtq_thread, - IRQF_ONESHOT, - "arm-smmu-v3-evtq", smmu); - if (ret < 0) - dev_warn(smmu->dev, "failed to enable evtq irq\n"); - } else { - dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); + if (smmu->features & ARM_SMMU_FEAT_EVTQ) { + irq =3D smmu->evtq.q.irq; + if (irq) { + ret =3D devm_request_threaded_irq(smmu->dev, irq, NULL, + arm_smmu_evtq_thread, + IRQF_ONESHOT, + "arm-smmu-v3-evtq", smmu); + if (ret < 0) + dev_warn(smmu->dev, + "failed to enable evtq irq\n"); + } else { + dev_warn(smmu->dev, + "no evtq irq - events will not be reported!\n"); + } } =20 irq =3D smmu->gerr_irq; @@ -4771,7 +4784,7 @@ static void arm_smmu_setup_unique_irqs(struct arm_smm= u_device *smmu) static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) { int ret, irq; - u32 irqen_flags =3D IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; + u32 irqen_flags =3D IRQ_CTRL_GERROR_IRQEN; =20 /* Disable IRQs first */ ret =3D arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, @@ -4797,6 +4810,8 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device= *smmu) } else arm_smmu_setup_unique_irqs(smmu); =20 + if (smmu->features & ARM_SMMU_FEAT_EVTQ) + irqen_flags |=3D IRQ_CTRL_EVTQ_IRQEN; if (smmu->features & ARM_SMMU_FEAT_PRI) irqen_flags |=3D IRQ_CTRL_PRIQ_IRQEN; =20 @@ -4915,16 +4930,21 @@ static int arm_smmu_device_reset(struct arm_smmu_de= vice *smmu) smmu, arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NSNH_ALL)); =20 /* Event queue */ - writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); - writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); - - enables |=3D CR0_EVTQEN; - ret =3D arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, - ARM_SMMU_CR0ACK); - if (ret) { - dev_err(smmu->dev, "failed to enable event queue\n"); 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charset="utf-8" A kdump kernel cannot use either queue. The crashed kernel's CDs and page tables might be corrupted, so events would spam the EVTQ, and there is no way to serve the page requests that would arrive at the PRIQ. The reset routine still enables both of the queues and then masks the two enable bits back out, having already programmed the queue bases and taken the interrupts of both. Clear ARM_SMMU_FEAT_EVTQ and ARM_SMMU_FEAT_PRI in the probe instead, so all of the queue handling, i.e. the interrupts, the IRQ_CTRL bits and the CR0 enables, keeps away from a kdump kernel via the feature tests. Both queues also go unallocated now, as the two allocations test the same features. Each of them is sized from the maxima that IDR1 advertises, so up to 4MB apiece on a 4K-page kernel, which a kdump kernel would otherwise pay for every SMMU instance out of a small crashkernel reservation. The IOPF workqueue of the event queue stays allocated here, as untangling it from the SVA and the stall features takes a pair of changes carried by the PRI series. It costs a struct and a workqueue rather than the megabytes that the two queues take, so leave it to that series. Suggested-by: Kevin Tian Suggested-by: Jason Gunthorpe Suggested-by: Kiryl Shutsemau (Meta) Suggested-by: Will Deacon Link: https://lore.kernel.org/all/amiBagGKn-Aym1DK@willie-the-truck/ Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen Acked-by: Kiryl Shutsemau (Meta) Reviewed-by: Jason Gunthorpe Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c776fdd43325d..7b9ef1ad1f688 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4981,9 +4981,6 @@ static int arm_smmu_device_reset(struct arm_smmu_devi= ce *smmu) return ret; } =20 - if (is_kdump_kernel()) - enables &=3D ~(CR0_EVTQEN | CR0_PRIQEN); - /* Enable the SMMU interface */ enables |=3D CR0_SMMUEN; ret =3D arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, @@ -5296,6 +5293,15 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) if (arm_smmu_sva_supported(smmu)) smmu->features |=3D ARM_SMMU_FEAT_SVA; =20 + /* + * A kdump kernel wants neither queue: the crashed kernel's CDs and page + * tables might be corrupted, spamming events, and page requests cannot + * be served. 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charset="utf-8" When booting after a kexec, both the kdump adoption and also the in-flight SMMUv3 live-update restoration built on the Kexec Handover (KHO) framework need to parse the previous kernel's STRTAB_BASE/STRTAB_BASE_CFG registers, in order to retain the stream table translating any in-flight DMAs. Add a new arm-smmu-v3-kexec.c holding the common read-only helpers: - arm_smmu_kexec_parse_strtab_2lvl() - arm_smmu_kexec_parse_strtab_linear() - arm_smmu_kexec_check_strtab_l1_desc() These helpers only validate the previous kernel's values against this very kernel's own limits, taking no ownership of the tables: a kdump kernel will adopt the tables via memremaps, while a live-update kernel will claim them using the KHO restore API. Build this new file under a hidden ARM_SMMU_V3_KEXEC Kconfig symbol, which is, for now, merely a CRASH_DUMP. Then, the coming live-update series would need to append its own user to this symbol, e.g. "|| IOMMU_LIVEUPDATE". Suggested-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/Kconfig | 4 + drivers/iommu/arm/arm-smmu-v3/Makefile | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 11 ++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c | 166 ++++++++++++++++++ 4 files changed, 182 insertions(+) create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index 5fac08b89deea..04b05d49abf76 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -109,6 +109,10 @@ config ARM_SMMU_V3_IOMMUFD =20 Say Y here if you are doing development and testing on this feature. =20 +# Common helpers for a kexec'd kernel, e.g. kdump adoption and live update +config ARM_SMMU_V3_KEXEC + def_bool CRASH_DUMP + config ARM_SMMU_V3_KUNIT_TEST tristate "KUnit tests for arm-smmu-v3 driver" if !KUNIT_ALL_TESTS depends on KUNIT diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm= -smmu-v3/Makefile index 493a659cc66bb..89a27de8dd2f0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/Makefile +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_ARM_SMMU_V3) +=3D arm_smmu_v3.o arm_smmu_v3-y :=3D arm-smmu-v3.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) +=3D arm-smmu-v3-iommufd.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) +=3D arm-smmu-v3-sva.o +arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_KEXEC) +=3D arm-smmu-v3-kexec.o arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) +=3D tegra241-cmdqv.o =20 obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) +=3D arm-smmu-v3-test.o diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 75e768b3d66d8..dd71d758defd3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1251,6 +1251,17 @@ tegra241_cmdqv_probe(struct arm_smmu_device *smmu) } #endif /* CONFIG_TEGRA241_CMDQV */ =20 +#ifdef CONFIG_ARM_SMMU_V3_KEXEC +int arm_smmu_kexec_parse_strtab_2lvl(struct arm_smmu_device *smmu, u32 cfg= _reg, + phys_addr_t base, u32 *num_l1_ents); +int arm_smmu_kexec_parse_strtab_linear(struct arm_smmu_device *smmu, + u32 cfg_reg, phys_addr_t base, + u32 *num_ents); +int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, + u64 l1_desc, u32 idx, + phys_addr_t *l2_base); +#endif /* CONFIG_ARM_SMMU_V3_KEXEC */ + struct arm_vsmmu { struct iommufd_viommu core; struct arm_smmu_device *smmu; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c new file mode 100644 index 0000000000000..b15e23df11b6d --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common helpers for a kexec'd kernel to parse, validate, and walk throug= h the + * previous kernel's SMMU table structures, shared by the kdump adoption a= nd a + * future live-update restoration. + * + * All of the helpers are read-only against the previous kernel's structur= es: a + * table that is not yet mapped by this kernel gets a transient memremap d= uring + * a walk, followed by an immediate memunmap. They never allocate memory o= r take + * ownership of the previous kernel's tables; the callers make those decis= ions. + */ + +#include + +#include "arm-smmu-v3.h" + +/** + * arm_smmu_kexec_parse_strtab_2lvl() - Validate a 2-level stream table + * @smmu: SMMU device of this kernel + * @cfg_reg: STRTAB_BASE_CFG register value set by the previous kernel + * @base: stream table base address extracted from the STRTAB_BASE register + * @num_l1_ents: pointer to return the number of L1 entries + * + * Validate the 2-level stream table geometry in @cfg_reg and @base's alig= nment + * against this kernel's hardware limits. + * + * Return: 0 on success with @num_l1_ents set, or -EINVAL on a bad geometry + */ +int arm_smmu_kexec_parse_strtab_2lvl(struct arm_smmu_device *smmu, u32 cfg= _reg, + phys_addr_t base, u32 *num_l1_ents) +{ + u32 log2size =3D FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, cfg_reg); + u32 split =3D FIELD_GET(STRTAB_BASE_CFG_SPLIT, cfg_reg); + u32 num_ents; + size_t size; + + if (log2size < split || log2size > smmu->sid_bits) { + dev_err(smmu->dev, "log2size %u out of range [%u, %u]\n", + log2size, split, smmu->sid_bits); + return -EINVAL; + } + if (split !=3D STRTAB_SPLIT) { + dev_err(smmu->dev, + "unsupported STRTAB_SPLIT %u (expected %u)\n", split, + STRTAB_SPLIT); + return -EINVAL; + } + + /* + * Bound the entry count before the shift, as a log2size wider than what + * this kernel itself supports would overflow it. + */ + if (log2size - split > ilog2(STRTAB_MAX_L1_ENTRIES)) { + dev_err(smmu->dev, "l1 entries 2^%u exceeds max %u\n", + log2size - split, STRTAB_MAX_L1_ENTRIES); + return -EINVAL; + } + + num_ents =3D 1U << (log2size - split); + + size =3D num_ents * sizeof(struct arm_smmu_strtab_l1); + /* + * According to spec (6.3.24), HW aligns the base down to the L1 table + * size, i.e. min 64 bytes, so an unaligned base would make this kernel + * read another table. + */ + if (!IS_ALIGNED(base, size)) { + dev_err(smmu->dev, "unaligned l1 stream table base %pa\n", + &base); + return -EINVAL; + } + + *num_l1_ents =3D num_ents; + return 0; +} + +/** + * arm_smmu_kexec_parse_strtab_linear() - Validate a linear stream table + * @smmu: SMMU device of this kernel + * @cfg_reg: STRTAB_BASE_CFG register value set by the previous kernel + * @base: stream table base address extracted from the STRTAB_BASE register + * @num_ents: pointer to return the number of STEs + * + * Validate the linear stream table geometry in @cfg_reg and @base's align= ment + * against this kernel's own limits. + * + * Return: 0 on success with @num_ents set, or -EINVAL on a bad geometry + */ +int arm_smmu_kexec_parse_strtab_linear(struct arm_smmu_device *smmu, + u32 cfg_reg, phys_addr_t base, + u32 *num_ents) +{ + u32 log2size =3D FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, cfg_reg); + unsigned int max_log2size =3D smmu->sid_bits; + size_t size; + + /* Cap the size at what this kernel itself would have allocated */ + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) + max_log2size =3D min_t( + unsigned int, max_log2size, + ilog2(STRTAB_MAX_L1_ENTRIES * STRTAB_NUM_L2_STES)); + + /* num_ents is limited to a u32, so cap log2size at 31 */ + max_log2size =3D min(max_log2size, 31U); + if (log2size > max_log2size) { + dev_err(smmu->dev, "unsupported log2size %u (> %u)\n", log2size, + max_log2size); + return -EINVAL; + } + + size =3D (1U << log2size) * sizeof(struct arm_smmu_ste); + /* + * According to spec (6.3.24), HW aligns the base down to the table size + * and ignores the low bits, so an unaligned base would make this kernel + * read a different table. + */ + if (!IS_ALIGNED(base, size)) { + dev_err(smmu->dev, "unaligned stream table base %pa\n", &base); + return -EINVAL; + } + + *num_ents =3D 1U << log2size; + return 0; +} + +/** + * arm_smmu_kexec_check_strtab_l1_desc() - Check one stream table L1 descr= iptor + * @smmu: SMMU device of this kernel + * @l1_desc: L1 descriptor value from the previous kernel's stream table + * @idx: index of the L1 descriptor, for diagnostics + * @l2_base: pointer to return the L2 table's physical address + * + * Return: 1 if the descriptor is unused, 0 if it is valid with @l2_base s= et, or + * -EINVAL if it is malformed + */ +int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, + u64 l1_desc, u32 idx, + phys_addr_t *l2_base) +{ + phys_addr_t base =3D l1_desc & STRTAB_L1_DESC_L2PTR_MASK; + u32 span =3D FIELD_GET(STRTAB_L1_DESC_SPAN, l1_desc); + + /* L1STD.L2Ptr is invalid */ + if (!span) + return 1; + + if (span !=3D STRTAB_SPLIT + 1) { + dev_err(smmu->dev, "L1[%u] unsupported span %u (vs %u)\n", idx, + span, STRTAB_SPLIT + 1); + return -EINVAL; + } + + /* + * A valid descriptor never carries a null pointer. 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charset="utf-8" When transitioning to a kdump kernel, the primary kernel might have crashed while endpoint devices were actively bus-mastering DMA. Currently, the SMMU driver aggressively resets the hardware during probe by clearing CR0_SMMUEN and setting the Global Bypass Attribute (GBPA) to ABORT. In a kdump scenario, this aggressive reset is highly destructive: a) If GBPA is set to ABORT, in-flight DMA will be aborted, generating fatal PCIe AER or SErrors that may panic the kdump kernel b) If GBPA is set to BYPASS, in-flight DMA targeting some IOVAs will bypass the SMMU and corrupt the physical memory at those 1:1 mapped IOVAs. To safely absorb in-flight DMAs, a kdump kernel will have to leave SMMUEN= =3D1 intact and avoid modifying STRTAB_BASE, allowing HW to continue translating in-flight DMAs reusing the crashed kernel's page tables until the endpoint device drivers probe and quiesce their respective hardware. However, the ARM SMMUv3 architecture specification states that updating the SMMU_STRTAB_BASE register while SMMUEN =3D=3D 1 is UNPREDICTABLE or ignored. This leaves a kdump kernel no choice but to adopt the stream table from the crashed kernel. Introduce ARM_SMMU_OPT_KDUMP_ADOPT and adopt functions memremapping all the stream tables extracted from STRTAB_BASE and STRTAB_BASE_CFG. Add them in a new arm-smmu-v3-kdump.c, which is only built when CONFIG_CRASH_DUMP=3Dy. Note that the adoption of the crashed kernel's stream table follows certain strict rules, since the old stream table might be compromised. Thus, apply some basic validations against the values read from the registers. If tests fail, it means the stream table cannot be trusted, so toss it entirely. To avoid OOM due to a potentially corrupted stream table, the memremap for l2 tables is done lazily on the kdump kernel's demand. The new option will be set in a following change, once the device reset and the RMR setup are reworked not to overwrite the adopted stream table, and the crashed kernel's in-use ASIDs and VMIDs are reserved. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/Makefile | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 21 ++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c | 229 ++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 +- 4 files changed, 269 insertions(+), 3 deletions(-) create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm= -smmu-v3/Makefile index 89a27de8dd2f0..2bc52473d960e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/Makefile +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile @@ -4,6 +4,7 @@ arm_smmu_v3-y :=3D arm-smmu-v3.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) +=3D arm-smmu-v3-iommufd.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) +=3D arm-smmu-v3-sva.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_KEXEC) +=3D arm-smmu-v3-kexec.o +arm_smmu_v3-$(CONFIG_CRASH_DUMP) +=3D arm-smmu-v3-kdump.o arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) +=3D tegra241-cmdqv.o =20 obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) +=3D arm-smmu-v3-test.o diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index dd71d758defd3..41d7a907b9ba2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -935,6 +935,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +#define ARM_SMMU_OPT_KDUMP_ADOPT (1 << 5) u32 options; =20 struct arm_smmu_cmdq cmdq; @@ -1262,6 +1263,26 @@ int arm_smmu_kexec_check_strtab_l1_desc(struct arm_s= mmu_device *smmu, phys_addr_t *l2_base); #endif /* CONFIG_ARM_SMMU_V3_KEXEC */ =20 +#ifdef CONFIG_CRASH_DUMP +int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu); +int arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_smmu_device *smmu, + u32 sid, phys_addr_t base, u32 span, + struct arm_smmu_strtab_l2 **l2table); +#else /* CONFIG_CRASH_DUMP */ +static inline int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu) +{ + return -EOPNOTSUPP; +} + +static inline int +arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_smmu_device *smmu, u32 = sid, + phys_addr_t base, u32 span, + struct arm_smmu_strtab_l2 **l2table) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_CRASH_DUMP */ + struct arm_vsmmu { struct iommufd_viommu core; struct arm_smmu_device *smmu; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c new file mode 100644 index 0000000000000..a074d59ce3445 --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Implementation of the kdump stream table adoption for ARM SMMUv3 + * + * When the crashed kernel left the SMMU enabled with in-flight DMAs, the = kdump + * kernel adopts the crashed kernel's stream tables, instead of doing a re= gular + * reset, to keep in-flight DMAs translating until the endpoint device dri= vers + * re-probe and quiesce their devices. + * + * Note: + * - Adoption only starts on an SMMU that the crashed kernel left enabled= , as a + * disabled SMMU (CR0_SMMUEN=3D0) could hold meaningless register value= s. + * - Values read from the crashed kernel's registers get structural valid= ation + * only (format, size, span, alignment, and ID range); the physical add= resses + * are not vetted, as the kdump kernel has no record of which pages hel= d the + * tables. + * - A structural inconsistency at adoption time tosses the entire adopti= on and + * makes the SMMU fall back to a full reset blocking in-flight DMAs. + * - L2 stream tables are adopted lazily at master-inserting time, to bou= nd the + * peak memory use against a corrupted L1 table; any lazy L2 adoption f= ailure + * rejects that device alone, as its blast radius is bounded to the bus. + * - Only a coherent SMMU (ARM_SMMU_FEAT_COHERENCY) is supported, as the = stream + * table adoption is done by memremap with MEMREMAP_WB, which is verifi= ed on + * the real hardware. Callers of these functions are responsible for ga= ting + * ARM_SMMU_FEAT_COHERENCY once during the probe. + */ + +#define dev_fmt(fmt) "kdump: " fmt + +#include +#include + +#include "arm-smmu-v3.h" + +int arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_smmu_device *smmu, + u32 sid, phys_addr_t base, u32 span, + struct arm_smmu_strtab_l2 **l2table) +{ + struct arm_smmu_strtab_l2 *table; + size_t size; + + /* + * Retest the span in case the L1 descriptor has been overwritten since + * the adopt. Reject this master's insert; panic or SMMU-disable would + * either lose the vmcore or cascade aborts. Do not try to fix it, as it + * would break all other SIDs in the same bus (PCI case). The corruption + * blast radius is already bounded to that bus range. + */ + if (span !=3D STRTAB_SPLIT + 1) { + dev_err(smmu->dev, + "L1[%u] span %u changed since adopt (was %u)\n", + arm_smmu_strtab_l1_idx(sid), span, STRTAB_SPLIT + 1); + return -EINVAL; + } + + size =3D (1UL << (span - 1)) * sizeof(struct arm_smmu_ste); + + /* Same live-corruption check as the span; reject an overwritten base */ + if (!base || !IS_ALIGNED(base, size)) { + dev_err(smmu->dev, "L1[%u] bad l2 table base %pa\n", + arm_smmu_strtab_l1_idx(sid), &base); + return -EINVAL; + } + + /* + * This L2 table is mapped lazily per master; devres frees it at unbind, + * as with the dmam_alloc_coherent() used for a fresh L2. + */ + table =3D devm_memremap(smmu->dev, base, size, MEMREMAP_WB); + if (IS_ERR(table)) { + dev_err(smmu->dev, + "failed to adopt l2 stream table for SID %u\n", sid); + return PTR_ERR(table); + } + + *l2table =3D table; + return 0; +} + +static int arm_smmu_kdump_adopt_strtab_2lvl(struct arm_smmu_device *smmu, + u32 cfg_reg, phys_addr_t base) +{ + struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; + u32 num_l1_ents; + size_t size; + int ret, i; + + ret =3D arm_smmu_kexec_parse_strtab_2lvl(smmu, cfg_reg, base, + &num_l1_ents); + if (ret) + return ret; + + cfg->l2.num_l1_ents =3D num_l1_ents; + + size =3D num_l1_ents * sizeof(struct arm_smmu_strtab_l1); + cfg->l2.l1tab =3D memremap(base, size, MEMREMAP_WB); + if (!cfg->l2.l1tab) + return -ENOMEM; + + cfg->l2.l2ptrs =3D + kcalloc(num_l1_ents, sizeof(*cfg->l2.l2ptrs), GFP_KERNEL); + if (!cfg->l2.l2ptrs) + return -ENOMEM; + + for (i =3D 0; i < num_l1_ents; i++) { + u64 l2ptr =3D le64_to_cpu(cfg->l2.l1tab[i].l2ptr); + phys_addr_t l2_base; + + ret =3D arm_smmu_kexec_check_strtab_l1_desc(smmu, l2ptr, i, + &l2_base); + if (ret < 0) + return ret; + + /* + * If the crashed kernel's l1 descriptors are deeply corrupted, + * blindly memremapping every l2 table here could lead to OOM. + * + * Defer the l2 memremap to arm_smmu_init_l2_strtab(), so peak + * memory is bounded by the kdump kernel's actual demand. + */ + } + + return 0; +} + +static int arm_smmu_kdump_adopt_strtab_linear(struct arm_smmu_device *smmu, + u32 cfg_reg, phys_addr_t base) +{ + struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; + u32 num_ents; + size_t size; + int ret; + + ret =3D arm_smmu_kexec_parse_strtab_linear(smmu, cfg_reg, base, + &num_ents); + if (ret) + return ret; + + /* + * We might end up with a num_ents !=3D sid_bits, which is fine, since the + * ARM_SMMU_OPT_KDUMP_ADOPT case bypasses arm_smmu_write_strtab(). + */ + cfg->linear.num_ents =3D num_ents; + + size =3D num_ents * sizeof(struct arm_smmu_ste); + cfg->linear.table =3D memremap(base, size, MEMREMAP_WB); + if (!cfg->linear.table) + return -ENOMEM; + return 0; +} + +static void arm_smmu_kdump_adopt_cleanup(void *data) +{ + struct arm_smmu_device *smmu =3D data; + struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + kfree(cfg->l2.l2ptrs); + if (cfg->l2.l1tab) + memunmap(cfg->l2.l1tab); + } else { + if (cfg->linear.table) + memunmap(cfg->linear.table); + } +} + +int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu) +{ + u32 cfg_reg =3D readl_relaxed(smmu->base + ARM_SMMU_STRTAB_BASE_CFG); + u64 base_reg =3D readq_relaxed(smmu->base + ARM_SMMU_STRTAB_BASE); + bool was_2lvl =3D smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB; + phys_addr_t base =3D base_reg & STRTAB_BASE_ADDR_MASK; + u32 fmt =3D FIELD_GET(STRTAB_BASE_CFG_FMT, cfg_reg); + int ret; + + dev_dbg(smmu->dev, "adopting crashed kernel's stream table\n"); + + if (fmt =3D=3D STRTAB_BASE_CFG_FMT_2LVL) { + /* + * Both kernels run on the same hardware, so it's impossible for + * kdump kernel to see the support for linear stream table only. + */ + if (WARN_ON(!(smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB))) + ret =3D -EINVAL; + else + ret =3D arm_smmu_kdump_adopt_strtab_2lvl(smmu, cfg_reg, + base); + } else if (fmt =3D=3D STRTAB_BASE_CFG_FMT_LINEAR) { + /* + * The kdump kernel need not match the crashed kernel. An older + * crashed kernel that predates two-level stream table support + * may have used a linear table on 2-level-capable hardware, so + * enforce the same format here to match the adopted table. + */ + ret =3D arm_smmu_kdump_adopt_strtab_linear(smmu, cfg_reg, base); + if (!ret) + smmu->features &=3D ~ARM_SMMU_FEAT_2_LVL_STRTAB; + } else { + dev_err(smmu->dev, "invalid STRTAB format %u\n", fmt); + ret =3D -EINVAL; + } + + if (ret) { + arm_smmu_kdump_adopt_cleanup(smmu); + goto err; + } + + ret =3D devm_add_action_or_reset(smmu->dev, arm_smmu_kdump_adopt_cleanup, + smmu); + /* devm_add_action_or_reset ran the cleanup upon failure */ + if (ret) { + dev_warn(smmu->dev, "failed to set up cleanup action\n"); + goto err; + } + + return 0; + +err: + dev_warn(smmu->dev, "falling back to full reset\n"); + /* + * Undo the linear adoption's clearing of FEAT_2_LVL_STRTAB so that the + * full-reset fallback uses the hardware-supported format. + */ + if (was_2lvl) + smmu->features |=3D ARM_SMMU_FEAT_2_LVL_STRTAB; + memset(&smmu->strtab_cfg, 0, sizeof(smmu->strtab_cfg)); + smmu->options &=3D ~ARM_SMMU_OPT_KDUMP_ADOPT; + return ret; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 7b9ef1ad1f688..971b12517941f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2002,11 +2002,23 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_= device *smmu, u32 sid) dma_addr_t l2ptr_dma; struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; struct arm_smmu_strtab_l2 **l2table; + u32 l1_idx =3D arm_smmu_strtab_l1_idx(sid); =20 - l2table =3D &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)]; + l2table =3D &cfg->l2.l2ptrs[l1_idx]; if (*l2table) return 0; =20 + /* Deferred adoption of the crashed kernel's L2 table */ + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + u64 l2ptr =3D le64_to_cpu(cfg->l2.l1tab[l1_idx].l2ptr); + phys_addr_t base =3D l2ptr & STRTAB_L1_DESC_L2PTR_MASK; + u32 span =3D FIELD_GET(STRTAB_L1_DESC_SPAN, l2ptr); + + if (span) + return arm_smmu_kdump_adopt_deferred_l2_strtab( + smmu, sid, base, span, l2table); + } + *l2table =3D dmam_alloc_coherent(smmu->dev, sizeof(**l2table), &l2ptr_dma, GFP_KERNEL); if (!*l2table) { @@ -2018,8 +2030,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_de= vice *smmu, u32 sid) =20 arm_smmu_init_initial_stes((*l2table)->stes, ARRAY_SIZE((*l2table)->stes)); - arm_smmu_write_strtab_l1_desc(&cfg->l2.l1tab[arm_smmu_strtab_l1_idx(sid)], - l2ptr_dma); + arm_smmu_write_strtab_l1_desc(&cfg->l2.l1tab[l1_idx], l2ptr_dma); return 0; } =20 @@ -4611,6 +4622,10 @@ static int arm_smmu_init_strtab(struct arm_smmu_devi= ce *smmu) if (ret) return ret; =20 + if ((smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) && + !arm_smmu_kdump_adopt_strtab(smmu)) + return 0; + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) ret =3D arm_smmu_init_strtab_2lvl(smmu); else --=20 2.43.0 From nobody Sat Sep 26 20:27:43 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010009.outbound.protection.outlook.com [52.101.193.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 872253590A9 for ; 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charset="utf-8" An S1 STE points to a CD table that both of the kexec flavors decode: the kdump adoption scans the CD table to reserve all the in-use ASIDs, and the live-update restoration claims the CD table via the KHO restore API. Add another read-only helper to the arm-smmu-v3-kexec.c: - arm_smmu_kexec_check_ste_cdtab() It validates the CD table geometry in an S1 STE against this kernel's own ssid_bits and the 2-level HW capability. And it accepts a linear CD table on the 2-level capable HW too, since a previous kernel might have used one, like the linear stream table. The CD table base gets validated against the table size as well, since the spec aligns a CD table to its own size, where an unaligned base would be a CONSTRAINED UNPREDICTABLE case: HW may zero its low bits or may fetch any CD in the table, so a scan reading such a base could miss the CDs in use. Reviewed-by: Jason Gunthorpe Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c | 57 +++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 41d7a907b9ba2..1bcf6cb2ebb3c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1261,6 +1261,9 @@ int arm_smmu_kexec_parse_strtab_linear(struct arm_smm= u_device *smmu, int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, u64 l1_desc, u32 idx, phys_addr_t *l2_base); +int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, + phys_addr_t *cdtab, u32 *s1fmt, + u32 *max_contexts); #endif /* CONFIG_ARM_SMMU_V3_KEXEC */ =20 #ifdef CONFIG_CRASH_DUMP diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c index b15e23df11b6d..700f63c7972e9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c @@ -164,3 +164,60 @@ int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smm= u_device *smmu, *l2_base =3D base; return 0; } + +/** + * arm_smmu_kexec_check_ste_cdtab() - Decode the CD table geometry of an S= TE + * @smmu: SMMU device of this kernel + * @ste0: first 64 bits of the previous kernel's S1 STE + * @cdtab: pointer to return the CD table's physical address + * @s1fmt: pointer to return the CD table format + * @max_contexts: pointer to return the number of CDs + * + * Note that a linear CD table on the 2-level capable hardware is accepted= , as a + * previous kernel might have used one, like the linear stream table. + * + * Note that the spec requires a CD table to be aligned to its own size, s= o an + * unaligned @cdtab gets rejected here: HW may then zero the low bits or f= etch + * any CD in the table, leaving the live ASIDs unknowable to this scan. + * + * Return: 0 on success with the three outputs set, or -EINVAL on a bad ge= ometry + */ +int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, + phys_addr_t *cdtab, u32 *s1fmt, + u32 *max_contexts) +{ + phys_addr_t base =3D ste0 & STRTAB_STE_0_S1CTXPTR_MASK; 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charset="utf-8" An adopted stream table keeps translating in-flight DMAs, so the SMMU also keeps caching the TLB entries tagged with the previous kernel's ASIDs and VMIDs. Any kexec flavor retaining those translations must reserve all the in-use IDs, so that this kernel cannot ever give any of its own domains an overlapping ID that would alias the previous kernel's cached TLB entries. Add the reservation helpers to arm-smmu-v3-kexec.c: - arm_smmu_kexec_scan_and_resv_ids() - arm_smmu_kexec_unresv_ids() At adoption time, arm_smmu_kexec_scan_and_resv_ids() runs a one-off scan: walking the stream table set up in the strtab_cfg and every CD table behind an S1 STE, it reserves the ASIDs in the asid xarray and the S2VMIDs in the vmid ida. The scan memremaps each table transiently, which is a necessity even for a live update: the ID reservation must be complete by the end of the SMMU probe itself, before this kernel starts allocating any ID for its own domains, yet the CD tables are only claimed when their masters get to re-probe, long after that point. Thus, the scan cannot rely on any claimed mapping and must map each table by itself. The scan walks untrusted tables, yet every loop is strictly index-bounded: the iteration counts derive from the log2size and s1cdmax fields, which are validated against this kernel's own sid_bits and ssid_bits, so a corrupted table cannot extend the walk. The ASID space is per SMMU instance and the scan runs before its own SMMU registers with the IOMMU core, i.e. before any domain of that SMMU can hold an ASID. So it reserves via xa_reserve(), and a failing scan just empties the xarray and the ida, since they hold nothing else at that point. Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c | 235 ++++++++++++++++++ 2 files changed, 237 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 1bcf6cb2ebb3c..64927c54f8b6b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1264,6 +1264,8 @@ int arm_smmu_kexec_check_strtab_l1_desc(struct arm_sm= mu_device *smmu, int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, phys_addr_t *cdtab, u32 *s1fmt, u32 *max_contexts); +int arm_smmu_kexec_scan_and_resv_ids(struct arm_smmu_device *smmu); +void arm_smmu_kexec_unresv_ids(struct arm_smmu_device *smmu); #endif /* CONFIG_ARM_SMMU_V3_KEXEC */ =20 #ifdef CONFIG_CRASH_DUMP diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c index 700f63c7972e9..8c53cd7570070 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c @@ -221,3 +221,238 @@ int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_de= vice *smmu, u64 ste0, *max_contexts =3D 1U << s1cdmax; return 0; } + +static int arm_smmu_kexec_resv_asid(struct arm_smmu_device *smmu, u32 asid) +{ + /* A valid CD never has ASID 0; both kernels share the same HW limit */ + if (!asid || asid >=3D 1UL << smmu->asid_bits) + return -EINVAL; + + guard(mutex)(&arm_smmu_asid_lock); + + /* + * The scan runs before this SMMU registers with the IOMMU core, so no + * domain of its own holds an ASID yet, while xa_reserve() does nothing + * if the entry is there, covering a domain's ASID that many CDs share. + */ + return xa_reserve(&smmu->asid_map, asid, GFP_KERNEL); +} + +static int arm_smmu_kexec_resv_vmid(struct arm_smmu_device *smmu, u32 vmid) +{ + int ret; + + /* A translating STE never has VMID 0, which is reserved for bypass */ + if (!vmid || vmid >=3D 1UL << smmu->vmid_bits) + return -EINVAL; + + ret =3D ida_alloc_range(&smmu->vmid_map, vmid, vmid, GFP_KERNEL); + if (ret < 0 && ret !=3D -ENOSPC) /* -ENOSPC means already reserved */ + return ret; + return 0; +} + +static int arm_smmu_kexec_resv_cd_asids(struct arm_smmu_device *smmu, + struct arm_smmu_cd *cds, u32 num_cds) +{ + int ret =3D 0; + u32 i; + + for (i =3D 0; i < num_cds; i++) { + u64 val =3D le64_to_cpu(cds[i].data[0]); + u32 asid =3D FIELD_GET(CTXDESC_CD_0_ASID, val); + + if (!(val & CTXDESC_CD_0_V)) + continue; + ret =3D arm_smmu_kexec_resv_asid(smmu, asid); + if (ret) + break; + } + return ret; +} + +/* + * Reserve the ASIDs of all the valid CDs of an S1 STE in the previous ker= nel's + * CD tables. The CD tables are transiently memremapped for the scan. + */ +static int arm_smmu_kexec_resv_s1_asids(struct arm_smmu_device *smmu, u64 = ste0) +{ + struct arm_smmu_cdtab_l1 *l1tab; + u32 num_l1_ents, num_cds, i; + u32 max_contexts, s1fmt; + phys_addr_t cdtab; + int ret; + + ret =3D arm_smmu_kexec_check_ste_cdtab(smmu, ste0, &cdtab, &s1fmt, + &max_contexts); + if (ret) + return ret; + + if (s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) { + struct arm_smmu_cd *cds; + + cds =3D memremap(cdtab, max_contexts * sizeof(*cds), MEMREMAP_WB); + if (!cds) + return -ENOMEM; + ret =3D arm_smmu_kexec_resv_cd_asids(smmu, cds, max_contexts); + memunmap(cds); + return ret; + } + + num_l1_ents =3D DIV_ROUND_UP(max_contexts, CTXDESC_L2_ENTRIES); + l1tab =3D memremap(cdtab, num_l1_ents * sizeof(*l1tab), MEMREMAP_WB); + if (!l1tab) + return -ENOMEM; + + /* max_contexts being under a full leaf makes the only leaf partial */ + num_cds =3D min_t(u32, max_contexts, CTXDESC_L2_ENTRIES); + + /* Aliased L2 tables cannot extend the walk; they only repeat a scan */ + for (i =3D 0; i < num_l1_ents; i++) { + u64 l1_desc =3D le64_to_cpu(l1tab[i].l2ptr); + phys_addr_t l2_base =3D l1_desc & CTXDESC_L1_DESC_L2PTR_MASK; + struct arm_smmu_cdtab_l2 *l2; + + if (!(l1_desc & CTXDESC_L1_DESC_V)) + continue; + + /* + * A valid descriptor never carries a null pointer. Also, an L2 + * table is always 64KB-aligned, so an unaligned pointer would + * make this kernel read a different table. + */ + if (!l2_base || !IS_ALIGNED(l2_base, sizeof(*l2))) { + ret =3D -EINVAL; + break; + } + + l2 =3D memremap(l2_base, num_cds * sizeof(*l2->cds), MEMREMAP_WB); + if (!l2) { + ret =3D -ENOMEM; + break; + } + ret =3D arm_smmu_kexec_resv_cd_asids(smmu, l2->cds, num_cds); + memunmap(l2); + if (ret) + break; + } + memunmap(l1tab); + return ret; +} + +static int arm_smmu_kexec_resv_ste_ids(struct arm_smmu_device *smmu, + struct arm_smmu_ste *ste) +{ + u32 vmid =3D FIELD_GET(STRTAB_STE_2_S2VMID, le64_to_cpu(ste->data[2])); + u64 ste0 =3D le64_to_cpu(ste->data[0]); + + if (!(ste0 & STRTAB_STE_0_V)) + return 0; + + switch (FIELD_GET(STRTAB_STE_0_CFG, ste0)) { + case STRTAB_STE_0_CFG_ABORT: + case STRTAB_STE_0_CFG_BYPASS: + return 0; + case STRTAB_STE_0_CFG_S1_TRANS: + return arm_smmu_kexec_resv_s1_asids(smmu, ste0); + case STRTAB_STE_0_CFG_NESTED: + /* + * A guest-owned CD table is in the IPA space, unreachable. Its + * ASIDs are only tagged with the S2VMID reserved below, so they + * cannot alias this kernel's VMID-0 or EL2 S1 domains. + */ + fallthrough; + case STRTAB_STE_0_CFG_S2_TRANS: + return arm_smmu_kexec_resv_vmid(smmu, vmid); + default: + return -EINVAL; + } +} + +/** + * arm_smmu_kexec_scan_and_resv_ids() - Reserve a stream table's in-use IDs + * @smmu: SMMU device of this kernel, with an adopted or restored strtab_c= fg + * + * Scan the stream table set up in the strtab_cfg and every CD table behin= d an + * S1 STE, reserving all of the in-use ASIDs and VMIDs. A failing scan rol= ls + * back through arm_smmu_kexec_unresv_ids(). + * + * Note that the scan selects the linear or 2-level walk per this kernel's= own + * ARM_SMMU_FEAT_2_LVL_STRTAB, so the caller must have matched the feature= bit + * to the format of the adopted stream table in the strtab_cfg. + * + * Return: 0 on success, -EINVAL on any malformed table entry, or -ENOMEM = on a + * memory shortage + */ +int arm_smmu_kexec_scan_and_resv_ids(struct arm_smmu_device *smmu) +{ + struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; + int ret =3D 0; + u32 i, j; + + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)) { + for (i =3D 0; i < cfg->linear.num_ents; i++) { + ret =3D arm_smmu_kexec_resv_ste_ids( + smmu, &cfg->linear.table[i]); + if (ret) + return ret; + } + return 0; + } + + /* Aliased L2 tables cannot extend the scan; they only repeat a scan */ + for (i =3D 0; i < cfg->l2.num_l1_ents; i++) { + u64 l1_desc =3D le64_to_cpu(cfg->l2.l1tab[i].l2ptr); + struct arm_smmu_strtab_l2 *l2; + phys_addr_t base; + + ret =3D arm_smmu_kexec_check_strtab_l1_desc(smmu, l1_desc, i, + &base); + if (ret =3D=3D 1) + continue; + if (ret) + return ret; + + /* + * This kernel will map the previous kernel's L2 tables lazily + * or not at all. Here, take a transient view for this scan. + */ + l2 =3D memremap(base, sizeof(*l2), MEMREMAP_WB); + if (!l2) + return -ENOMEM; + for (j =3D 0; j < ARRAY_SIZE(l2->stes); j++) { + ret =3D arm_smmu_kexec_resv_ste_ids(smmu, &l2->stes[j]); + if (ret) + break; + } + memunmap(l2); + if (ret) + return ret; + } + return 0; +} + +/** + * arm_smmu_kexec_unresv_ids() - Release the IDs that a failing scan reser= ved + * @smmu: SMMU device of this kernel that failed its reservation scan + * + * Undo the reservations of a failing arm_smmu_kexec_scan_and_resv_ids() c= all, + * for a caller that falls back to a full reset. + * + * That reset flushes the whole TLB, so the previous kernel's IDs no longe= r need + * any protection. A scan that fails halfway would otherwise keep a good s= hare + * of an 8-bit ASID or VMID space reserved for nothing. + */ +void arm_smmu_kexec_unresv_ids(struct arm_smmu_device *smmu) +{ + /* + * Emptying both maps releases exactly this scan's IDs, as no domain of + * this SMMU can hold one until it registers with the IOMMU core, later + * in the probe. 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charset="utf-8" The adopted stream table keeps translating in-flight DMA, so the SMMU keeps caching TLB entries tagged with the crashed kernel's ASIDs and VMIDs. If this kernel handed one of those IDs to its own domain, the new domain's DMA could hit the crashed kernel's cached translations, e.g. a stale entry left behind by an invalidation that the crash cut short. Scan the adopted stream table at adoption time, reserving every ID in use via arm_smmu_kexec_scan_and_resv_ids(), and roll all of them back through arm_smmu_kexec_unresv_ids() should the scan fail. A nested STE's guest-owned CD table is left alone, since its ASIDs live in a space of their own under that STE's VMID. Reserving that VMID covers all of them, so there is no reason for the scan to walk the (VMID, ASID) pairs behind it. The only ASIDs needing a reservation are those in the space that this kernel uses for its own domains. Note that, on an E2H/VHE host, the kernel's stage-1 domains are tagged by the EL2 ASID, and the TLBI_EL2_* commands take no VMID. So isolating this kernel by a reserved VMID alone would not work. Reserving the ASIDs covers both the E2H and the NSEL1 cases. Reservations are never released: a kdump kernel reboots after it saves the vmcore, and the full-reset fallback flushes the entire TLB, which turns any stale reservation into a merely unused ID. If the scan finds any inconsistent structure, toss the entire adoption and fall back to the full reset. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c | 12 +++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c index a074d59ce3445..6740cc7e671cb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c @@ -205,16 +205,26 @@ int arm_smmu_kdump_adopt_strtab(struct arm_smmu_devic= e *smmu) goto err; } =20 + ret =3D arm_smmu_kexec_scan_and_resv_ids(smmu); + if (ret) { + dev_warn(smmu->dev, "failed to reserve in-use ASIDs/VMIDs\n"); + arm_smmu_kdump_adopt_cleanup(smmu); + goto err_unresv; + } + ret =3D devm_add_action_or_reset(smmu->dev, arm_smmu_kdump_adopt_cleanup, smmu); /* devm_add_action_or_reset ran the cleanup upon failure */ if (ret) { dev_warn(smmu->dev, "failed to set up cleanup action\n"); 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charset="utf-8" Though the kdump kernel adopts the crashed kernel's stream table, the iommu core will still try to attach each probed device to a default domain, which overwrites the adopted STE and breaks in-flight DMA from that device. Implement an is_attach_deferred() callback to prevent this. For each device that has STE.V=3D1 and STE.Cfg!=3DAbort in the adopted table, defer the def= ault domain attachment, until the device driver explicitly requests it. Also, move arm_smmu_get_step_for_sid() to the header for the kdump function to use. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 23 +++++++++++++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c | 19 ++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 ++++++++----------- 3 files changed, 52 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 64927c54f8b6b..3f2ebdb99e8f7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1219,6 +1219,22 @@ int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_de= vice *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_cmd *cmds, int n, bool sync); + +static inline struct arm_smmu_ste * +arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + /* Two-level walk */ + return &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)] + ->stes[arm_smmu_strtab_l2_idx(sid)]; + } else { + /* Simple linear lookup */ + return &cfg->linear.table[sid]; + } +} + int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_cmd *cmds, int n, @@ -1273,6 +1289,7 @@ int arm_smmu_kdump_adopt_strtab(struct arm_smmu_devic= e *smmu); int arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_smmu_device *smmu, u32 sid, phys_addr_t base, u32 span, struct arm_smmu_strtab_l2 **l2table); +bool arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master); #else /* CONFIG_CRASH_DUMP */ static inline int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu) { @@ -1286,6 +1303,12 @@ arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_s= mmu_device *smmu, u32 sid, { return -EOPNOTSUPP; } + +static inline bool +arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master) +{ + return false; +} #endif /* CONFIG_CRASH_DUMP */ =20 struct arm_vsmmu { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c index 6740cc7e671cb..5bc938901b65d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c @@ -237,3 +237,22 @@ int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device= *smmu) smmu->options &=3D ~ARM_SMMU_OPT_KDUMP_ADOPT; return ret; } + +bool arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master) +{ + struct arm_smmu_device *smmu =3D master->smmu; + int i; + + for (i =3D 0; i < master->num_streams; i++) { + struct arm_smmu_ste *ste =3D + arm_smmu_get_step_for_sid(smmu, master->streams[i].id); + u64 ent0 =3D le64_to_cpu(ste->data[0]); + + /* Defer only when there might be in-flight DMAs */ + if ((ent0 & STRTAB_STE_0_V) && + FIELD_GET(STRTAB_STE_0_CFG, ent0) !=3D STRTAB_STE_0_CFG_ABORT) + return true; + } + + return false; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1d4fb6c4f0a91..ef1ef4d452949 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2965,21 +2965,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_= domain *smmu_domain, return 0; } =20 -static struct arm_smmu_ste * -arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) -{ - struct arm_smmu_strtab_cfg *cfg =3D &smmu->strtab_cfg; - - if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { - /* Two-level walk */ - return &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)] - ->stes[arm_smmu_strtab_l2_idx(sid)]; - } else { - /* Simple linear lookup */ - return &cfg->linear.table[sid]; - } -} - void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, const struct arm_smmu_ste *target) { @@ -4390,6 +4375,15 @@ static int arm_smmu_def_domain_type(struct device *d= ev) return 0; } =20 +static bool arm_smmu_is_attach_deferred(struct device *dev) +{ + struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + + if (master->smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) + return arm_smmu_kdump_is_attach_deferred(master); + return false; +} + static const struct iommu_ops arm_smmu_ops =3D { .identity_domain =3D &arm_smmu_identity_domain, .blocked_domain =3D &arm_smmu_blocked_domain, @@ -4398,6 +4392,7 @@ static const struct iommu_ops arm_smmu_ops =3D { .hw_info =3D arm_smmu_hw_info, .domain_alloc_sva =3D arm_smmu_sva_domain_alloc, .domain_alloc_paging_flags =3D arm_smmu_domain_alloc_paging_flags, + .is_attach_deferred =3D arm_smmu_is_attach_deferred, .probe_device =3D arm_smmu_probe_device, .release_device =3D arm_smmu_release_device, .device_group =3D arm_smmu_device_group, --=20 2.43.0 From nobody Sat Sep 26 20:27:43 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012041.outbound.protection.outlook.com [52.101.48.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0E2B357D0B for ; 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charset="utf-8" When ARM_SMMU_OPT_KDUMP_ADOPT is detected, do not disable SMMUEN and skip the CR1/CR2/STRTAB_BASE update sequence in arm_smmu_device_reset(). Those register writes are all CONSTRAINED UNPREDICTABLE while CR0_SMMUEN=3D=3D1, = so leaving them intact lets in-flight DMAs continue to be translated by the adopted stream table. Initialize 'enables' to 0, so it can carry the retained CR0 fields in the kdump case, clearing only the queue enable bits. Then, preserve them when enabling the command queue. The retained CR0 keeps the crashed kernel's ATSCHK too, which selects the fast (0) or the safe (1) mode for the ATS translated traffic. Switching to the safe mode would start checking the in-flight traffic against STE.EATS fields that the crashed kernel never set up for a check, aborting the very DMAs being carried. Clear latched gerror bits if necessary. Reviewed-by: Kevin Tian Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 60 +++++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ef1ef4d452949..0fb8c60526699 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4882,10 +4882,28 @@ static void arm_smmu_write_strtab(struct arm_smmu_d= evice *smmu) static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; - u32 reg, enables; + u32 reg, enables =3D 0; =20 - /* Clear CR0 and sync (disables SMMU and queue processing) */ reg =3D readl_relaxed(smmu->base + ARM_SMMU_CR0); + + /* + * In a kdump case (set when CR0_SMMUEN=3D1 and !GERROR_SFM_ERR), retain + * all the live CR0 fields, e.g. CR0_SMMUEN to avoid aborting in-flight + * DMA and CR0_ATSCHK to carry on the ATS-check policy, while clearing + * only the queue enable bits for this kernel to take over the queues. + * + * According to spec, updating STRTAB_BASE/CR1/CR2 when CR0_SMMUEN=3D1 is + * CONSTRAINED UNPREDICTABLE. So, skip those register updates and rely + * on the adopted stream table from the crashed kernel. + */ + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + dev_info(smmu->dev, + "kdump: retaining SMMUEN for in-flight DMA\n"); + enables =3D reg & ~(CR0_CMDQEN | CR0_EVTQEN | CR0_PRIQEN); + goto reset_queues; + } + + /* Clear CR0 and sync (disables SMMU and queue processing) */ if (reg & CR0_SMMUEN) { dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); @@ -4915,12 +4933,41 @@ static int arm_smmu_device_reset(struct arm_smmu_de= vice *smmu) /* Stream table */ arm_smmu_write_strtab(smmu); =20 +reset_queues: + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + /* + * Disable queues since arm_smmu_device_disable() was skipped. + * CR0 fields are independent per spec, so the queue enable bits + * can be cleared while retaining SMMUEN=3D1. + */ + ret =3D arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to disable queues\n"); + return ret; + } + } + + /* + * GERROR bits are latched. Read after queue disabling so that unhandled + * errors would be visible. Ack everything prior to re-enabling the CMDQ + * as a stale CMDQ_ERR would halt the CMDQ and new command will timeout. + * Acking SFM_ERR is defined too, although it would not exit the SFM. + */ + if (is_kdump_kernel()) { + u32 gerror =3D readl_relaxed(smmu->base + ARM_SMMU_GERROR); + u32 gerrorn =3D readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + + if ((gerror ^ gerrorn) & GERROR_ERR_MASK) + writel(gerror, smmu->base + ARM_SMMU_GERRORN); + } + /* Command queue */ writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); =20 - enables =3D CR0_CMDQEN; + enables |=3D CR0_CMDQEN; ret =3D arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); if (ret) { @@ -4976,7 +5023,12 @@ static int arm_smmu_device_reset(struct arm_smmu_dev= ice *smmu) } } =20 - if (smmu->features & ARM_SMMU_FEAT_ATS) { + /* + * In a kdump adopt case, retain the crashed kernel's ATS-check policy + * captured above rather than forcing it on. + */ + if (!(smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) && + (smmu->features & ARM_SMMU_FEAT_ATS)) { enables |=3D CR0_ATSCHK; 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Sun, 30 Aug 2026 16:18:41 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v10 12/13] iommu/arm-smmu-v3: Skip RMR bypass for kdump adoption Date: Sun, 30 Aug 2026 16:18:13 -0700 Message-ID: <89285912833ba2aea8e43d10d66f0e7e01e1c256.1788130528.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|DS0PR12MB7725:EE_ X-MS-Office365-Filtering-Correlation-Id: 742db65c-0e2e-42a7-ced0-08df06ed0d57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|30052699003|23010399003|7416014|376014|6133799003|22082099003|18002099003|56012099006|11063799006|10067099003; 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charset="utf-8" RMR bypass STEs are installed during SMMUv3 probe for StreamIDs listed by IORT RMR nodes. A normal boot switches the driver to a fresh stream table whose initial STEs abort, so those RMR SIDs need bypass entries before it becomes live. This preserves firmware/guest-owned traffic, including vSMMU guest MSI cases built around RMR-described SIDs. ARM_SMMU_OPT_KDUMP_ADOPT is the opposite case: the driver keeps SMMUEN set and adopts the crashed kernel's stream table, so RMR SIDs already have the only translation state known to be safe for active in-flight DMA. Replacing an adopted STE with bypass can turn translated DMA into physical DMA, then point it at the wrong memory. arm_smmu_make_bypass_ste() also rewrites the STE in place after clearing it first. While the table is live, a concurrent hardware STE fetch can observe V=3D0 or mixed old/new state. Leaving the adopted STE unmodified keeps the kdump kernel using the crashed kernel's translation. That gives the endpoint driver a chance to probe and quiesce the device. If the old STE was already abort or invalid, installing bypass would create new DMA permission; leaving it alone is a safer failure mode. Later domain setup still gets the RMR direct mappings through the reserved-region path. Reviewed-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Assisted-by: Codex:gpt-5.5 Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 0fb8c60526699..525cdc2e7d495 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5536,6 +5536,14 @@ static void arm_smmu_rmr_install_bypass_ste(struct a= rm_smmu_device *smmu) struct list_head rmr_list; struct iommu_resv_region *e; =20 + /* + * Kdump adoption keeps the crashed kernel's table live. Rewriting the + * adopted STE here could expose an in-flight fetch to a transient V=3D0 + * entry, or change Cfg=3Dtranslate to Cfg=3Dbypass. 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charset="utf-8" arm_smmu_device_hw_probe() runs before arm_smmu_init_structures(), so it's natural to decide whether the kdump kernel must adopt the crashed kernel's stream table. Given that memremap is used to adopt the old stream table, set this option only on a coherent SMMU. And make sure SMMU isn't in Service Failure Mode. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen Tested-by: Breno Leitao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 ++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c | 27 +++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 +++ 3 files changed, 36 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 3f2ebdb99e8f7..e0f16f8d13842 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1290,6 +1290,7 @@ int arm_smmu_kdump_adopt_deferred_l2_strtab(struct ar= m_smmu_device *smmu, u32 sid, phys_addr_t base, u32 span, struct arm_smmu_strtab_l2 **l2table); bool arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master); +void arm_smmu_device_kdump_probe(struct arm_smmu_device *smmu); #else /* CONFIG_CRASH_DUMP */ static inline int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu) { @@ -1309,6 +1310,10 @@ arm_smmu_kdump_is_attach_deferred(struct arm_smmu_ma= ster *master) { return false; } + +static inline void arm_smmu_device_kdump_probe(struct arm_smmu_device *smm= u) +{ +} #endif /* CONFIG_CRASH_DUMP */ =20 struct arm_vsmmu { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c b/drivers/io= mmu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c index 5bc938901b65d..e7c7927b1ff79 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kdump.c @@ -256,3 +256,30 @@ bool arm_smmu_kdump_is_attach_deferred(struct arm_smmu= _master *master) =20 return false; } + +void arm_smmu_device_kdump_probe(struct arm_smmu_device *smmu) +{ + u32 gerror, gerrorn, active; + + /* No adoption if SMMU is disabled (i.e., there is no in-flight DMA) */ + if (!(readl_relaxed(smmu->base + ARM_SMMU_CR0) & CR0_SMMUEN)) + return; + + /* For now, only support a coherent SMMU that works with MEMREMAP_WB */ + if (!(smmu->features & ARM_SMMU_FEAT_COHERENCY)) { + dev_warn(smmu->dev, + "non-coherent SMMU unsupported; reset to block all DMAs\n"); + return; + } + + gerror =3D readl_relaxed(smmu->base + ARM_SMMU_GERROR); + gerrorn =3D readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + active =3D gerror ^ gerrorn; + if (active & GERROR_SFM_ERR) { + dev_warn(smmu->dev, + "SMMU in Service Failure Mode, must reset\n"); + return; + } + + smmu->options |=3D ARM_SMMU_OPT_KDUMP_ADOPT; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 525cdc2e7d495..2c5befcf64456 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5367,6 +5367,10 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) =20 dev_info(smmu->dev, "oas %lu-bit (features 0x%08x)\n", smmu->oas, smmu->features); + + if (is_kdump_kernel()) + arm_smmu_device_kdump_probe(smmu); + return 0; } =20 --=20 2.43.0