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Wed, 26 Aug 2026 07:37:58 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH 1/1] gpu: nova-core: correct FSP secure boot documentation Date: Wed, 26 Aug 2026 17:37:46 +0300 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CE:EE_|SA1PR12MB7320:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ecf7666-7901-4ad2-e1fb-08df037fb58e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700016|376014|23010399003|22082099003|18002099003|3023799007|56012099006|11063799006|10067099003|6133799003; X-Microsoft-Antispam-Message-Info: TDCdoGf9jXxK6V8EJ1/h7igI0yrgjBdJO5FtTnXSKHN6d99gzEOKj3SuRTLRfLtwRuLcmDDM2/IAmO9CuWgt9yMJj0SneVMm5sdvwx7IoOtUwtOdAhktioZs7RoSN2Gt9YQ8PcNv8kyxWi5/kYZqb8f8vWgyCaza+n4y1+EaMwXxyXxobGVK1KlyGSW/aXmvPXNJ6wZgZTZY41xRRom6mVZx0buA8ZLOtWH/kEQu4PFhzbqEGgDCR2tGpDWBt2s8b+WQ1iCDN2clusfjS4qlcyM7p81hgnwN0PvaDeJLt1yw0TTXjuV9RpLiMqk/Y26/hvly1hXTqZe4iUXeIE0PcuATFWi8aDX9nBTSIX8cOBngXpnS4Rh0f0Tl3vL74zQSATXMJDT9FhZeX4UvYkkq8O/GUlWNCFzJ+gxb7iG9QonkQqeq/HdeRAz3dOeWwaugfHfZz17N+JJtphLk1RCZ498rQ9WTKsdy3ahPIrldOQcTt81LVfbPv8vsZN79DUJWymg4/rgf1nZuVwPTSVWXMFNxg5pZeaD2HE8RxO+YFopP1L0K+dM+MMFq/dumxfh/TTGOAbTJCjl9pkmLDBldQ/SBw96MlOa3RN+UAYrBxv4Xu2+TlR4uGUhM7crya7mJzUCccIHDJxSE8OxsC0KnH7+akMhA91iaPLNRqR5J2doYv4/LEd5PasnvAzTl1rdVc7VSCKR5SgN5HKKH42XxGw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700016)(376014)(23010399003)(22082099003)(18002099003)(3023799007)(56012099006)(11063799006)(10067099003)(6133799003);DIR:OUT;SFP:1101; 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charset="utf-8" The FSP documentation still blurs the roles of FSP, GSP BootROM, and GSP-FMC in the common Hopper/Blackwell dGPU boot path. It also uses incorrect expansions for NVDM and FRTS and describes GSP-FMC as an ELF image, while nova-core loads it from a TLV firmware file. Correct those terms and show the FSP-to-GSP handoff in the existing message-flow diagram. Clarify that the COT response reports command status only, and scope the SEC2 and PRC descriptions to the dGPU platforms covered by nova-core. Signed-off-by: Zhi Wang --- Documentation/gpu/nova/core/fsp.rst | 88 ++++++++++++++++------------- 1 file changed, 50 insertions(+), 38 deletions(-) diff --git a/Documentation/gpu/nova/core/fsp.rst b/Documentation/gpu/nova/c= ore/fsp.rst index cc2e3bbb9b53..bebe3c8ede2a 100644 --- a/Documentation/gpu/nova/core/fsp.rst +++ b/Documentation/gpu/nova/core/fsp.rst @@ -3,8 +3,8 @@ =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D FSP (Foundation Security Processor) and Secure Boot =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D -This document describes the role of the FSP in the GPU boot sequence on -Hopper and Blackwell GPUs, and how it differs from the earlier Ampere boot +This document describes the role of the FSP in the common boot path for +Hopper and Blackwell dGPUs, and how it differs from the earlier Ampere boot flow. It also provides a brief overview of the PRC (Product Reconfiguration Control) protocol used to query device configuration through FSP. As with other documents in this directory, the information is subject to change and @@ -42,18 +42,20 @@ On **Hopper/Blackwell** GPUs, FSP replaces this multi-s= tage process with a single message-driven interface:: =20 FSP (hardware root of trust, boots from ROM) - -> FMC (First Mutable Code, verified by FSP) - -> GSP-RM (verified and loaded by FMC) + -> GSP BootROM + -> GSP-FMC (First Mutable Code, running on GSP) + -> GSP-RM (verified and loaded by GSP-FMC) =20 -The driver only needs to: +At a high level, the driver: =20 1. Wait for FSP to complete its own secure boot (polling a scratch registe= r). -2. Send a Chain of Trust (COT) message to FSP with the FMC firmware locati= on, - cryptographic signatures, and GSP boot parameters. -3. FSP authenticates the FMC firmware and boots it, FMC in turn loads GSP-= RM. +2. Send a Chain of Trust (COT) message to FSP with the GSP-FMC firmware + location, cryptographic signatures, and GSP boot parameters. +3. Wait for the FSP command response, then for later GSP-side boot milesto= nes. =20 -There is no SEC2 involvement, no Booter ucode, and no FWSEC-FRTS stage. The -entire secure boot is driven by a single FSP message exchange. +In the dGPU path described here, SEC2 and Booter ucode are not used to bri= ng +up GSP-RM, and FWSEC-FRTS is not run as a separate stage. The driver initi= ates +secure boot through a single FSP message exchange. =20 Chain of Trust (COT) protocol =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D @@ -62,39 +64,49 @@ ensuring the GPU reaches a known, trusted state. =20 The driver communicates with FSP using a message queue (Falcon MSGQ interface). Each message consists of an MCTP (Management Component Transpo= rt -Protocol) transport header and an NVDM (NVIDIA Vendor Defined Message) hea= der, +Protocol) transport header and an NVDM (NVIDIA Data Model) header, followed by a protocol-specific payload. =20 For Chain of Trust, the payload includes: =20 -- The system memory address of the FMC firmware image. -- Cryptographic material: a SHA-384 hash, RSA-3K public key, and RSA-3K - signature extracted from the FMC ELF firmware. -- FRTS (Firmware Runtime Services) region information (vidmem offset and s= ize). +- The system memory address of the GSP-FMC firmware image. +- Cryptographic material extracted from the GSP-FMC TLV firmware: a SHA-384 + hash, RSA-3K public key, and RSA-3K signature. +- FRTS (Firmware Runtime Security) region information (vidmem offset and s= ize). - The system memory address of the GSP boot arguments structure. =20 -FSP verifies the signature against the provided public key and hash, and if -verification succeeds, boots the FMC. The FMC then authenticates and launc= hes -GSP-RM. +FSP validates the COT payload and authenticates the GSP-FMC image using the +supplied cryptographic material. It then stages the image in GSP memory and +triggers GSP BootROM. GSP BootROM authenticates and starts GSP-FMC, which = then +authenticates and launches GSP-RM. =20 The message flow is:: =20 - nova-core FSP - | | - | 1. Poll scratch register | - | (wait for FSP boot complete) | - | | - | 2. COT message ------------> | - | (FMC addr, signatures, | - | boot params) | - | | - | |--- Verify FMC signature - | |--- Boot FMC - | |--- FMC loads GSP-RM - | | - | 3. COT response <------------ | - | (success/error) | - | | + nova-core FSP GSP + | | | + | 1. Poll scratch register | | + | (wait for FSP boot complete) | | + | | | + | 2. COT message ------------> | | + | (GSP-FMC addr, | | + | signatures, boot params) | | + | | | + | | Verify GSP-FMC | + | | signature | + | | | + | | Load GSP-FMC image | + | | -------------------->| + | | | + | | Trigger GSP BootROM | + | | -------------------->| GSP Boot= ROM + | | | starts G= SP-FMC + | 3. COT response <----------- | | GSP-FMC + | (command status) | | verifies= and + | | | starts G= SP-RM + | | | + +The COT response reports only the FSP command status; it does not indicate +that GSP-RM is ready. =20 FSP message format =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -107,7 +119,7 @@ All FSP messages share a common header format consistin= g of two 32-bit words: - Bits 29:28: Packet sequence number - Bits 23:16: Source Endpoint ID =20 -**NVDM header** (NVIDIA Vendor Defined Message): +**NVDM header** (NVIDIA Data Model): =20 - Bits 6:0: MCTP message type (0x7e =3D vendor-defined PCI) - Bits 23:8: PCI vendor ID (0x10de =3D NVIDIA) @@ -127,9 +139,9 @@ Each knob has two values: - **Active**: the currently effective value for this boot cycle. - **Persistent**: the value stored in InfoROM, applied on subsequent boots. =20 -The nova-core driver uses PRC to read the vGPU mode knob (object ID 0x29) -during early boot, before firmware loading, to determine whether the GPU -should operate in vGPU mode. +On Blackwell and later dGPUs, nova-core uses PRC to read the vGPU mode knob +(object ID 0x29) during early boot, before firmware loading, to determine +whether the GPU should operate in vGPU mode. =20 The PRC message format follows the same MCTP/NVDM header structure as COT, with NVDM type 0x13. The payload contains: --=20 2.53.0