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Peter Anvin" , Petr Tesarik , Ravi Bangoria , Ananth Narayan , Sandipan Das Subject: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug Date: Thu, 6 Aug 2026 15:33:26 +0530 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb10.amd.com (10.181.42.219) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SA0PR12MB7461:EE_ X-MS-Office365-Filtering-Correlation-Id: 615ca743-71af-46f2-0605-08def3a3c2fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|376014|7416014|82310400026|1800799024|6133799003|10067099003|56012099006|11063799006|18002099003|22082099003|3023799007; X-Microsoft-Antispam-Message-Info: 0uLGBZzmvsXlN3durF93oSyy/NqcKaEvGbqFxD6K82fwvo6pdnLn5Q1H+xHtu6/naORkfSxJ0WAM6MyQOKBLjbEi3RhX6B1WCrDOx7va1pCPe1JMtxDP7Rl+GaAIwWL+H12ZjFQ4isrlTYZykQzO6F8ZyF0O4awv3796aHhk2UU9/jibxThYXT0yGWc5jEXkyibBiKPWX/6sXmjiRpRAbK/msd8zEWXrsnb/4y2ayZ/950b+E2CZLxeYslEwxDbwrLfSE6ULulDNNFAMfHkHR2gbiaaB7ZH/nP4LfMSw+QxWmsjT8LdnHxnhQ+oGBc41DaZQ/0rx7PRN+dPCWbEKKof+ZE+YzdTNJ4syVNhM7WGgCnRYfqUh2+86U555hhcWQrQ2Grj4iJtHmM/XGDPHJeHqbcNoWGAyhq6qyjUT1KI/6OqdYwoQkQiqc7Zfm3NMmWzhHvrZOKp4velcYvPFbUijtfB2oJqTw6QNwMghyMzAiP812I1SrnHwSmeZm3hg2ecnPnNQ6Zm309JvjY16KM9cWnIt5dk4V/bgzqi0HbrHUfUnFN+wbVgfAIOqeVqUYs0ATrwticGqFSmjllnCFyDPWs8HA2xLQUA7kCKQcFG37Nz1Bz+1D4o/3qQE04gvLph+dPd109pJWTWPfpPwsa+31Z6iR9bR+mvnAAS3T3vMT+oUxnWPUg/FVQetCeib X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(376014)(7416014)(82310400026)(1800799024)(6133799003)(10067099003)(56012099006)(11063799006)(18002099003)(22082099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j+G58DiFGWxmrIbFHgnyrL5aVaO/HRRqbivNUWSU4NOZxjR4ESQ2ZDhRmmn2/vSs/98AayoTzm3EiAVcemSxhVPY8mU2GK6WXmxfidIcLHW6WUOg948cvtmCYeJ8Nkwaqpzr3/ilJGAYVvcwZxLjBjmrZS64bDaX2lFxscqBNnWYp1YXKunDQ4TWKV8lk7IMpwVYbAs9xRenzB4O88S2LeQrez+h2lC3zwzS5cEhpAApYDYkHKr+8BRczJ1FDrfa9SWXrpplaDxE7EvC/G2NCn1hkOsVQk4NBgu5zOPs758/27YNMKMozsbquvTo2ftOGORf85OFDcRIZ/lPTHC56qDa9rVS231LddnXWwYQmu74Ir/tFxB+VGW5Pm9NUdZYCzRvC341pymiGhMl7YxW1aGy3s15BcV15zycAV/c1kxQZ+LKCBccs1BSznDNT1dr X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 10:16:20.8541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 615ca743-71af-46f2-0605-08def3a3c2fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7461 Content-Type: text/plain; charset="utf-8" perf_event_print_debug() dumps the global control and status MSRs whenever x86_pmu.version >=3D 2, reading registers that exist only on Intel-compatible PMUs. This is not safe since x86_pmu.version is not Intel-specific and is now set by other vendors whose global registers use different addresses. As a first step, split perf_event_print_debug() in two. The register dump moves into a new common helper, x86_pmu_print_debug(), leaving perf_event_print_debug() to handle the preamble and dispatch to an optional x86_pmu::print_debug method. This lets each vendor-specific PMU dump its own global state before chaining into the common helper. PMUs that do not implement the method, such as those with x86_pmu.version < 2, get the common helper alone. No functional change intended. Signed-off-by: Sandipan Das --- arch/x86/events/core.c | 29 ++++++++++++++++++++++------- arch/x86/events/perf_event.h | 4 ++++ 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index af0b67ffb43d..17dc53a62378 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, i= nt flags) perf_event_update_userpage(event); } =20 -void perf_event_print_debug(void) +void x86_pmu_print_debug(int cpu) { u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; unsigned long *cntr_mask, *fixed_cntr_mask; @@ -1566,17 +1566,11 @@ void perf_event_print_debug(void) u64 pebs, debugctl; int cpu, idx; =20 - guard(irqsave)(); - - cpu =3D smp_processor_id(); cpuc =3D &per_cpu(cpu_hw_events, cpu); cntr_mask =3D hybrid(cpuc->pmu, cntr_mask); fixed_cntr_mask =3D hybrid(cpuc->pmu, fixed_cntr_mask); pebs_constraints =3D hybrid(cpuc->pmu, pebs_constraints); =20 - if (!*(u64 *)cntr_mask) - return; - if (x86_pmu.version >=3D 2) { rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); @@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) } } =20 +void perf_event_print_debug(void) +{ + struct cpu_hw_events *cpuc; + unsigned long *cntr_mask; + int cpu; + + guard(irqsave)(); + + cpu =3D smp_processor_id(); + cpuc =3D &per_cpu(cpu_hw_events, cpu); + cntr_mask =3D hybrid(cpuc->pmu, cntr_mask); + + if (!*(u64 *)cntr_mask) + return; + + if (x86_pmu.print_debug) + x86_pmu.print_debug(cpu); + else + x86_pmu_print_debug(cpu); +} + void x86_pmu_stop(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index a8afea8d38f0..465bf513bb82 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1052,6 +1052,8 @@ struct x86_pmu { int num_hybrid_pmus; struct x86_hybrid_pmu *hybrid_pmu; enum intel_cpu_type (*get_hybrid_cpu_type) (void); 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Thu, 6 Aug 2026 05:04:57 -0500 From: Sandipan Das To: , CC: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , "Alexander Shishkin" , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , , "H . Peter Anvin" , Petr Tesarik , Ravi Bangoria , Ananth Narayan , Sandipan Das Subject: [PATCH 2/3] perf/x86: Move MSR_CORE_PERF_GLOBAL_* dump to vendor code Date: Thu, 6 Aug 2026 15:33:27 +0530 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb10.amd.com (10.181.42.219) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|IA1PR12MB8078:EE_ X-MS-Office365-Filtering-Correlation-Id: 561e368b-f8a3-4025-457d-08def3a3c3d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|36860700016|82310400026|1800799024|13003099007|6133799003|10067099003|11063799006|56012099006|18002099003|22082099003|3023799007; X-Microsoft-Antispam-Message-Info: 8GchDt59lE+n+fVtbQ+LUqPBEgqOokgw58cb/xhWSp88Vr/aLAR2x2Nn7y98oh0OTfNx2bDXGIJP3zQXc5jnMZKQsnA9Hj0qnhZC2s3QCENrN/2QRB3T4zpANh8AbfrN3Hz/XuaoDDIA6H3tFj/1rS8ruJhGf0gcMKB/iA0uuo1uOUBnCih8ADk01Dv8qVgKFvW11GBeeH2onjtUZQa5iMJIOg3tBDaffFILw18vNSQmzfhdhNMinchfABLZof3oG0dngaocDMoFfYN182Baw/xG5WgWvfW5JPIHINPRW6Sa5RRR4Q3BeA7UTb+1S6O9157RY4t6icU5afjcgjbuvvVsU+If8YRL8oLCKUPL0zi36wrYiKagBiui+wLGWAndnDkJFq5v+XfdXSt/j9QMc/R8SVy0HdjaVX7nQ/kxXEqh/f4wT4akQjKooym3/+E2aQ0d2s/yfy4jGTFIE2m6DY2wvleXpc7W5b4xbFDhYdLDX5NkAgJExLNuH+vBDEWsnzFZm6bGUajtEYp9t3HoTRSP3PQI/vcdEvUPDyvMOfILAYQigdgkrhfTrqWyBSJYwhwEErpkf2Gq+XXg+fA6vaZUwd4bKd3x5K3GCN8Baosjj/NqABDnYE3sYQFv4dW4gA5zuH6/+DYGFbch13DM7WXweLomx4UW7xQ7+xUlbF9lT9RmrZvI0nAyMV8arP4VwalhW+dyjdNn/UlRaXI2xg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(23010399003)(36860700016)(82310400026)(1800799024)(13003099007)(6133799003)(10067099003)(11063799006)(56012099006)(18002099003)(22082099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sTpCI7c2CZvZqAKBnitzmcMpnpeMcTbsmcbjlNuhV4TIl9Cj05PmIT8Q83Od1WHG23/52VYhFWA13c9XcbXWv99ZZy4w1YUmNZtfjehObYjBuUNhvUOSZlVGV9uFoJSvDSU/5OxY85S87IOGlfcZt57UiVC1CgFh/J6E36z/kVHgm9xDxvKFirKEvG1x3OqTvxCYv0I2w15onUmFR0NCDb3yIUFGuRFIILD2FVqrYgaZKFe/5y82KdJfhqwY77C8+6P3KxwFmUS+8iVeycSeq2RdISbj3ly5JbhbPn8fy9VN7ktNjUQnNhSXrFfCfgtL/jWR7CgW3CZdN4YqWrIm/3G6pkllf5lHhTzMmNWgP+2+kqu31NGl4uVmfb+tHexTNZ4Rca9Uv5QlWlmAS9kN/rTaKNnFoAANFLbmqOTJ82KeRMwvpu9zR1wurOECbel5 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 10:16:22.3111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 561e368b-f8a3-4025-457d-08def3a3c3d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8078 Content-Type: text/plain; charset="utf-8" MSR_CORE_PERF_GLOBAL_{CTRL,STATUS} and MSR_ARCH_PERFMON_FIXED_CTR_CTRL are Intel Architectural PerfMon registers that are not available on AMD processors. Since commit 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support"), x86_pmu.version is also set to 2 on AMD processors that support PerfMonV2, which makes perf_event_print_debug() attempt to read these non-existent MSRs. The resulting #GP is caught by the exception fixup, but as the reads are unchecked, SysRq-P logs an "unchecked MSR access error" for each one and then prints zeroes as if they were valid register contents. Implement x86_pmu::print_debug for the Intel and Zhaoxin PMUs, which do have these registers, and drop the reads from common code. Both are wired up through PMU descriptors that are selected only when the PMU version is at least 2, so the version check is no longer needed. MSR_CORE_PERF_GLOBAL_OVF_CTRL is also dropped from the dump since it is write-to-clear and does not read back the overflow state. Fixes: 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support") Reported-by: Petr Tesarik Closes: https://lore.kernel.org/all/20260717150315.2868314-1-ptesarik@suse.= com/ Cc: stable@vger.kernel.org Signed-off-by: Sandipan Das --- arch/x86/events/core.c | 29 +++-------------------------- arch/x86/events/intel/core.c | 32 ++++++++++++++++++++++++++++++++ arch/x86/events/zhaoxin/core.c | 18 ++++++++++++++++++ 3 files changed, 53 insertions(+), 26 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 17dc53a62378..7511197579fd 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1559,38 +1559,15 @@ static void x86_pmu_start(struct perf_event *event,= int flags) =20 void x86_pmu_print_debug(int cpu) { - u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; unsigned long *cntr_mask, *fixed_cntr_mask; - struct event_constraint *pebs_constraints; + u64 pmc_ctrl, pmc_count, prev_left; struct cpu_hw_events *cpuc; - u64 pebs, debugctl; - int cpu, idx; + int idx; =20 cpuc =3D &per_cpu(cpu_hw_events, cpu); cntr_mask =3D hybrid(cpuc->pmu, cntr_mask); fixed_cntr_mask =3D hybrid(cpuc->pmu, fixed_cntr_mask); - pebs_constraints =3D hybrid(cpuc->pmu, pebs_constraints); - - if (x86_pmu.version >=3D 2) { - rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); - rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); - rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); - rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); - - pr_info("\n"); - pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); - pr_info("CPU#%d: status: %016llx\n", cpu, status); - pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); - pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); - if (pebs_constraints) { - rdmsrq(MSR_IA32_PEBS_ENABLE, pebs); - pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); - } - if (x86_pmu.lbr_nr) { - rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); - pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); - } - } + pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); =20 for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) { diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b39c6ce0efb5..e1ed0e173d0c 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3736,6 +3736,36 @@ static void intel_pmu_reset(void) local_irq_restore(flags); } =20 +static void intel_pmu_print_debug(int cpu) +{ + struct event_constraint *pebs_constraints; + struct cpu_hw_events *cpuc; + u64 ctrl, status, fixed; + u64 pebs, debugctl; + + cpuc =3D &per_cpu(cpu_hw_events, cpu); + pebs_constraints =3D hybrid(cpuc->pmu, pebs_constraints); + + rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); + rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); + + pr_info("\n"); + pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); + pr_info("CPU#%d: status: %016llx\n", cpu, status); + pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); + if (pebs_constraints) { + rdmsrq(MSR_IA32_PEBS_ENABLE, pebs); + pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); + } + if (x86_pmu.lbr_nr) { + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); + pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); + } + + x86_pmu_print_debug(cpu); +} + /* * We may be running with guest PEBS events created by KVM, and the * PEBS records are logged into the guest's DS and invisible to host. @@ -6680,6 +6710,8 @@ static __initconst const struct x86_pmu intel_pmu =3D= { * counting SMM by default. */ .attr_freeze_on_smi =3D 1, + + .print_debug =3D intel_pmu_print_debug, }; =20 static __init void intel_clovertown_quirk(void) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index e506f677db57..cc447e228efb 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -288,6 +288,22 @@ static inline void zxc_pmu_ack_status(u64 ack) zhaoxin_pmu_disable_all(); } =20 +static void zhaoxin_pmu_print_debug(int cpu) +{ + u64 ctrl, status, fixed; + + rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); + rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); + + pr_info("\n"); + pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); + pr_info("CPU#%d: status: %016llx\n", cpu, status); + pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); + + x86_pmu_print_debug(cpu); +} + static void zhaoxin_pmu_disable_fixed(struct hw_perf_event *hwc) { int idx =3D hwc->idx - INTEL_PMC_IDX_FIXED; @@ -479,6 +495,8 @@ static const struct x86_pmu zhaoxin_pmu __initconst =3D= { =20 .format_attrs =3D zx_arch_formats_attr, .events_sysfs_show =3D zhaoxin_event_sysfs_show, + + .print_debug =3D zhaoxin_pmu_print_debug, }; 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Peter Anvin" , Petr Tesarik , Ravi Bangoria , Ananth Narayan , Sandipan Das Subject: [PATCH 3/3] perf/x86/amd: Implement x86_pmu::print_debug Date: Thu, 6 Aug 2026 15:33:28 +0530 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb10.amd.com (10.181.42.219) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|CH3PR12MB9252:EE_ X-MS-Office365-Filtering-Correlation-Id: 58c70ba7-cdcc-432d-b017-08def3a3c636 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|7416014|23010399003|13003099007|6133799003|56012099006|10067099003|18002099003|22082099003|11063799006|5023799004; X-Microsoft-Antispam-Message-Info: lQ+0rqw+3GLYuPDQBr2Ndt3xaZ96dE4f97otonoZvcPAvxhOU61sTsCxKSQLs3j129Dr8rQYDFXZXGz42sDWsPRirj4xR20U9aCram/QJGBfhTg+sOJQ+zSQneupzSLfGNrtISCqUVUkpYIgIXpCRPApSMCR3T7NYb3eaO4hDwZWYSoI+unpzMWnoxdC87Sa0/pRb49LlV81ovwDS73WOzIVTfq+myV8PBhkavnz9O6r8ZzFP/vo9tHugTVQWE2Qlp/QnbDwHc3Soifz2NUmxnFLuCjxCeNPdO8DQip39P5NFQL6K8ciD1gQsFMpYhPBNRvij6iqBD6dN1HyGQrMWKWZjgy62QftUXqb1u2DUciKmV+PNYL/v0BXUmZ9GMXXYFJnwkgQr+JCv/ONQA1J/w0PvmSL24ypKylZz0gmWpVfRZaCvJH4GpgO/ZjM7TimkDfGmxWb7KopyFlxnBrUEnNcS2pv4qloJg+yxSx9cv/9ku2TiPFC8fLXkS6bKQSJure2ejAYDYubyzrxUZ0AHGOq1Ik37i4PrG9Ijg9CfNgmbKkGM+/t/KIvMHXt0SbH+DaaX+h8rYS2Z+93RitM2KXRN+3reU18q1UJX9/ucyS2mMGectZEz3JBMGXuJC1uDBZbUm2eGp2yDu1y0rjQJrKRMB6X6/q0+aCTqWDT2vi3F0GqjmOH+fY8cwEwxZP+cm5AyoOVfoQhDGXAu1UUkA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(7416014)(23010399003)(13003099007)(6133799003)(56012099006)(10067099003)(18002099003)(22082099003)(11063799006)(5023799004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: acocvgCxbqX58vRIEuXN8HF+Vc6rmCvB4vPrqamhYlL/QhjE3w64Tn/gCYK49GZ4NGDVcH5r9E6Fpgz8UqEvIG4Jl6HjHIqXrNb5Pq5SHyKt4Q1ypQ+sbCnDzPM0snnlgFynw7fOatH4Rv0A7BKD5md1CTCrNgornVluRsLLap9FxzR44ZgpC8tsLgvpZIQmuKNMLdZPH2E5JATbtpt9rHT0Sya9IBxPpTveGuWj+KZ84TrJaDXsEycQ653QIMFSWfjA/9D0Obfc3BdkjvyUto7+hqwVL/D5T/Bbtr4nGbxn1GlzYBDo54SkI84/V03/A22RRnZpjO8glGfxWaaXVpUqhG5BOWh15mAV8Jx7Gr2MvQQqOOv7NvmBkZagSlnNicuf4BpBVx/wC6B88vkary0WLRD4IuhnloO/6aS8ru1PPYCgg4byvyYaS72BX1Uq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 10:16:26.2533 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58c70ba7-cdcc-432d-b017-08def3a3c636 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9252 Content-Type: text/plain; charset="utf-8" Implement x86_pmu::print_debug for PerfMonV2 capable processors to dump MSR_AMD64_PERF_CNTR_GLOBAL_{CTL,STATUS}, plus MSR_AMD_DBG_EXTN_CFG if LBR Extension Version 2 is available. Chain into x86_pmu_print_debug() afterwards to dump the event selectors and counters. MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_{CLR,SET} are left out since they are write-only. Fixes: 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support") Reported-by: Petr Tesarik Closes: https://lore.kernel.org/all/20260717150315.2868314-1-ptesarik@suse.= com/ Cc: stable@vger.kernel.org Signed-off-by: Sandipan Das Tested-by: Petr Tesarik --- arch/x86/events/amd/core.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index a787409f5a62..ecd648af81f7 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -841,6 +841,25 @@ static void amd_pmu_v2_disable_all(void) amd_pmu_check_overflow(); } =20 +static void amd_pmu_v2_print_debug(int cpu) +{ + u64 ctrl, status, debugextn; + + rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctrl); + rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status); + + pr_info("\n"); + pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); + pr_info("CPU#%d: status: %016llx\n", cpu, status); + + if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_V2)) { + rdmsrq(MSR_AMD_DBG_EXTN_CFG, debugextn); + pr_info("CPU#%d: debugextn: %016llx\n", cpu, debugextn); + } + + x86_pmu_print_debug(cpu); +} + DEFINE_STATIC_CALL_NULL(amd_pmu_branch_add, *x86_pmu.add); =20 static void amd_pmu_add_event(struct perf_event *event) @@ -1452,6 +1471,7 @@ static int __init amd_core_pmu_init(void) x86_pmu.disable_all =3D amd_pmu_v2_disable_all; x86_pmu.enable =3D amd_pmu_v2_enable_event; x86_pmu.handle_irq =3D amd_pmu_v2_handle_irq; + x86_pmu.print_debug =3D amd_pmu_v2_print_debug; static_call_update(amd_pmu_test_overflow, amd_pmu_test_overflow_status); } =20 --=20 2.53.0