From nobody Sat Oct 3 03:53:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29C7D1ACED5; Wed, 5 Aug 2026 15:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943270; cv=none; b=TGFdMQ3fojdO6vSHqZ+ulDBh+hO4pWVtSQaJf+aDg0Z1J3alS87lqU3yMoPzwnKu2oueBEKsHSFGltFps6RaGKoQszg81FX5mtT60QYfEHi608zv/QQl1WHSW49rlr/Rofd8ixfNY9nIKsl7UQUgvFuu5YQ+zazeJb9advgt498= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943270; c=relaxed/simple; bh=b/ioUMqrpQtpju97vaf3OSPM0DlD2QUKdDEN7m06sbY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dHc28DvscIOv6GMFqq/pd+MBXRbvkskdrH3ivyZD18UQKo8XE7UnbH6nD/RH1ep+yG7OqaNN9/CBffF91v4EWhn/u1YKPllH7RFSpVob90kiWBbXxoplaTDgZytLoWg4AOjvmYfPkNLxIxXXGBrbOHn2retllhfSg8d+iC0TMgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0A1D41F00A3A; Wed, 5 Aug 2026 15:21:04 +0000 (UTC) From: Geert Uytterhoeven To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Conor Dooley Subject: [PATCH v3 1/6] dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator Date: Wed, 5 Aug 2026 17:20:49 +0200 Message-ID: <7a33c99816c850faeec5c17532811faf78959a1d.1785941595.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for the Renesas R-Car X5H Clock Pulse Generator, and add binding definitions for a limited initial set of clocks. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Tested-by: Marek Vasut Acked-by: Conor Dooley --- v3: - Add Acked-by, v2: - Add Reviewed-by, Tested-by, - Drop preliminary, - Expand CPG acronym, - Drop R8A78000_CPG_MSOCK_PERW_BUS, - Add R8A78000_CPG_SGASYNCD8_PERW_BUS, to avoid holes in the SGASYNCDn_PERW_BUS sequence, - Drop firmware property. --- .../bindings/clock/renesas,r8a78000-cpg.yaml | 55 +++++++++++++++++++ .../dt-bindings/clock/renesas,r8a78000-cpg.h | 14 +++++ 2 files changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7800= 0-cpg.yaml create mode 100644 include/dt-bindings/clock/renesas,r8a78000-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.y= aml b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml new file mode 100644 index 0000000000000000..4e23bba334382346 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car X5H Clock Pulse Generator + +maintainers: + - Geert Uytterhoeven + +description: + The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillator= s, + PLL circuits, clock dividers and clock control circuits. It provides va= rious + clocks for other modules. + +properties: + compatible: + const: renesas,r8a78000-cpg + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: extal + - const: extalr + + '#clock-cells': + description: + The single clock specifier cell must be the clock number, as defined= in + . + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@c1320000 { + compatible =3D "renesas,r8a78000-cpg"; + reg =3D <0xc1320000 0x10000>; + clocks =3D <&extal_clk>, <&extalr_clk>; + clock-names =3D "extal", "extalr"; + #clock-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-= bindings/clock/renesas,r8a78000-cpg.h new file mode 100644 index 0000000000000000..7fd09a3fb353d952 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Glider bv + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ + +/* R-Car X5H Clock Pulse Generator Clocks */ + +#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0 +#define R8A78000_CPG_SGASYNCD8_PERW_BUS 1 +#define R8A78000_CPG_SGASYNCD16_PERW_BUS 2 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */ --=20 2.43.0 From nobody Sat Oct 3 03:53:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28765478859; Wed, 5 Aug 2026 15:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943274; cv=none; b=WRHujBs9xgfEt0gk9Op0hXNRx0xodLqxnVSaK8WCuOTwpnUzpT+EPVP6HXlxmPqmIMQ7aWEgUkwVLjFebc4/y0tqzXiaBSeraEBAjM0i48YqNB15swBOtzV8E46hhdbLySdGHB54dG2suaPJdN1Nb/geZHNRuY2H/5znscQGCr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943274; c=relaxed/simple; bh=TivlnZRdkebeAmAjJjT4n7r5quvXruztK8/+iVvyBLs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e4FUVZnsSz8feOrI/qNNXTtbE85PAPz1hr1A4W6kvjVNq9RpOuSgW3g/eTMWzZZyUxwCM7QGQctm7WeI/6SddzQkNbUKPQFnO+r5Kbx9c3bZq73LvQ/rMV06bjJg9sgDsQ62IrA8D1euaYx2EbR3peu/czt22F7WO5Q7C6LWis4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BB2A1F000E9; Wed, 5 Aug 2026 15:21:09 +0000 (UTC) From: Geert Uytterhoeven To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Conor Dooley Subject: [PATCH v3 2/6] dt-bindings: power: Document Renesas R-Car X5H Module Controller Date: Wed, 5 Aug 2026 17:20:50 +0200 Message-ID: <1173a3a32e818befa8d2ede0edda7aa1da82e549.1785941595.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Renesas R-Car X5H Module Controllers, and add binding definitions for power domains not backed by registers. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Acked-by: Conor Dooley --- v3: - Add Reviewed-by, Acked-by, v2: - Clarify the meaning of the two power domain cells and the reset cell, - Drop R8A78000_MDLC_PD_CMN, as CMN is backed by MDPG bits, - Expand MDLC acronym, - Add a comment stating that all R8A78000_MDLC_PD_* definitions are for always-on power domains, - Drop firmware property. --- .../bindings/power/renesas,r8a78000-mdlc.yaml | 61 +++++++++++++++++++ .../dt-bindings/power/renesas,r8a78000-mdlc.h | 15 +++++ 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/renesas,r8a7800= 0-mdlc.yaml create mode 100644 include/dt-bindings/power/renesas,r8a78000-mdlc.h diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.= yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml new file mode 100644 index 0000000000000000..1dba1e1b1c5b52d0 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/renesas,r8a78000-mdlc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car X5H Module Controller + +maintainers: + - Geert Uytterhoeven + +description: + Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provid= es + Power Gating for up to 64 Power Domains, and Module Standby and Reset fo= r up + to 256 modules in the Power Domain of each Module hierarchy. + +properties: + compatible: + const: renesas,r8a78000-mdlc + + reg: + maxItems: 1 + + '#power-domain-cells': + description: | + - The first power domain specifier cell is the power domain part, and + must be either the Module Power Domain Gating (MPDG) register index + (0x00-0x3f) from the datasheet, for power domains which are backed= by + MPDG bits and which can be controlled in that manner, or a Power + Domain number, as defined in + , for power domains whi= ch + are always on, and for which there are no MPDG bits to control the= m. + + - The second power domain specifier cell is the module standby part,= and + must be the module number (0x00-0xff), composed of the Module Syst= em + Reset (MSRES) register index in the high nibble, and the Module Re= set + Destination bitfield index in the low nibble. + const: 2 + + '#reset-cells': + description: + The single reset specifier cell must be the module number (0x00-0xff= ), + and thus identical to the second power domain specifier cell. + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + system-controller@c3060000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0xc3060000 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/power/renesas,r8a78000-mdlc.h b/include/dt= -bindings/power/renesas,r8a78000-mdlc.h new file mode 100644 index 0000000000000000..6f3d1ae23648e55b --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a78000-mdlc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Glider bv + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ + +/* R-Car X5H Module Controller Always-On Power Domains */ + +#define R8A78000_MDLC_PD_AON 0x40 +#define R8A78000_MDLC_PD_SCP 0x41 +#define R8A78000_MDLC_PD_APL 0x42 +#define R8A78000_MDLC_PD_ACL 0x43 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ */ --=20 2.43.0 From nobody Sat Oct 3 03:53:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D27477E51; Wed, 5 Aug 2026 15:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943278; cv=none; b=eL+ttS8d3STJgJgxN4aKh2c3DU0VeNh39yKrORuKZ/Vt4mBz5ka3JfvozMScjNXxLppdcNV0kBNS6uLivXDHAl/vuaj/Jt7OtHLXEgHZrTkOdygEUVF+dxYE7yt2CxVKCw8k/4b+nQxH2zQkZQzIbEZ1fbsjjLQ99bRl2UChB60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943278; c=relaxed/simple; bh=jstlG2uEpPXFK/GgJ2YPsn0an3lMBL0ZuVnngTY46hE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BIDvQ1WFDQoQNTrJXF8tzMf3ihe/AzIZ9hyEcJ44MztjHSP7cxvmuOazPMuRDRXLQzng6MNfpU0QNbqCi0e7dLjSTF3BjBBUvoN19Bfs7uPEgfoZzjoOpFjNWMkLfQaRF+0cdxlm6Zse9Jc5G9JjOkrPFuSKEZGlUlIeYYwFdwM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 756421F00A3A; Wed, 5 Aug 2026 15:21:13 +0000 (UTC) From: Geert Uytterhoeven To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 3/6] clk: renesas: Add R-Car X5H CPG driver Date: Wed, 5 Aug 2026 17:20:51 +0200 Message-ID: <3f981753722de1ba871667be63460e89d299d635.1785941595.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a minimal Clock Pulse Generator driver for the R-Car X5H (R8A78000) SoC. For now this supports just the few fixed-rate clocks that are needed by the current minimal DTS. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut --- v3: - Add fixed-rate clocks to kerneldoc of r8a78000_cpg_priv.map, - Use devm_clk_hw_register_fixed_rate(), drop unregister_fixed_clks(), - Drop fill_clk_map(), as it is not really needed until SCMI remapping support is added later, - Replace by more specific in v7.2-rc2, v2: - Spin off from "clk: renesas: Add R-Car X5H CPG SCMI remapping driver", - Add default support not using SCMI, - Drop all SCMI remapping support, - Document use of -1 as a sentinel, - Document use of FIXED_CLK() IDs. --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a78000-cpg.c | 166 +++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 drivers/clk/renesas/r8a78000-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 0203ecbb38825f13..f0482bdfc4616cfa 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -34,6 +34,7 @@ config CLK_RENESAS select CLK_R8A779F0 if ARCH_R8A779F0 select CLK_R8A779G0 if ARCH_R8A779G0 select CLK_R8A779H0 if ARCH_R8A779H0 + select CLK_R8A78000 if ARCH_R8A78000 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 @@ -176,6 +177,9 @@ config CLK_R8A779H0 bool "R-Car V4M clock support" if COMPILE_TEST select CLK_RCAR_GEN4_CPG =20 +config CLK_R8A78000 + bool "R-Car X5H clock support" if COMPILE_TEST + config CLK_R9A06G032 bool "RZ/N1D clock support" if COMPILE_TEST =20 diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index bd2bed91ab291d72..4f76f8c402ffe9a3 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) +=3D r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) +=3D r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779G0) +=3D r8a779g0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779H0) +=3D r8a779h0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A78000) +=3D r8a78000-cpg.o obj-$(CONFIG_CLK_R9A06G032) +=3D r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G043) +=3D r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) +=3D r9a07g044-cpg.o diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78= 000-cpg.c new file mode 100644 index 0000000000000000..7946f9d0b423def1 --- /dev/null +++ b/drivers/clk/renesas/r8a78000-cpg.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car X5H Clock Pulse Generator + * + * Copyright (C) 2026 Glider bv + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct clk_map { + int dt_id; /* DT binding clock ID or -1 sentinel */ + u32 fw_id; /* FIXED_CLK() ID */ +}; + +enum fixed_clk { + FIXED_CLK_66M, + FIXED_CLK_266M, + NUM_FIXED_CLKS +}; + +static const unsigned long fixed_clk_rates[NUM_FIXED_CLKS] =3D { + [FIXED_CLK_66M] =3D 66666000, + [FIXED_CLK_266M] =3D 266660000, +}; + +#define FIXED_CLK(rate) FIXED_CLK_ ## rate + +/** + * struct r8a78000_cpg_priv - Clock Pulse Generator Private Data + * + * @dev: CPG device + * @map: Mapping from DT clock IDs to fixed-rate clocks + * @fixed_hws: Fixed rate clocks + */ +struct r8a78000_cpg_priv { + struct device *dev; + const struct clk_map *map; + struct clk_hw *fixed_hws[NUM_FIXED_CLKS]; +}; + +static const struct clk_map *clk_map_find(const struct clk_map *map, u32 i= d) +{ + if (!map) + return NULL; + + for (; map->dt_id >=3D 0; map++) { + if (map->dt_id =3D=3D id) + return map; + } + + return NULL; +} + +static struct clk_hw *r8a78000_clk_get(struct of_phandle_args *spec, + void *data) +{ + struct r8a78000_cpg_priv *priv =3D data; + struct device *dev =3D priv->dev; + const struct clk_map *map; + struct clk_hw *hw; + u32 id; + + if (spec->args_count !=3D 1) + return ERR_PTR(-EINVAL); + + id =3D spec->args[0]; + + map =3D clk_map_find(priv->map, id); + if (!map) { + dev_err(dev, "Unknown clock %u\n", id); + return ERR_PTR(-ENOENT); + } + + dev_dbg(dev, "Mapping DT clock %u to fixed clock %u\n", id, map->fw_id); + + hw =3D priv->fixed_hws[map->fw_id]; + + dev_dbg(dev, "clock %u is %s at %lu Hz\n", id, clk_hw_get_name(hw), + clk_hw_get_rate(hw)); + + return hw; +} + +static int register_fixed_clks(struct r8a78000_cpg_priv *priv) +{ + struct device *dev =3D priv->dev; + unsigned long rate; + struct clk_hw *hw; + const char *name; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(fixed_clk_rates); i++) { + rate =3D fixed_clk_rates[i]; + name =3D devm_kasprintf(dev, GFP_KERNEL, "cpg-%lu", rate); + if (!name) + return -ENOMEM; + + hw =3D devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed_hws[i] =3D hw; + } + + return 0; +} + +static int r8a78000_cpg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct r8a78000_cpg_priv *priv; + const struct clk_map *map; + int ret; + + map =3D of_device_get_match_data(dev); + if (!map) + return -ENODEV; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->map =3D map; + + ret =3D register_fixed_clks(priv); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, r8a78000_clk_get, priv); +} + +static const struct clk_map r8a78000_cpg_default[] =3D { + { R8A78000_CPG_SGASYNCD4_PERW_BUS, FIXED_CLK(266M) }, + { R8A78000_CPG_SGASYNCD16_PERW_BUS, FIXED_CLK(66M) }, + { -1 } +}; + +static const struct of_device_id r8a78000_cpg_match[] =3D { + { + .compatible =3D "renesas,r8a78000-cpg", + .data =3D &r8a78000_cpg_default, + }, + { /* sentinel */ } +}; + +static struct platform_driver r8a78000_cpg_driver =3D { + .probe =3D r8a78000_cpg_probe, + .driver =3D { + .name =3D "r8a78000-cpg", + .of_match_table =3D r8a78000_cpg_match, + .suppress_bind_attrs =3D true, + }, +}; + +builtin_platform_driver(r8a78000_cpg_driver) + +MODULE_DESCRIPTION("R-Car X5H CPG Driver"); --=20 2.43.0 From nobody Sat Oct 3 03:53:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A25477E51; Wed, 5 Aug 2026 15:21:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943282; cv=none; b=EgIMfxn2P62eO0pFPKkA1ncT+GrDgi89rhuw1RifclSS856P5Nya3ff+mW1dvj8mQwj/wL0zeC0nfqk8u7rPBwYa0snV66mswySjOYKgfKYnP3jyq1mDRtGHeCBu9QygNe82d6TitvGr5X/EGPcJh3G5g5v8uMftOaX3sQapxIc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943282; c=relaxed/simple; bh=t6yLzGGXXrhB5hoGTwyQoIva2UQzCuHjc1rb7pSwjQQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m9zWzS0+v4mOnmMzlEvMG246V4DWAMC80hdiYhYVRaEXa0syq17bVQ2Z7C9sz6JT+Ws2CB12U98hHmALRlir13pZDbLSBnHuhhd6nXzTw8qwOVzyf99JPEO5vU9aUvg0hDb0YVlXmTSpWoEf3rSG3K09QlCZFbbPHF6oL4Ve4ho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 759041F000E9; Wed, 5 Aug 2026 15:21:17 +0000 (UTC) From: Geert Uytterhoeven To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver Date: Wed, 5 Aug 2026 17:20:52 +0200 Message-ID: <89e6a71b35703f10e12f520af1f389b5f40f4b35.1785941595.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a minimal Module Controller driver for the R-Car X5H (R8A78000) SoC. For now this just supports the always-on power domains, and dummy module clocks and resets for the serial console (which is enabled by the boot loader). Signed-off-by: Geert Uytterhoeven --- v3: - Replace by more specific in v7.2-rc2, - Add a comment to document only always-on domains are supported, - Consistently use /* sentinel */ for zero sentinels, - Drop trailing commas from sentinels, v2: - Spin off from "pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping driver", - Add default support not using SCMI, - Drop all SCMI remapping support, - Document use of -1 as a sentinel, - Rename struct r8a78000_mdlc_info to mdlc_info, - Print HW IDs in hexadecimal, - Reduce log level for unsupported MDLC instances from warn to dbg, --- drivers/pmdomain/renesas/Kconfig | 4 + drivers/pmdomain/renesas/Makefile | 1 + drivers/pmdomain/renesas/r8a78000-mdlc.c | 330 +++++++++++++++++++++++ drivers/soc/renesas/Kconfig | 1 + 4 files changed, 336 insertions(+) create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kc= onfig index b507c3e0d723efc6..f2f52d3c29a083f1 100644 --- a/drivers/pmdomain/renesas/Kconfig +++ b/drivers/pmdomain/renesas/Kconfig @@ -13,6 +13,10 @@ config SYSC_RMOBILE bool "System Controller support for R-Mobile" if COMPILE_TEST =20 # SoC +config MDLC_R8A78000 + bool "Module Controller support for R8A78000 (R-Car X5H)" if COMPILE_TEST + select RESET_CONTROLLER + config SYSC_R8A7742 bool "System Controller support for R8A7742 (RZ/G1H)" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/M= akefile index 0391e6e67440a786..17849aad37a5ac4f 100644 --- a/drivers/pmdomain/renesas/Makefile +++ b/drivers/pmdomain/renesas/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # SoC +obj-$(CONFIG_MDLC_R8A78000) +=3D r8a78000-mdlc.o obj-$(CONFIG_SYSC_R8A7742) +=3D r8a7742-sysc.o obj-$(CONFIG_SYSC_R8A7743) +=3D r8a7743-sysc.o obj-$(CONFIG_SYSC_R8A7745) +=3D r8a7745-sysc.o diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/re= nesas/r8a78000-mdlc.c new file mode 100644 index 0000000000000000..5c8acead7cff9bdd --- /dev/null +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car X5H Module Controller + * + * Copyright (C) 2026 Glider bv + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct mod_map { + int hw_id; /* Hardware module ID or -1 sentinel */ +}; + +struct mdlc_info { + u32 base; + const struct mod_map *mod_map; +}; + +/** + * struct r8a78000_mdlc_priv - Module Controller Private Data + * + * @link: Link into list of MDLC instances + * @genpd_data: PM domain provider data + * @rcdev: Reset controller entity + * @dev: MDLC device + * @np: Device node in DT representing the MDLC + * @mod_map: Mapping from hardware module IDs + */ +struct r8a78000_mdlc_priv { + struct hlist_node link; + struct genpd_onecell_data genpd_data; + struct reset_controller_dev rcdev; + struct device *dev; + struct device_node *np; + const struct mod_map *mod_map; +}; + +static struct generic_pm_domain *r8a78000_genpd_always_on; +static HLIST_HEAD(r8a78000_mdlc_list); +static DEFINE_MUTEX(r8a78000_mdlc_lock); /* protects the two above */ + +static struct generic_pm_domain *r8a78000_genpd_xlate( + const struct of_phandle_args *spec, void *data) +{ + struct r8a78000_mdlc_priv *priv =3D container_of(data, + struct r8a78000_mdlc_priv, genpd_data); + struct device *dev =3D priv->dev; + u32 id; + + if (spec->args_count !=3D 2) + return ERR_PTR(-EINVAL); + + id =3D spec->args[0]; + + if (id >=3D R8A78000_MDLC_PD_AON) { + dev_dbg(dev, + "Mapping HW power domain 0x%x to always-on domain\n", + id); + return r8a78000_genpd_always_on; + } + + /* For now only always-on domains are supported */ + dev_err(dev, "Unknown power domain 0x%x\n", id); + return ERR_PTR(-ENOENT); +} + +#define rcdev_to_priv(_rcdev) \ + container_of(_rcdev, struct r8a78000_mdlc_priv, rcdev) + +static const struct mod_map *mod_map_find(const struct mod_map *map, u32 i= d) +{ + if (!map) + return NULL; + + for (; map->hw_id >=3D 0; map++) { + if (map->hw_id =3D=3D id) + return map; + } + + return NULL; +} + +static int r8a78000_mdlc_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *spec) +{ + struct r8a78000_mdlc_priv *priv =3D rcdev_to_priv(rcdev); + struct device *dev =3D priv->dev; + const struct mod_map *map; + u32 id; + + if (spec->args_count !=3D 1) + return -EINVAL; + + id =3D spec->args[0]; + + map =3D mod_map_find(priv->mod_map, id); + if (!map) { + dev_err(dev, "Unknown reset 0x%x\n", id); + return -ENOENT; + } + + dev_dbg(dev, "Ignoring HW reset 0x%x\n", id); + return id; +} + +#define DEFINE_MDLC_RESET_WRAPPER(op) \ + static int r8a78000_mdlc_ ## op(struct reset_controller_dev *rcdev, \ + unsigned long id) \ + { \ + struct r8a78000_mdlc_priv *priv =3D rcdev_to_priv(rcdev); \ + \ + dev_dbg(priv->dev, "%s: Ignoring\n", __func__); \ + return 0; \ + } + +DEFINE_MDLC_RESET_WRAPPER(reset) +DEFINE_MDLC_RESET_WRAPPER(assert) +DEFINE_MDLC_RESET_WRAPPER(deassert) +DEFINE_MDLC_RESET_WRAPPER(status) + +static const struct reset_control_ops r8a78000_mdlc_reset_ops =3D { + .reset =3D r8a78000_mdlc_reset, + .assert =3D r8a78000_mdlc_assert, + .deassert =3D r8a78000_mdlc_deassert, + .status =3D r8a78000_mdlc_status, +}; + +static int r8a78000_mdlc_attach_dev(struct generic_pm_domain *domain, + struct device *dev) +{ + struct device_node *np =3D dev->of_node; + struct r8a78000_mdlc_priv *priv; + struct of_phandle_args pd_spec; + const struct mod_map *map; + unsigned int id; + int ret; + + ret =3D of_parse_phandle_with_args(np, "power-domains", + "#power-domain-cells", 0, &pd_spec); + if (ret < 0) + return ret; + + if (pd_spec.args_count !=3D 2) { + of_node_put(pd_spec.np); + return -EINVAL; + } + + scoped_guard(mutex, &r8a78000_mdlc_lock) { + hlist_for_each_entry(priv, &r8a78000_mdlc_list, link) { + if (priv->np =3D=3D pd_spec.np) + break; + } + } + + if (!priv) { + dev_err(dev, "%s: MDLC %pOF not found\n", __func__, pd_spec.np); + of_node_put(pd_spec.np); + return -ENODEV; + } + + id =3D pd_spec.args[1]; + of_node_put(pd_spec.np); + + map =3D mod_map_find(priv->mod_map, id); + if (!map) { + dev_err(dev, "Unknown module 0x%x\n", id); + return -ENOENT; + } + + dev_dbg(dev, "Ignoring HW module 0x%x\n", id); + return 0; +} + +static void r8a78000_mdlc_unlink(void *data) +{ + struct r8a78000_mdlc_priv *priv =3D data; + + scoped_guard(mutex, &r8a78000_mdlc_lock) { + hlist_del(&priv->link); + } +} + +static void r8a78000_genpd_del_provider(void *data) +{ + of_genpd_del_provider(data); +} + +static int r8a78000_genpd_always_on_singleton(struct device *dev) +{ + struct generic_pm_domain *genpd; + int ret; + + guard(mutex)(&r8a78000_mdlc_lock); + + if (r8a78000_genpd_always_on) + return 0; + + genpd =3D kzalloc_obj(*genpd); + if (!genpd) + return -ENOMEM; + + genpd->name =3D "always-on"; + genpd->attach_dev =3D r8a78000_mdlc_attach_dev; + + ret =3D pm_genpd_init(genpd, &pm_domain_always_on_gov, false); + if (ret) { + kfree(genpd); + return dev_err_probe(dev, ret, + "Failed to create always-on domain\n"); + } + + r8a78000_genpd_always_on =3D genpd; + return 0; +} + +static int r8a78000_mdlc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct r8a78000_mdlc_priv *priv; + const struct mdlc_info *info; + struct resource *res; + int ret; + + ret =3D r8a78000_genpd_always_on_singleton(dev); + if (ret) + return ret; + + info =3D of_device_get_match_data(dev); + if (!info) + return -ENODEV; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->np =3D np; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + for (; info->base; info++) { + if (info->base =3D=3D res->start) + break; + } + + if (!info->base) { + dev_dbg(dev, "Unsupported MDLC instance 0x%pa\n", &res->start); + return -ENODEV; + } + + priv->mod_map =3D info->mod_map; + + scoped_guard(mutex, &r8a78000_mdlc_lock) { + hlist_add_head(&priv->link, &r8a78000_mdlc_list); + } + + ret =3D devm_add_action_or_reset(dev, r8a78000_mdlc_unlink, priv); + if (ret) + return dev_err_probe(dev, ret, "failed to add action\n"); + + /* Note that no actual domains are registered, just need translation */ + priv->genpd_data.xlate =3D r8a78000_genpd_xlate; + ret =3D of_genpd_add_provider_onecell(np, &priv->genpd_data); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register genpd provider\n"); + + ret =3D devm_add_action_or_reset(dev, r8a78000_genpd_del_provider, np); + if (ret) + return dev_err_probe(dev, ret, + "failed to add unregister action\n"); + + priv->rcdev.ops =3D &r8a78000_mdlc_reset_ops; + priv->rcdev.of_node =3D np; + priv->rcdev.of_reset_n_cells =3D 1; + priv->rcdev.of_xlate =3D r8a78000_mdlc_reset_xlate; + + ret =3D devm_reset_controller_register(dev, &priv->rcdev); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register reset controller\n"); + + return 0; +} + +static const struct mod_map r8a78000_mdlc_perw_mod_default[] =3D { + { 0x54 }, /* HSCIF0 */ + { -1 } +}; + +static const struct mdlc_info r8a78000_mdlc_default[] =3D { + { + .base =3D 0xc05d0000 /* mdlc_perw */, + .mod_map =3D r8a78000_mdlc_perw_mod_default, + }, + { /* sentinel */ } +}; + +static const struct of_device_id r8a78000_mdlc_match[] =3D { + { + .compatible =3D "renesas,r8a78000-mdlc", + .data =3D &r8a78000_mdlc_default, + }, + { /* sentinel */ } +}; + +static struct platform_driver r8a78000_mdlc_driver =3D { + .probe =3D r8a78000_mdlc_probe, + .driver =3D { + .name =3D "r8a78000-mdlc", + .of_match_table =3D r8a78000_mdlc_match, + .suppress_bind_attrs =3D true, + }, +}; + +builtin_platform_driver(r8a78000_mdlc_driver) + +MODULE_DESCRIPTION("R-Car X5H MDLC Driver"); diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fdf18ed2dfc2186d..eb8ac0d47d9d42b1 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -357,6 +357,7 @@ config ARCH_R8A78000 bool "ARM64 Platform support for R8A78000 (R-Car X5H)" default y if ARCH_RENESAS select ARCH_RCAR_GEN5 + select MDLC_R8A78000 help This enables support for the Renesas R-Car X5H SoC. =20 --=20 2.43.0 From nobody Sat Oct 3 03:53:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9397A47A0A6; Wed, 5 Aug 2026 15:21:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943287; cv=none; b=tBDjWga3YGVaAPmSeftzVA/W95NLyrHlf9DiLDx3WFQAcvasskh9HFXesZGJuklVrUwDX+qo9dpPGyVlRvswfqNVOwBKXEq/EXxz+ro3wVkydqAYkWc8uvRuFsvzp4m+3YJNPiJ6n66Gr+CdlS0wP/grdKqHHWBNmHU6cIjh4ME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943287; c=relaxed/simple; bh=RjWouVeZQ0p/bM745k8tn8+4irmInNRdnKF8icW7XlY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nXmxHNNBMxbIZTpEWurad/+PBJd3b120lIBtcpK8IA9y62zRQa3j3HhcYpNgXszSSLAqp5IukVYAScqbb4SacEgre833cprkzwCnHsmLW7MpVkghvMbOJ19eTe96v+kkjdFvUN+8SZgvH0jrBUnFR5ZKa881PWWL3EYYBFCdfk8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7736B1F00A3A; Wed, 5 Aug 2026 15:21:21 +0000 (UTC) From: Geert Uytterhoeven To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 5/6] arm64: dts: renesas: r8a78000: Add CPG node Date: Wed, 5 Aug 2026 17:20:53 +0200 Message-ID: <03a40ce94e01a5a390493b8c711c299d328a2db3.1785941595.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a device node for the Clock Pulse Generator (CPG) on the R-Car X5H (R8A78000) SoC. Convert all (H)SCIF serial ports from dummy to CPG clocks, removing the need for any dummy clocks. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut --- v3: - Add Reviewed-by, v2: - Split in separate CPG and MDLC patches. --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 59 +++++++++++++---------- 1 file changed, 34 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dt= s/renesas/r8a78000.dtsi index fb71974ef390509d..1fe078c7822c01a5 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ =20 +#include #include =20 / { @@ -668,23 +669,6 @@ L3_CA720_7: cache-controller-37 { }; }; =20 - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <266660000>; - }; - extal_clk: extal-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -882,7 +866,9 @@ scif0: serial@c0700000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc0700000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -892,7 +878,9 @@ scif1: serial@c0704000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc0704000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -902,7 +890,9 @@ scif3: serial@c0708000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc0708000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -912,7 +902,9 @@ scif4: serial@c070c000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc070c000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -922,7 +914,9 @@ hscif0: serial@c0710000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc0710000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -932,7 +926,9 @@ hscif1: serial@c0714000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc0714000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -942,7 +938,9 @@ hscif2: serial@c0718000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc0718000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -952,7 +950,9 @@ hscif3: serial@c071c000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc071c000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; status =3D "disabled"; }; @@ -965,6 +965,15 @@ stcm_transport: sram@c1060000 { ranges =3D <0 0x0 0xc1060000 0x1c00>; /* actual transport nodes must be set per board file */ }; + + cpg: clock-controller@c1320000 { + compatible =3D "renesas,r8a78000-cpg"; + reg =3D <0 0xc1320000 0 0x10000>; + clocks =3D <&extal_clk>, <&extalr_clk>; + clock-names =3D "extal", "extalr"; + #clock-cells =3D <1>; + bootph-all; + }; }; =20 timer { --=20 2.43.0 From nobody Sat Oct 3 03:53:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E8F4420475; Wed, 5 Aug 2026 15:21:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943290; cv=none; b=sAZypnFIltG1vItDnnrAuFCRaM7geeo4hqIaBpkYVOX4hJ1yh7fOgGsZ1ONV9cOB9wlNr6R7QL31Py1qvf22WvUX44IEBIdS5AST8qaOBbKOn4wXIM7hHR0IA9tVk7SIJlVbXrrEMiBFDbC1nKehC1QNN2FUoLr3G3JvAnothOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785943290; c=relaxed/simple; bh=I0J+MWKiWSED1BqPpMHg3NeQTQNNwiOeUyWs5x1YkOs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gBoipKSnzz+HvSkMTh5BygrGU/58MfxdmoZKtCtCVYRxTeA+bfUaYZ04CfqGoKnVUmxPAQwTdzGmv2OMinhwlkhJZA61os786J9i5aEPID2JMUemHbOp+cdrCnp7Tj45mt31BjgL6ixUvT1i5rulxllDOhX4MMHp+BRCZdLBwhY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F2B11F00A3D; Wed, 5 Aug 2026 15:21:25 +0000 (UTC) From: Geert Uytterhoeven To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 6/6] arm64: dts: renesas: r8a78000: Add MDLC nodes Date: Wed, 5 Aug 2026 17:20:54 +0200 Message-ID: <9b7f96352ef5fe08e7003169710a9af874fccb68.1785941595.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for the Module Control (MDLC) blocks on the R-Car X5H (R8A78000) SoC. Complete hardware desciption of all (H)SCIF serial ports, by linking them to an MDLC for power domains and resets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut --- v3: - Add Reviewed-by, - Sort MDLC nodes (alphabetically, by label), v2: - Split in separate CPG and MDLC patches. --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 241 ++++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dt= s/renesas/r8a78000.dtsi index 1fe078c7822c01a5..9a07753b221541ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include =20 / { @@ -870,6 +871,8 @@ scif0: serial@c0700000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x40>; + resets =3D <&mdlc_perw 0x40>; status =3D "disabled"; }; =20 @@ -882,6 +885,8 @@ scif1: serial@c0704000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x41>; + resets =3D <&mdlc_perw 0x41>; status =3D "disabled"; }; =20 @@ -894,6 +899,8 @@ scif3: serial@c0708000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x42>; + resets =3D <&mdlc_perw 0x42>; status =3D "disabled"; }; =20 @@ -906,6 +913,8 @@ scif4: serial@c070c000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x43>; + resets =3D <&mdlc_perw 0x43>; status =3D "disabled"; }; =20 @@ -918,6 +927,8 @@ hscif0: serial@c0710000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x54>; + resets =3D <&mdlc_perw 0x54>; status =3D "disabled"; }; =20 @@ -930,6 +941,8 @@ hscif1: serial@c0714000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x55>; + resets =3D <&mdlc_perw 0x55>; status =3D "disabled"; }; =20 @@ -942,6 +955,8 @@ hscif2: serial@c0718000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x56>; + resets =3D <&mdlc_perw 0x56>; status =3D "disabled"; }; =20 @@ -954,6 +969,8 @@ hscif3: serial@c071c000 { <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x57>; + resets =3D <&mdlc_perw 0x57>; status =3D "disabled"; }; =20 @@ -974,6 +991,230 @@ cpg: clock-controller@c1320000 { #clock-cells =3D <1>; bootph-all; }; + + mdlc_aon: system-controller@c1338000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1338000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_cmnn: system-controller@ca410000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xca410000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_cmns: system-controller@ca510000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xca510000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr0: system-controller@e8000000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8000000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr1: system-controller@e8080000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8080000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr2: system-controller@e8100000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8100000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr3: system-controller@e8180000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8180000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr4: system-controller@e8200000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8200000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr5: system-controller@e8280000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8280000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr6: system-controller@e8300000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8300000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr7: system-controller@e8380000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8380000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_dsp: system-controller@cbe90000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xcbe90000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_gpc: system-controller@cb510000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xcb510000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_hscn: system-controller@c9c90000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc9c90000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_hscs: system-controller@de200000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xde200000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_imn: system-controller@c1990000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1990000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ims: system-controller@c1d90000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1d90000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_mm: system-controller@e9980000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe9980000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_npu0: system-controller@d2c30000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xd2c30000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_npu1: system-controller@d6c30000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xd6c30000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_pere: system-controller@c08f0000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc08f0000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_perw: system-controller@c05d0000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc05d0000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_rt: system-controller@19440000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0x19440000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_scp: system-controller@c1330000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1330000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_top: system-controller@c6480000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc6480000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_vio: system-controller@c5000000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc5000000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_vipn: system-controller@c3060000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc3060000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_vips: system-controller@c3460000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc3460000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; }; =20 timer { --=20 2.43.0